3 #include <linux/types.h>
4 #include <linux/delay.h> /* udelay */
10 #include "vb_setmode.h"
17 static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
19 static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
20 { 2, 13, 9, 64, 0x45},
21 { 2, 12, 9, 32, 0x35},
22 { 2, 12, 8, 16, 0x31},
23 { 2, 11, 8, 8, 0x21} };
25 static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
26 { 2, 14, 11, 128, 0x5D},
27 { 2, 14, 10, 64, 0x59},
28 { 2, 13, 11, 64, 0x4D},
29 { 2, 14, 9, 32, 0x55},
30 { 2, 13, 10, 32, 0x49},
31 { 2, 12, 11, 32, 0x3D},
32 { 2, 14, 8, 16, 0x51},
33 { 2, 13, 9, 16, 0x45},
34 { 2, 12, 10, 16, 0x39},
37 { 2, 12, 8, 4, 0x31} };
39 static int XGINew_RAMType;
42 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
43 struct vb_device_info *pVBInfo)
45 unsigned char data, temp;
47 if (HwDeviceExtension->jChipType < XG20) {
48 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
49 data = *pVBInfo->pSoftSetting & 0x07;
52 data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
54 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
58 } else if (HwDeviceExtension->jChipType == XG27) {
59 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
60 data = *pVBInfo->pSoftSetting & 0x07;
63 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
64 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
65 if ((temp & 0x88) == 0x80)
70 } else if (HwDeviceExtension->jChipType == XG21) {
71 /* Independent GPIO control */
72 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
74 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
75 /* GPIOF 0:DVI 1:DVO */
76 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
78 /* for current XG20 & XG21, GPIOH is floating, driver will
79 * fix DDR temporarily */
80 if (temp & 0x01) /* DVI read GPIOH */
84 /* ~HOTPLUG_SUPPORT */
85 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
88 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
97 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
98 struct vb_device_info *pVBInfo)
100 xgifb_reg_set(P3c4, 0x18, 0x01);
101 xgifb_reg_set(P3c4, 0x19, 0x20);
102 xgifb_reg_set(P3c4, 0x16, 0x00);
103 xgifb_reg_set(P3c4, 0x16, 0x80);
105 if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
107 xgifb_reg_set(P3c4, 0x18, 0x00);
108 xgifb_reg_set(P3c4, 0x19, 0x20);
109 xgifb_reg_set(P3c4, 0x16, 0x00);
110 xgifb_reg_set(P3c4, 0x16, 0x80);
114 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
115 xgifb_reg_set(P3c4, 0x19, 0x01);
116 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);
117 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);
119 xgifb_reg_set(P3c4, 0x1B, 0x03);
121 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
122 xgifb_reg_set(P3c4, 0x19, 0x00);
123 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);
124 xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
125 xgifb_reg_set(P3c4, 0x1B, 0x00);
128 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
129 struct vb_device_info *pVBInfo)
132 xgifb_reg_set(pVBInfo->P3c4,
134 pVBInfo->MCLKData[XGINew_RAMType].SR28);
135 xgifb_reg_set(pVBInfo->P3c4,
137 pVBInfo->MCLKData[XGINew_RAMType].SR29);
138 xgifb_reg_set(pVBInfo->P3c4,
140 pVBInfo->MCLKData[XGINew_RAMType].SR2A);
142 xgifb_reg_set(pVBInfo->P3c4,
144 pVBInfo->ECLKData[XGINew_RAMType].SR2E);
145 xgifb_reg_set(pVBInfo->P3c4,
147 pVBInfo->ECLKData[XGINew_RAMType].SR2F);
148 xgifb_reg_set(pVBInfo->P3c4,
150 pVBInfo->ECLKData[XGINew_RAMType].SR30);
152 /* [Vicent] 2004/07/07,
153 * When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
154 /* [Hsuan] 2004/08/20,
155 * Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
156 * Set SR32 D[1:0] = 10b */
157 if (HwDeviceExtension->jChipType == XG42) {
158 if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C) &&
159 (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01) &&
160 (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C) &&
161 (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01)) ||
162 ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22) &&
163 (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))
164 xgifb_reg_set(pVBInfo->P3c4,
166 ((unsigned char) xgifb_reg_get(
167 pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
171 static void XGINew_DDRII_Bootup_XG27(
172 struct xgi_hw_device_info *HwDeviceExtension,
173 unsigned long P3c4, struct vb_device_info *pVBInfo)
175 unsigned long P3d4 = P3c4 + 0x10;
176 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
178 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
180 /* Set Double Frequency */
181 /* xgifb_reg_set(P3d4, 0x97, 0x11); *//* CR97 */
182 xgifb_reg_set(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
186 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
187 xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
188 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
190 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
193 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
194 xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
195 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
197 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
200 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
201 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
202 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
204 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
207 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
208 xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
209 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
211 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
212 xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
215 xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
217 xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
219 xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
220 xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
221 xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
224 xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
227 xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
228 xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
229 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
231 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
234 xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
235 xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
236 xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
238 xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
241 /* Set SR1B refresh control 000:close; 010:open */
242 xgifb_reg_set(P3c4, 0x1B, 0x04);
247 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
248 unsigned long P3c4, struct vb_device_info *pVBInfo)
250 unsigned long P3d4 = P3c4 + 0x10;
252 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
254 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
256 xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
259 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
260 xgifb_reg_set(P3c4, 0x19, 0x80);
261 xgifb_reg_set(P3c4, 0x16, 0x05);
262 xgifb_reg_set(P3c4, 0x16, 0x85);
264 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
265 xgifb_reg_set(P3c4, 0x19, 0xC0);
266 xgifb_reg_set(P3c4, 0x16, 0x05);
267 xgifb_reg_set(P3c4, 0x16, 0x85);
269 xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
270 xgifb_reg_set(P3c4, 0x19, 0x40);
271 xgifb_reg_set(P3c4, 0x16, 0x05);
272 xgifb_reg_set(P3c4, 0x16, 0x85);
274 /* xgifb_reg_set(P3c4, 0x18, 0x52); */ /* MRS1 */
275 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
276 xgifb_reg_set(P3c4, 0x19, 0x02);
277 xgifb_reg_set(P3c4, 0x16, 0x05);
278 xgifb_reg_set(P3c4, 0x16, 0x85);
281 xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
283 xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
286 /* xgifb_reg_set(P3c4 ,0x18, 0x52); */ /* MRS2 */
287 xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
288 xgifb_reg_set(P3c4, 0x19, 0x00);
289 xgifb_reg_set(P3c4, 0x16, 0x05);
290 xgifb_reg_set(P3c4, 0x16, 0x85);
295 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
296 struct vb_device_info *pVBInfo)
298 xgifb_reg_set(P3c4, 0x18, 0x01);
299 xgifb_reg_set(P3c4, 0x19, 0x40);
300 xgifb_reg_set(P3c4, 0x16, 0x00);
301 xgifb_reg_set(P3c4, 0x16, 0x80);
304 xgifb_reg_set(P3c4, 0x18, 0x00);
305 xgifb_reg_set(P3c4, 0x19, 0x40);
306 xgifb_reg_set(P3c4, 0x16, 0x00);
307 xgifb_reg_set(P3c4, 0x16, 0x80);
309 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
310 /* xgifb_reg_set(P3c4, 0x18, 0x31); */
311 xgifb_reg_set(P3c4, 0x19, 0x01);
312 xgifb_reg_set(P3c4, 0x16, 0x03);
313 xgifb_reg_set(P3c4, 0x16, 0x83);
315 xgifb_reg_set(P3c4, 0x1B, 0x03);
317 /* xgifb_reg_set(P3c4, 0x18, 0x31); */
318 xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
319 xgifb_reg_set(P3c4, 0x19, 0x00);
320 xgifb_reg_set(P3c4, 0x16, 0x03);
321 xgifb_reg_set(P3c4, 0x16, 0x83);
322 xgifb_reg_set(P3c4, 0x1B, 0x00);
325 static void XGINew_DDR1x_DefaultRegister(
326 struct xgi_hw_device_info *HwDeviceExtension,
327 unsigned long Port, struct vb_device_info *pVBInfo)
329 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
331 if (HwDeviceExtension->jChipType >= XG20) {
332 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
335 pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
338 pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
341 pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
343 xgifb_reg_set(P3d4, 0x98, 0x01);
344 xgifb_reg_set(P3d4, 0x9A, 0x02);
346 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
348 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
350 switch (HwDeviceExtension->jChipType) {
356 pVBInfo->CR40[11][XGINew_RAMType]);
360 pVBInfo->CR40[12][XGINew_RAMType]);
364 pVBInfo->CR40[13][XGINew_RAMType]);
367 xgifb_reg_set(P3d4, 0x82, 0x88);
368 xgifb_reg_set(P3d4, 0x86, 0x00);
369 /* Insert read command for delay */
370 xgifb_reg_get(P3d4, 0x86);
371 xgifb_reg_set(P3d4, 0x86, 0x88);
372 xgifb_reg_get(P3d4, 0x86);
375 pVBInfo->CR40[13][XGINew_RAMType]);
376 xgifb_reg_set(P3d4, 0x82, 0x77);
377 xgifb_reg_set(P3d4, 0x85, 0x00);
379 /* Insert read command for delay */
380 xgifb_reg_get(P3d4, 0x85);
381 xgifb_reg_set(P3d4, 0x85, 0x88);
383 /* Insert read command for delay */
384 xgifb_reg_get(P3d4, 0x85);
388 pVBInfo->CR40[12][XGINew_RAMType]);
392 pVBInfo->CR40[11][XGINew_RAMType]);
396 xgifb_reg_set(P3d4, 0x97, 0x00);
397 xgifb_reg_set(P3d4, 0x98, 0x01);
398 xgifb_reg_set(P3d4, 0x9A, 0x02);
399 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
403 static void XGINew_DDR2_DefaultRegister(
404 struct xgi_hw_device_info *HwDeviceExtension,
405 unsigned long Port, struct vb_device_info *pVBInfo)
407 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
409 /* keep following setting sequence, each setting in
410 * the same reg insert idle */
411 xgifb_reg_set(P3d4, 0x82, 0x77);
412 xgifb_reg_set(P3d4, 0x86, 0x00);
413 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
414 xgifb_reg_set(P3d4, 0x86, 0x88);
415 xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
417 xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]);
418 xgifb_reg_set(P3d4, 0x82, 0x77);
419 xgifb_reg_set(P3d4, 0x85, 0x00);
420 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
421 xgifb_reg_set(P3d4, 0x85, 0x88);
422 xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
423 xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
424 if (HwDeviceExtension->jChipType == XG27)
426 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]);
428 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
430 xgifb_reg_set(P3d4, 0x98, 0x01);
431 xgifb_reg_set(P3d4, 0x9A, 0x02);
432 if (HwDeviceExtension->jChipType == XG27)
433 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
435 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
438 static void XGINew_SetDRAMDefaultRegister340(
439 struct xgi_hw_device_info *HwDeviceExtension,
440 unsigned long Port, struct vb_device_info *pVBInfo)
442 unsigned char temp, temp1, temp2, temp3, i, j, k;
444 unsigned long P3d4 = Port, P3c4 = Port - 0x10;
446 xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][XGINew_RAMType]);
447 xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][XGINew_RAMType]);
448 xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][XGINew_RAMType]);
449 xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][XGINew_RAMType]);
452 for (i = 0; i < 4; i++) {
453 /* CR6B DQS fine tune delay */
454 temp = pVBInfo->CR6B[XGINew_RAMType][i];
455 for (j = 0; j < 4; j++) {
456 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
458 xgifb_reg_set(P3d4, 0x6B, temp2);
459 /* Insert read command for delay */
460 xgifb_reg_get(P3d4, 0x6B);
467 for (i = 0; i < 4; i++) {
468 /* CR6E DQM fine tune delay */
469 temp = pVBInfo->CR6E[XGINew_RAMType][i];
470 for (j = 0; j < 4; j++) {
471 temp1 = ((temp >> (2 * j)) & 0x03) << 2;
473 xgifb_reg_set(P3d4, 0x6E, temp2);
474 /* Insert read command for delay */
475 xgifb_reg_get(P3d4, 0x6E);
482 for (k = 0; k < 4; k++) {
483 /* CR6E_D[1:0] select channel */
484 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
486 for (i = 0; i < 8; i++) {
487 /* CR6F DQ fine tune delay */
488 temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i];
489 for (j = 0; j < 4; j++) {
490 temp1 = (temp >> (2 * j)) & 0x03;
492 xgifb_reg_set(P3d4, 0x6F, temp2);
493 /* Insert read command for delay */
494 xgifb_reg_get(P3d4, 0x6F);
502 xgifb_reg_set(P3d4, 0x80, pVBInfo->CR40[9][XGINew_RAMType]); /* CR80 */
503 xgifb_reg_set(P3d4, 0x81, pVBInfo->CR40[10][XGINew_RAMType]); /* CR81 */
506 /* CR89 terminator type select */
507 temp = pVBInfo->CR89[XGINew_RAMType][0];
508 for (j = 0; j < 4; j++) {
509 temp1 = (temp >> (2 * j)) & 0x03;
511 xgifb_reg_set(P3d4, 0x89, temp2);
512 xgifb_reg_get(P3d4, 0x89); /* Insert read command for delay */
517 temp = pVBInfo->CR89[XGINew_RAMType][1];
520 xgifb_reg_set(P3d4, 0x89, temp2);
522 temp = pVBInfo->CR40[3][XGINew_RAMType];
524 temp2 = (temp >> 4) & 0x07;
526 xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
527 xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
528 xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
529 xgifb_reg_set(P3d4, 0x41, pVBInfo->CR40[0][XGINew_RAMType]); /* CR41 */
531 if (HwDeviceExtension->jChipType == XG27)
532 xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
534 for (j = 0; j <= 6; j++) /* CR90 - CR96 */
535 xgifb_reg_set(P3d4, (0x90 + j),
536 pVBInfo->CR40[14 + j][XGINew_RAMType]);
538 for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
539 xgifb_reg_set(P3d4, (0xC3 + j),
540 pVBInfo->CR40[21 + j][XGINew_RAMType]);
542 for (j = 0; j < 2; j++) /* CR8A - CR8B */
543 xgifb_reg_set(P3d4, (0x8A + j),
544 pVBInfo->CR40[1 + j][XGINew_RAMType]);
546 if ((HwDeviceExtension->jChipType == XG41) ||
547 (HwDeviceExtension->jChipType == XG42))
548 xgifb_reg_set(P3d4, 0x8C, 0x87);
550 xgifb_reg_set(P3d4, 0x59, pVBInfo->CR40[4][XGINew_RAMType]); /* CR59 */
552 xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
553 xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
554 xgifb_reg_set(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
555 if (XGINew_RAMType) {
556 /* xgifb_reg_set(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
557 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
558 if (HwDeviceExtension->jChipType == XG27)
559 xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
562 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
564 xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
566 temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
568 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
570 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
571 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
573 xgifb_reg_set(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
576 static void XGINew_SetDRAMSizingType(int index,
577 unsigned short DRAMTYPE_TABLE[][5],
578 struct vb_device_info *pVBInfo)
582 data = DRAMTYPE_TABLE[index][4];
583 xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, data);
585 /* should delay 50 ns */
588 static unsigned short XGINew_SetDRAMSizeReg(int index,
589 unsigned short DRAMTYPE_TABLE[][5],
590 struct vb_device_info *pVBInfo)
592 unsigned short data = 0, memsize = 0;
594 unsigned char ChannelNo;
596 RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 32;
597 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
605 if (XGINew_ChannelAB == 3)
608 ChannelNo = XGINew_ChannelAB;
610 if (ChannelNo * RankSize <= 256) {
611 while ((RankSize >>= 1) > 0)
616 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
617 xgifb_reg_set(pVBInfo->P3c4,
619 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
622 /* data |= XGINew_ChannelAB << 2; */
623 /* data |= (XGINew_DataBusWidth / 64) << 1; */
624 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
627 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
632 static unsigned short XGINew_SetDRAMSize20Reg(int index,
633 unsigned short DRAMTYPE_TABLE[][5],
634 struct vb_device_info *pVBInfo)
636 unsigned short data = 0, memsize = 0;
638 unsigned char ChannelNo;
640 RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 8;
641 data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
649 if (XGINew_ChannelAB == 3)
652 ChannelNo = XGINew_ChannelAB;
654 if (ChannelNo * RankSize <= 256) {
655 while ((RankSize >>= 1) > 0)
660 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
661 xgifb_reg_set(pVBInfo->P3c4,
663 (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
667 /* data |= XGINew_ChannelAB << 2; */
668 /* data |= (XGINew_DataBusWidth / 64) << 1; */
669 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
672 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
677 static int XGINew_ReadWriteRest(unsigned short StopAddr,
678 unsigned short StartAddr, struct vb_device_info *pVBInfo)
681 unsigned long Position = 0;
683 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
685 for (i = StartAddr; i <= StopAddr; i++) {
687 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
690 udelay(500); /* [Vicent] 2004/04/16.
691 Fix #1759 Memory Size error in Multi-Adapter. */
695 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
698 for (i = StartAddr; i <= StopAddr; i++) {
700 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) !=
707 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
711 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
713 if ((data & 0x10) == 0) {
714 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
715 data = (data & 0x02) >> 1;
722 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
723 struct vb_device_info *pVBInfo)
727 switch (HwDeviceExtension->jChipType) {
730 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
732 XGINew_ChannelAB = 1; /* XG20 "JUST" one channel */
734 if (data == 0) { /* Single_32_16 */
736 if ((HwDeviceExtension->ulVideoMemorySize - 1)
739 XGINew_DataBusWidth = 32; /* 32 bits */
740 /* 22bit + 2 rank + 32bit */
741 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
742 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
745 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
748 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
750 /* 22bit + 1 rank + 32bit */
751 xgifb_reg_set(pVBInfo->P3c4,
754 xgifb_reg_set(pVBInfo->P3c4,
759 if (XGINew_ReadWriteRest(23,
766 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
768 XGINew_DataBusWidth = 16; /* 16 bits */
769 /* 22bit + 2 rank + 16bit */
770 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
771 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
774 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
777 xgifb_reg_set(pVBInfo->P3c4,
783 } else { /* Dual_16_8 */
784 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
786 XGINew_DataBusWidth = 16; /* 16 bits */
787 /* (0x31:12x8x2) 22bit + 2 rank */
788 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
790 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
793 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
796 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
798 /* (0x31:12x8x2) 22bit + 1 rank */
799 xgifb_reg_set(pVBInfo->P3c4,
803 xgifb_reg_set(pVBInfo->P3c4,
808 if (XGINew_ReadWriteRest(22,
815 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
817 XGINew_DataBusWidth = 8; /* 8 bits */
818 /* (0x31:12x8x2) 22bit + 2 rank */
819 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
821 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
824 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
826 else /* (0x31:12x8x2) 22bit + 1 rank */
827 xgifb_reg_set(pVBInfo->P3c4,
836 XGINew_DataBusWidth = 16; /* 16 bits */
837 XGINew_ChannelAB = 1; /* Single channel */
838 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
841 if (XGINew_CheckFrequence(pVBInfo) == 1) {
842 XGINew_DataBusWidth = 32; /* 32 bits */
843 XGINew_ChannelAB = 3; /* Quad Channel */
844 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
845 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
847 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
850 XGINew_ChannelAB = 2; /* Dual channels */
851 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
853 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
856 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x49);
858 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
861 XGINew_ChannelAB = 3;
862 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
863 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
865 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
868 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
870 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
873 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x39);
875 XGINew_DataBusWidth = 64; /* 64 bits */
876 XGINew_ChannelAB = 2; /* Dual channels */
877 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
878 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
880 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
883 XGINew_ChannelAB = 1; /* Single channels */
884 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
886 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
889 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x53);
891 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
894 XGINew_ChannelAB = 2; /* Dual channels */
895 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
896 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
898 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
901 XGINew_ChannelAB = 1; /* Single channels */
902 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
904 if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
907 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x43);
914 XG42 SR14 D[3] Reserve
915 D[2] = 1, Dual Channel
918 It's Different from Other XG40 Series.
920 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
921 XGINew_DataBusWidth = 32; /* 32 bits */
922 XGINew_ChannelAB = 2; /* 2 Channel */
923 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
924 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
926 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
929 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
930 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
931 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
934 XGINew_ChannelAB = 1; /* Single Channel */
935 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
936 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
938 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
941 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
942 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
945 XGINew_DataBusWidth = 64; /* 64 bits */
946 XGINew_ChannelAB = 1; /* 1 channels */
947 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
948 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
950 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
953 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
954 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
962 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
963 XGINew_DataBusWidth = 32; /* 32 bits */
964 XGINew_ChannelAB = 3;
965 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
966 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
968 if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
971 XGINew_ChannelAB = 2; /* 2 channels */
972 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
974 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
977 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
978 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
980 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
981 XGINew_ChannelAB = 3; /* 4 channels */
983 XGINew_ChannelAB = 2; /* 2 channels */
984 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
987 XGINew_DataBusWidth = 64; /* 64 bits */
988 XGINew_ChannelAB = 2; /* 2 channels */
989 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
990 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
992 if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
995 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
996 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
1003 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
1004 struct vb_device_info *pVBInfo)
1007 unsigned short memsize, addr;
1009 xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
1010 xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
1011 XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
1013 if (HwDeviceExtension->jChipType >= XG20) {
1014 for (i = 0; i < 12; i++) {
1015 XGINew_SetDRAMSizingType(i,
1016 XGINew_DDRDRAM_TYPE20,
1018 memsize = XGINew_SetDRAMSize20Reg(i,
1019 XGINew_DDRDRAM_TYPE20,
1024 addr = memsize + (XGINew_ChannelAB - 2) + 20;
1025 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1026 (unsigned long) (1 << addr))
1029 if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
1033 for (i = 0; i < 4; i++) {
1034 XGINew_SetDRAMSizingType(i,
1035 XGINew_DDRDRAM_TYPE340,
1037 memsize = XGINew_SetDRAMSizeReg(i,
1038 XGINew_DDRDRAM_TYPE340,
1044 addr = memsize + (XGINew_ChannelAB - 2) + 20;
1045 if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1046 (unsigned long) (1 << addr))
1049 if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
1056 static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
1057 struct vb_device_info *pVBInfo)
1059 unsigned short data;
1061 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1062 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1064 XGISetModeNew(HwDeviceExtension, 0x2e);
1066 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1067 /* disable read cache */
1068 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
1069 XGI_DisplayOff(HwDeviceExtension, pVBInfo);
1071 /* data = xgifb_reg_get(pVBInfo->P3c4, 0x1); */
1072 /* data |= 0x20 ; */
1073 /* xgifb_reg_set(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
1074 XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
1075 data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1076 /* enable read cache */
1077 xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
1080 static void ReadVBIOSTablData(unsigned char ChipType,
1081 struct vb_device_info *pVBInfo)
1083 volatile unsigned char *pVideoMemory =
1084 (unsigned char *) pVBInfo->ROMAddr;
1087 /* Volari customize data area end */
1089 if (ChipType == XG21) {
1090 pVBInfo->IF_DEF_LVDS = 0;
1091 if (pVideoMemory[0x65] & 0x1) {
1092 pVBInfo->IF_DEF_LVDS = 1;
1093 i = pVideoMemory[0x316] | (pVideoMemory[0x317] << 8);
1094 j = pVideoMemory[i - 1];
1098 pVBInfo->XG21_LVDSCapList[k].
1101 (pVideoMemory[i + 1] << 8);
1102 pVBInfo->XG21_LVDSCapList[k].LVDSHT
1103 = pVideoMemory[i + 2] |
1104 (pVideoMemory[i + 3] << 8);
1105 pVBInfo->XG21_LVDSCapList[k].LVDSVT
1106 = pVideoMemory[i + 4] |
1107 (pVideoMemory[i + 5] << 8);
1108 pVBInfo->XG21_LVDSCapList[k].LVDSHDE
1109 = pVideoMemory[i + 6] |
1110 (pVideoMemory[i + 7] << 8);
1111 pVBInfo->XG21_LVDSCapList[k].LVDSVDE
1112 = pVideoMemory[i + 8] |
1113 (pVideoMemory[i + 9] << 8);
1114 pVBInfo->XG21_LVDSCapList[k].LVDSHFP
1115 = pVideoMemory[i + 10] |
1116 (pVideoMemory[i + 11] << 8);
1117 pVBInfo->XG21_LVDSCapList[k].LVDSVFP
1118 = pVideoMemory[i + 12] |
1119 (pVideoMemory[i + 13] << 8);
1120 pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
1121 = pVideoMemory[i + 14] |
1122 (pVideoMemory[i + 15] << 8);
1123 pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
1124 = pVideoMemory[i + 16] |
1125 (pVideoMemory[i + 17] << 8);
1126 pVBInfo->XG21_LVDSCapList[k].VCLKData1
1127 = pVideoMemory[i + 18];
1128 pVBInfo->XG21_LVDSCapList[k].VCLKData2
1129 = pVideoMemory[i + 19];
1130 pVBInfo->XG21_LVDSCapList[k].PSC_S1
1131 = pVideoMemory[i + 20];
1132 pVBInfo->XG21_LVDSCapList[k].PSC_S2
1133 = pVideoMemory[i + 21];
1134 pVBInfo->XG21_LVDSCapList[k].PSC_S3
1135 = pVideoMemory[i + 22];
1136 pVBInfo->XG21_LVDSCapList[k].PSC_S4
1137 = pVideoMemory[i + 23];
1138 pVBInfo->XG21_LVDSCapList[k].PSC_S5
1139 = pVideoMemory[i + 24];
1144 (k < (sizeof(XGI21_LCDCapList) /
1146 XGI21_LVDSCapStruct))));
1148 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability
1150 (pVideoMemory[i + 1] << 8);
1151 pVBInfo->XG21_LVDSCapList[0].LVDSHT
1152 = pVideoMemory[i + 2] |
1153 (pVideoMemory[i + 3] << 8);
1154 pVBInfo->XG21_LVDSCapList[0].LVDSVT
1155 = pVideoMemory[i + 4] |
1156 (pVideoMemory[i + 5] << 8);
1157 pVBInfo->XG21_LVDSCapList[0].LVDSHDE
1158 = pVideoMemory[i + 6] |
1159 (pVideoMemory[i + 7] << 8);
1160 pVBInfo->XG21_LVDSCapList[0].LVDSVDE
1161 = pVideoMemory[i + 8] |
1162 (pVideoMemory[i + 9] << 8);
1163 pVBInfo->XG21_LVDSCapList[0].LVDSHFP
1164 = pVideoMemory[i + 10] |
1165 (pVideoMemory[i + 11] << 8);
1166 pVBInfo->XG21_LVDSCapList[0].LVDSVFP
1167 = pVideoMemory[i + 12] |
1168 (pVideoMemory[i + 13] << 8);
1169 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC
1170 = pVideoMemory[i + 14] |
1171 (pVideoMemory[i + 15] << 8);
1172 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC
1173 = pVideoMemory[i + 16] |
1174 (pVideoMemory[i + 17] << 8);
1175 pVBInfo->XG21_LVDSCapList[0].VCLKData1
1176 = pVideoMemory[i + 18];
1177 pVBInfo->XG21_LVDSCapList[0].VCLKData2
1178 = pVideoMemory[i + 19];
1179 pVBInfo->XG21_LVDSCapList[0].PSC_S1
1180 = pVideoMemory[i + 20];
1181 pVBInfo->XG21_LVDSCapList[0].PSC_S2
1182 = pVideoMemory[i + 21];
1183 pVBInfo->XG21_LVDSCapList[0].PSC_S3
1184 = pVideoMemory[i + 22];
1185 pVBInfo->XG21_LVDSCapList[0].PSC_S4
1186 = pVideoMemory[i + 23];
1187 pVBInfo->XG21_LVDSCapList[0].PSC_S5
1188 = pVideoMemory[i + 24];
1194 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1195 struct vb_device_info *pVBInfo)
1197 unsigned short tempbx = 0, temp, tempcx, CR3CData;
1199 temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
1201 if (temp & Monitor1Sense)
1202 tempbx |= ActiveCRT1;
1203 if (temp & LCDSense)
1204 tempbx |= ActiveLCD;
1205 if (temp & Monitor2Sense)
1206 tempbx |= ActiveCRT2;
1207 if (temp & TVSense) {
1209 if (temp & AVIDEOSense)
1210 tempbx |= (ActiveAVideo << 8);
1211 if (temp & SVIDEOSense)
1212 tempbx |= (ActiveSVideo << 8);
1213 if (temp & SCARTSense)
1214 tempbx |= (ActiveSCART << 8);
1215 if (temp & HiTVSense)
1216 tempbx |= (ActiveHiTV << 8);
1217 if (temp & YPbPrSense)
1218 tempbx |= (ActiveYPbPr << 8);
1221 tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1222 tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
1224 if (tempbx & tempcx) {
1225 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
1226 if (!(CR3CData & DisplayDeviceFromCMOS)) {
1228 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1233 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1238 xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1239 xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1242 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1243 struct vb_device_info *pVBInfo)
1245 unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1247 temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1248 temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1249 temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1251 if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1252 if (temp & ActiveCRT2)
1253 tempcl = SetCRT2ToRAMDAC;
1256 if (temp & ActiveLCD) {
1257 tempcl |= SetCRT2ToLCD;
1258 if (temp & DriverMode) {
1259 if (temp & ActiveTV) {
1260 tempch = SetToLCDA | EnableDualEdge;
1261 temp ^= SetCRT2ToLCD;
1263 if ((temp >> 8) & ActiveAVideo)
1264 tempcl |= SetCRT2ToAVIDEO;
1265 if ((temp >> 8) & ActiveSVideo)
1266 tempcl |= SetCRT2ToSVIDEO;
1267 if ((temp >> 8) & ActiveSCART)
1268 tempcl |= SetCRT2ToSCART;
1270 if (pVBInfo->IF_DEF_HiVision == 1) {
1271 if ((temp >> 8) & ActiveHiTV)
1272 tempcl |= SetCRT2ToHiVisionTV;
1275 if (pVBInfo->IF_DEF_YPbPr == 1) {
1276 if ((temp >> 8) & ActiveYPbPr)
1282 if ((temp >> 8) & ActiveAVideo)
1283 tempcl |= SetCRT2ToAVIDEO;
1284 if ((temp >> 8) & ActiveSVideo)
1285 tempcl |= SetCRT2ToSVIDEO;
1286 if ((temp >> 8) & ActiveSCART)
1287 tempcl |= SetCRT2ToSCART;
1289 if (pVBInfo->IF_DEF_HiVision == 1) {
1290 if ((temp >> 8) & ActiveHiTV)
1291 tempcl |= SetCRT2ToHiVisionTV;
1294 if (pVBInfo->IF_DEF_YPbPr == 1) {
1295 if ((temp >> 8) & ActiveYPbPr)
1300 tempcl |= SetSimuScanMode;
1301 if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1302 || (temp & ActiveCRT2)))
1303 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1304 if ((temp & ActiveLCD) && (temp & ActiveTV))
1305 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1306 xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1308 CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1309 CR31Data &= ~(SetNotSimuMode >> 8);
1310 if (!(temp & ActiveCRT1))
1311 CR31Data |= (SetNotSimuMode >> 8);
1312 CR31Data &= ~(DisableCRT2Display >> 8);
1313 if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1314 CR31Data |= (DisableCRT2Display >> 8);
1315 xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1317 CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1318 CR38Data &= ~SetYPbPr;
1320 xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1324 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1325 struct vb_device_info *pVBInfo)
1328 volatile unsigned char *pVideoMemory =
1329 (unsigned char *) pVBInfo->ROMAddr;
1331 pVBInfo->IF_DEF_LVDS = 0;
1334 if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
1335 pVBInfo->IF_DEF_LVDS = 1;
1336 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1338 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1341 /* Enable GPIOA/B read */
1342 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1343 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1344 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1345 XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1346 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1347 /* Enable read GPIOF */
1348 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1349 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
1351 xgifb_reg_and_or(pVBInfo->P3d4,
1354 0x80); /* TMDS on chip */
1356 xgifb_reg_and_or(pVBInfo->P3d4,
1359 0xA0); /* Only DVO on chip */
1360 /* Disable read GPIOF */
1361 xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1368 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1369 struct vb_device_info *pVBInfo)
1371 unsigned char Temp, bCR4A;
1373 pVBInfo->IF_DEF_LVDS = 0;
1374 bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1375 /* Enable GPIOA/B/C read */
1376 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1377 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1378 xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1381 pVBInfo->IF_DEF_LVDS = 1;
1383 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1384 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1386 /* TMDS/DVO setting */
1387 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1389 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1393 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1395 unsigned char CR38, CR4A, temp;
1397 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1398 /* enable GPIOE read */
1399 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1400 CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1402 if ((CR38 & 0xE0) > 0x80) {
1403 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1408 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1413 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1415 unsigned char CR4A, temp;
1417 CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1418 /* enable GPIOA/B/C read */
1419 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1420 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1424 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
1426 xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1431 unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1433 struct vb_device_info VBINF;
1434 struct vb_device_info *pVBInfo = &VBINF;
1435 unsigned char i, temp = 0, temp1;
1436 /* VBIOSVersion[5]; */
1437 volatile unsigned char *pVideoMemory;
1439 /* unsigned long j, k; */
1443 pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1445 pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1447 pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
1449 pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
1451 /* Newdebugcode(0x99); */
1454 /* if (pVBInfo->ROMAddr == 0) */
1457 if (pVBInfo->FBAddr == NULL) {
1458 printk("\n pVBInfo->FBAddr == 0 ");
1462 if (pVBInfo->BaseAddr == 0) {
1463 printk("\npVBInfo->BaseAddr == 0 ");
1468 outb(0x67, (pVBInfo->BaseAddr + 0x12)); /* 3c2 <- 67 ,ynlai */
1470 pVBInfo->ISXPDOS = 0;
1475 /* VBIOSVersion[4] = 0x0; */
1477 /* 09/07/99 modify by domao */
1479 pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1480 pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1481 pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1482 pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1483 pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1484 pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1485 pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1486 pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1487 pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1488 pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1489 pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1490 pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1491 pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
1492 pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
1493 pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
1494 pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
1495 pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
1498 if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1499 /* Run XGI_GetVBType before InitTo330Pointer */
1500 XGI_GetVBType(pVBInfo);
1502 InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1505 ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
1508 xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1511 /* GetXG21Sense (GPIO) */
1512 if (HwDeviceExtension->jChipType == XG21)
1513 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1515 if (HwDeviceExtension->jChipType == XG27)
1516 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1520 /* 2.Reset Extended register */
1522 for (i = 0x06; i < 0x20; i++)
1523 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1525 for (i = 0x21; i <= 0x27; i++)
1526 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1528 /* for(i = 0x06; i <= 0x27; i++) */
1529 /* xgifb_reg_set(pVBInfo->P3c4, i, 0); */
1533 for (i = 0x31; i <= 0x3B; i++)
1534 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1537 /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1538 if (HwDeviceExtension->jChipType == XG42)
1539 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1541 /* for (i = 0x30; i <= 0x3F; i++) */
1542 /* xgifb_reg_set(pVBInfo->P3d4, i, 0); */
1544 for (i = 0x79; i <= 0x7C; i++)
1545 xgifb_reg_set(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
1549 if (HwDeviceExtension->jChipType >= XG20)
1550 xgifb_reg_set(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
1554 XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension,
1560 /* 4.SetDefExt1Regs begin */
1561 xgifb_reg_set(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
1562 if (HwDeviceExtension->jChipType == XG27) {
1563 xgifb_reg_set(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
1564 xgifb_reg_set(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
1566 xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1567 xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1568 /* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */
1569 /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1570 xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1571 /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1572 xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1573 if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
1574 xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
1577 /* xgifb_reg_set(pVBInfo->P3c4, 0x11, SR11); */
1581 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1584 temp1 = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
1586 if (temp1 == 0x02) {
1587 outl(0x80000000, 0xcf8);
1588 ChipsetID = inl(0x0cfc);
1589 outl(0x8000002C, 0xcf8);
1590 VendorID = inl(0x0cfc);
1591 VendorID &= 0x0000FFFF;
1592 outl(0x8001002C, 0xcf8);
1593 GraphicVendorID = inl(0x0cfc);
1594 GraphicVendorID &= 0x0000FFFF;
1596 if (ChipsetID == 0x7301039)
1597 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x09);
1599 ChipsetID &= 0x0000FFFF;
1601 if ((ChipsetID == 0x700E) ||
1602 (ChipsetID == 0x1022) ||
1603 (ChipsetID == 0x1106) ||
1604 (ChipsetID == 0x10DE)) {
1605 if (ChipsetID == 0x1106) {
1606 if ((VendorID == 0x1019) &&
1607 (GraphicVendorID == 0x1019))
1608 xgifb_reg_set(pVBInfo->P3d4,
1612 xgifb_reg_set(pVBInfo->P3d4,
1616 xgifb_reg_set(pVBInfo->P3d4,
1626 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1627 for (i = 0x47; i <= 0x4C; i++)
1628 xgifb_reg_set(pVBInfo->P3d4,
1630 pVBInfo->AGPReg[i - 0x47]);
1632 for (i = 0x70; i <= 0x71; i++)
1633 xgifb_reg_set(pVBInfo->P3d4,
1635 pVBInfo->AGPReg[6 + i - 0x70]);
1637 for (i = 0x74; i <= 0x77; i++)
1638 xgifb_reg_set(pVBInfo->P3d4,
1640 pVBInfo->AGPReg[8 + i - 0x74]);
1641 /* Set AGP customize registers (in SetDefAGPRegs) End */
1642 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
1643 /* outl(0x80000000, 0xcf8); */
1644 /* ChipsetID = inl(0x0cfc); */
1645 /* if (ChipsetID == 0x25308086) */
1646 /* xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */
1648 HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension,
1656 xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1661 xgifb_reg_set(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
1662 xgifb_reg_set(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
1663 xgifb_reg_set(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
1666 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1668 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1669 /* alan, disable VideoCapture */
1670 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1671 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1672 /* chk if BCLK>=100MHz */
1673 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1674 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1676 xgifb_reg_set(pVBInfo->Part1Port,
1678 (*pVBInfo->pCRT2Data_1_2));
1682 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1685 xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1687 if ((HwDeviceExtension->jChipType == XG42) &&
1688 XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1690 xgifb_reg_set(pVBInfo->P3c4,
1692 (*pVBInfo->pSR31 & 0x3F) | 0x40);
1693 xgifb_reg_set(pVBInfo->P3c4,
1695 (*pVBInfo->pSR32 & 0xFC) | 0x01);
1697 xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1698 xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
1700 xgifb_reg_set(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
1704 SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4); */
1706 if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1707 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1708 if (pVBInfo->IF_DEF_LVDS == 0) {
1709 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1710 xgifb_reg_set(pVBInfo->Part4Port,
1712 *pVBInfo->pCRT2Data_4_D);
1713 xgifb_reg_set(pVBInfo->Part4Port,
1715 *pVBInfo->pCRT2Data_4_E);
1716 xgifb_reg_set(pVBInfo->Part4Port,
1718 *pVBInfo->pCRT2Data_4_10);
1719 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1722 XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1731 XGI_SenseCRT1(pVBInfo);
1734 /* XGINew_DetectMonitor(HwDeviceExtension); */
1735 pVBInfo->IF_DEF_CH7007 = 0;
1736 if ((HwDeviceExtension->jChipType == XG21) &&
1737 (pVBInfo->IF_DEF_CH7007)) {
1740 XGI_GetSenseStatus(HwDeviceExtension, pVBInfo);
1744 if (HwDeviceExtension->jChipType == XG21) {
1747 xgifb_reg_and_or(pVBInfo->P3d4,
1750 Monitor1Sense); /* Z9 default has CRT */
1751 temp = GetXG21FPBits(pVBInfo);
1752 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1756 if (HwDeviceExtension->jChipType == XG27) {
1757 xgifb_reg_and_or(pVBInfo->P3d4,
1760 Monitor1Sense); /* Z9 default has CRT */
1761 temp = GetXG27FPBits(pVBInfo);
1762 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1766 XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
1769 XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1774 XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
1779 /* SetDefExt2Regs begin */
1782 temp = (unsigned char) xgifb_reg_get(pVBInfo->P3c4, 0x3A);
1788 *pVBInfo->pSR21 &= 0xEF;
1790 xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1792 *pVBInfo->pSR22 &= 0x20;
1793 xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
1795 /* base = 0x80000000; */
1796 /* OutPortLong(0xcf8, base); */
1797 /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1798 /* if (Temp == 0x1039) { */
1799 xgifb_reg_set(pVBInfo->P3c4,
1801 (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
1803 /* xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
1806 xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1810 XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1811 XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1815 xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1816 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x31);