drivers/staging/xgifb/vb_init.c

   1 #include "vgatypes.h"
   2
   3 #include <linux/types.h>
   4 #include <linux/delay.h> /* udelay */
   5 #include "XGIfb.h"
   6
   7 #include "vb_def.h"
   8 #include "vb_struct.h"
   9 #include "vb_util.h"
  10 #include "vb_setmode.h"
  11 #include "vb_init.h"
  12 #include "vb_ext.h"
  13
  14
  15 #include <linux/io.h>
  16
  17 static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
  18
  19 static unsigned short XGINew_DDRDRAM_TYPE340[4][5] = {
  20         { 2, 13, 9, 64, 0x45},
  21         { 2, 12, 9, 32, 0x35},
  22         { 2, 12, 8, 16, 0x31},
  23         { 2, 11, 8,  8, 0x21} };
  24
  25 static unsigned short XGINew_DDRDRAM_TYPE20[12][5] = {
  26         { 2, 14, 11, 128, 0x5D},
  27         { 2, 14, 10, 64, 0x59},
  28         { 2, 13, 11, 64, 0x4D},
  29         { 2, 14,  9, 32, 0x55},
  30         { 2, 13, 10, 32, 0x49},
  31         { 2, 12, 11, 32, 0x3D},
  32         { 2, 14,  8, 16, 0x51},
  33         { 2, 13,  9, 16, 0x45},
  34         { 2, 12, 10, 16, 0x39},
  35         { 2, 13,  8,  8, 0x41},
  36         { 2, 12,  9,  8, 0x35},
  37         { 2, 12,  8,  4, 0x31} };
  38
  39 static int XGINew_RAMType;
  40
  41 static unsigned char
  42 XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
  43                        struct vb_device_info *pVBInfo)
  44 {
  45         unsigned char data, temp;
  46
  47         if (HwDeviceExtension->jChipType < XG20) {
  48                 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
  49                         data = *pVBInfo->pSoftSetting & 0x07;
  50                         return data;
  51                 } else {
  52                         data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
  53                         if (data == 0)
  54                                 data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
  55                                        0x02) >> 1;
  56                         return data;
  57                 }
  58         } else if (HwDeviceExtension->jChipType == XG27) {
  59                 if (*pVBInfo->pSoftSetting & SoftDRAMType) {
  60                         data = *pVBInfo->pSoftSetting & 0x07;
  61                         return data;
  62                 }
  63                 temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
  64                 /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
  65                 if ((temp & 0x88) == 0x80)
  66                         data = 0; /* DDR */
  67                 else
  68                         data = 1; /* DDRII */
  69                 return data;
  70         } else if (HwDeviceExtension->jChipType == XG21) {
  71                 /* Independent GPIO control */
  72                 xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
  73                 udelay(800);
  74                 xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
  75                 /* GPIOF 0:DVI 1:DVO */
  76                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
  77                 /* HOTPLUG_SUPPORT */
  78                 /* for current XG20 & XG21, GPIOH is floating, driver will
  79                  * fix DDR temporarily */
  80                 if (temp & 0x01) /* DVI read GPIOH */
  81                         data = 1; /* DDRII */
  82                 else
  83                         data = 0; /* DDR */
  84                 /* ~HOTPLUG_SUPPORT */
  85                 xgifb_reg_or(pVBInfo->P3d4, 0xB4, 0x02);
  86                 return data;
  87         } else {
  88                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97) & 0x01;
  89
  90                 if (data == 1)
  91                         data++;
  92
  93                 return data;
  94         }
  95 }
  96
  97 static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
  98                                  struct vb_device_info *pVBInfo)
  99 {
 100         xgifb_reg_set(P3c4, 0x18, 0x01);
 101         xgifb_reg_set(P3c4, 0x19, 0x20);
 102         xgifb_reg_set(P3c4, 0x16, 0x00);
 103         xgifb_reg_set(P3c4, 0x16, 0x80);
 104
 105         if (*pVBInfo->pXGINew_DRAMTypeDefinition != 0x0C) { /* Samsung F Die */
 106                 mdelay(3);
 107                 xgifb_reg_set(P3c4, 0x18, 0x00);
 108                 xgifb_reg_set(P3c4, 0x19, 0x20);
 109                 xgifb_reg_set(P3c4, 0x16, 0x00);
 110                 xgifb_reg_set(P3c4, 0x16, 0x80);
 111         }
 112
 113         udelay(60);
 114         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
 115         xgifb_reg_set(P3c4, 0x19, 0x01);
 116         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[0]);
 117         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[1]);
 118         mdelay(1);
 119         xgifb_reg_set(P3c4, 0x1B, 0x03);
 120         udelay(500);
 121         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
 122         xgifb_reg_set(P3c4, 0x19, 0x00);
 123         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[2]);
 124         xgifb_reg_set(P3c4, 0x16, pVBInfo->SR16[3]);
 125         xgifb_reg_set(P3c4, 0x1B, 0x00);
 126 }
 127
 128 static void XGINew_SetMemoryClock(struct xgi_hw_device_info *HwDeviceExtension,
 129                 struct vb_device_info *pVBInfo)
 130 {
 131
 132         xgifb_reg_set(pVBInfo->P3c4,
 133                       0x28,
 134                       pVBInfo->MCLKData[XGINew_RAMType].SR28);
 135         xgifb_reg_set(pVBInfo->P3c4,
 136                       0x29,
 137                       pVBInfo->MCLKData[XGINew_RAMType].SR29);
 138         xgifb_reg_set(pVBInfo->P3c4,
 139                       0x2A,
 140                       pVBInfo->MCLKData[XGINew_RAMType].SR2A);
 141
 142         xgifb_reg_set(pVBInfo->P3c4,
 143                       0x2E,
 144                       pVBInfo->ECLKData[XGINew_RAMType].SR2E);
 145         xgifb_reg_set(pVBInfo->P3c4,
 146                       0x2F,
 147                       pVBInfo->ECLKData[XGINew_RAMType].SR2F);
 148         xgifb_reg_set(pVBInfo->P3c4,
 149                       0x30,
 150                       pVBInfo->ECLKData[XGINew_RAMType].SR30);
 151
 152         /* [Vicent] 2004/07/07,
 153          * When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
 154         /* [Hsuan] 2004/08/20,
 155          * Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
 156          * Set SR32 D[1:0] = 10b */
 157         if (HwDeviceExtension->jChipType == XG42) {
 158                 if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C) &&
 159                     (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01) &&
 160                     (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C) &&
 161                       (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01)) ||
 162                      ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22) &&
 163                       (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))
 164                         xgifb_reg_set(pVBInfo->P3c4,
 165                                       0x32,
 166                                       ((unsigned char) xgifb_reg_get(
 167                                           pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
 168         }
 169 }
 170
 171 static void XGINew_DDRII_Bootup_XG27(
 172                         struct xgi_hw_device_info *HwDeviceExtension,
 173                         unsigned long P3c4, struct vb_device_info *pVBInfo)
 174 {
 175         unsigned long P3d4 = P3c4 + 0x10;
 176         XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
 177                                                       pVBInfo);
 178         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 179
 180         /* Set Double Frequency */
 181         /* xgifb_reg_set(P3d4, 0x97, 0x11); *//* CR97 */
 182         xgifb_reg_set(P3d4, 0x97, *pVBInfo->pXGINew_CR97); /* CR97 */
 183
 184         udelay(200);
 185
 186         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS2 */
 187         xgifb_reg_set(P3c4, 0x19, 0x80); /* Set SR19 */
 188         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 189         udelay(15);
 190         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 191         udelay(15);
 192
 193         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS3 */
 194         xgifb_reg_set(P3c4, 0x19, 0xC0); /* Set SR19 */
 195         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 196         udelay(15);
 197         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 198         udelay(15);
 199
 200         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS1 */
 201         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 202         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 203         udelay(30);
 204         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 205         udelay(15);
 206
 207         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Enable */
 208         xgifb_reg_set(P3c4, 0x19, 0x0A); /* Set SR19 */
 209         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 210         udelay(30);
 211         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 212         xgifb_reg_set(P3c4, 0x16, 0x80); /* Set SR16 */
 213         /* udelay(15); */
 214
 215         xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B */
 216         udelay(60);
 217         xgifb_reg_set(P3c4, 0x1B, 0x00); /* Set SR1B */
 218
 219         xgifb_reg_set(P3c4, 0x18, 0x42); /* Set SR18 */ /* MRS, DLL Reset */
 220         xgifb_reg_set(P3c4, 0x19, 0x08); /* Set SR19 */
 221         xgifb_reg_set(P3c4, 0x16, 0x00); /* Set SR16 */
 222
 223         udelay(30);
 224         xgifb_reg_set(P3c4, 0x16, 0x83); /* Set SR16 */
 225         udelay(15);
 226
 227         xgifb_reg_set(P3c4, 0x18, 0x80); /* Set SR18 */ /* MRS, ODT */
 228         xgifb_reg_set(P3c4, 0x19, 0x46); /* Set SR19 */
 229         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 230         udelay(30);
 231         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 232         udelay(15);
 233
 234         xgifb_reg_set(P3c4, 0x18, 0x00); /* Set SR18 */ /* EMRS */
 235         xgifb_reg_set(P3c4, 0x19, 0x40); /* Set SR19 */
 236         xgifb_reg_set(P3c4, 0x16, 0x20); /* Set SR16 */
 237         udelay(30);
 238         xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
 239         udelay(15);
 240
 241         /* Set SR1B refresh control 000:close; 010:open */
 242         xgifb_reg_set(P3c4, 0x1B, 0x04);
 243         udelay(200);
 244
 245 }
 246
 247 static void XGINew_DDR2_MRS_XG20(struct xgi_hw_device_info *HwDeviceExtension,
 248                 unsigned long P3c4, struct vb_device_info *pVBInfo)
 249 {
 250         unsigned long P3d4 = P3c4 + 0x10;
 251
 252         XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
 253                                                       pVBInfo);
 254         XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 255
 256         xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
 257
 258         udelay(200);
 259         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS2 */
 260         xgifb_reg_set(P3c4, 0x19, 0x80);
 261         xgifb_reg_set(P3c4, 0x16, 0x05);
 262         xgifb_reg_set(P3c4, 0x16, 0x85);
 263
 264         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS3 */
 265         xgifb_reg_set(P3c4, 0x19, 0xC0);
 266         xgifb_reg_set(P3c4, 0x16, 0x05);
 267         xgifb_reg_set(P3c4, 0x16, 0x85);
 268
 269         xgifb_reg_set(P3c4, 0x18, 0x00); /* EMRS1 */
 270         xgifb_reg_set(P3c4, 0x19, 0x40);
 271         xgifb_reg_set(P3c4, 0x16, 0x05);
 272         xgifb_reg_set(P3c4, 0x16, 0x85);
 273
 274         /* xgifb_reg_set(P3c4, 0x18, 0x52); */ /* MRS1 */
 275         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 276         xgifb_reg_set(P3c4, 0x19, 0x02);
 277         xgifb_reg_set(P3c4, 0x16, 0x05);
 278         xgifb_reg_set(P3c4, 0x16, 0x85);
 279
 280         udelay(15);
 281         xgifb_reg_set(P3c4, 0x1B, 0x04); /* SR1B */
 282         udelay(30);
 283         xgifb_reg_set(P3c4, 0x1B, 0x00); /* SR1B */
 284         udelay(100);
 285
 286         /* xgifb_reg_set(P3c4 ,0x18, 0x52); */ /* MRS2 */
 287         xgifb_reg_set(P3c4, 0x18, 0x42); /* MRS1 */
 288         xgifb_reg_set(P3c4, 0x19, 0x00);
 289         xgifb_reg_set(P3c4, 0x16, 0x05);
 290         xgifb_reg_set(P3c4, 0x16, 0x85);
 291
 292         udelay(200);
 293 }
 294
 295 static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
 296                                   struct vb_device_info *pVBInfo)
 297 {
 298         xgifb_reg_set(P3c4, 0x18, 0x01);
 299         xgifb_reg_set(P3c4, 0x19, 0x40);
 300         xgifb_reg_set(P3c4, 0x16, 0x00);
 301         xgifb_reg_set(P3c4, 0x16, 0x80);
 302         udelay(60);
 303
 304         xgifb_reg_set(P3c4, 0x18, 0x00);
 305         xgifb_reg_set(P3c4, 0x19, 0x40);
 306         xgifb_reg_set(P3c4, 0x16, 0x00);
 307         xgifb_reg_set(P3c4, 0x16, 0x80);
 308         udelay(60);
 309         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
 310         /* xgifb_reg_set(P3c4, 0x18, 0x31); */
 311         xgifb_reg_set(P3c4, 0x19, 0x01);
 312         xgifb_reg_set(P3c4, 0x16, 0x03);
 313         xgifb_reg_set(P3c4, 0x16, 0x83);
 314         mdelay(1);
 315         xgifb_reg_set(P3c4, 0x1B, 0x03);
 316         udelay(500);
 317         /* xgifb_reg_set(P3c4, 0x18, 0x31); */
 318         xgifb_reg_set(P3c4, 0x18, pVBInfo->SR15[2][XGINew_RAMType]); /* SR18 */
 319         xgifb_reg_set(P3c4, 0x19, 0x00);
 320         xgifb_reg_set(P3c4, 0x16, 0x03);
 321         xgifb_reg_set(P3c4, 0x16, 0x83);
 322         xgifb_reg_set(P3c4, 0x1B, 0x00);
 323 }
 324
 325 static void XGINew_DDR1x_DefaultRegister(
 326                 struct xgi_hw_device_info *HwDeviceExtension,
 327                 unsigned long Port, struct vb_device_info *pVBInfo)
 328 {
 329         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 330
 331         if (HwDeviceExtension->jChipType >= XG20) {
 332                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 333                 xgifb_reg_set(P3d4,
 334                               0x82,
 335                               pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
 336                 xgifb_reg_set(P3d4,
 337                               0x85,
 338                               pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
 339                 xgifb_reg_set(P3d4,
 340                               0x86,
 341                               pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
 342
 343                 xgifb_reg_set(P3d4, 0x98, 0x01);
 344                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 345
 346                 XGINew_DDR1x_MRS_XG20(P3c4, pVBInfo);
 347         } else {
 348                 XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
 349
 350                 switch (HwDeviceExtension->jChipType) {
 351                 case XG41:
 352                 case XG42:
 353                         /* CR82 */
 354                         xgifb_reg_set(P3d4,
 355                                       0x82,
 356                                       pVBInfo->CR40[11][XGINew_RAMType]);
 357                         /* CR85 */
 358                         xgifb_reg_set(P3d4,
 359                                       0x85,
 360                                       pVBInfo->CR40[12][XGINew_RAMType]);
 361                         /* CR86 */
 362                         xgifb_reg_set(P3d4,
 363                                       0x86,
 364                                       pVBInfo->CR40[13][XGINew_RAMType]);
 365                         break;
 366                 default:
 367                         xgifb_reg_set(P3d4, 0x82, 0x88);
 368                         xgifb_reg_set(P3d4, 0x86, 0x00);
 369                         /* Insert read command for delay */
 370                         xgifb_reg_get(P3d4, 0x86);
 371                         xgifb_reg_set(P3d4, 0x86, 0x88);
 372                         xgifb_reg_get(P3d4, 0x86);
 373                         xgifb_reg_set(P3d4,
 374                                       0x86,
 375                                       pVBInfo->CR40[13][XGINew_RAMType]);
 376                         xgifb_reg_set(P3d4, 0x82, 0x77);
 377                         xgifb_reg_set(P3d4, 0x85, 0x00);
 378
 379                         /* Insert read command for delay */
 380                         xgifb_reg_get(P3d4, 0x85);
 381                         xgifb_reg_set(P3d4, 0x85, 0x88);
 382
 383                         /* Insert read command for delay */
 384                         xgifb_reg_get(P3d4, 0x85);
 385                         /* CR85 */
 386                         xgifb_reg_set(P3d4,
 387                                       0x85,
 388                                       pVBInfo->CR40[12][XGINew_RAMType]);
 389                         /* CR82 */
 390                         xgifb_reg_set(P3d4,
 391                                       0x82,
 392                                       pVBInfo->CR40[11][XGINew_RAMType]);
 393                         break;
 394                 }
 395
 396                 xgifb_reg_set(P3d4, 0x97, 0x00);
 397                 xgifb_reg_set(P3d4, 0x98, 0x01);
 398                 xgifb_reg_set(P3d4, 0x9A, 0x02);
 399                 XGINew_DDR1x_MRS_340(P3c4, pVBInfo);
 400         }
 401 }
 402
 403 static void XGINew_DDR2_DefaultRegister(
 404                 struct xgi_hw_device_info *HwDeviceExtension,
 405                 unsigned long Port, struct vb_device_info *pVBInfo)
 406 {
 407         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 408
 409         /* keep following setting sequence, each setting in
 410          * the same reg insert idle */
 411         xgifb_reg_set(P3d4, 0x82, 0x77);
 412         xgifb_reg_set(P3d4, 0x86, 0x00);
 413         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 414         xgifb_reg_set(P3d4, 0x86, 0x88);
 415         xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
 416         /* CR86 */
 417         xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]);
 418         xgifb_reg_set(P3d4, 0x82, 0x77);
 419         xgifb_reg_set(P3d4, 0x85, 0x00);
 420         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 421         xgifb_reg_set(P3d4, 0x85, 0x88);
 422         xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
 423         xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
 424         if (HwDeviceExtension->jChipType == XG27)
 425                 /* CR82 */
 426                 xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]);
 427         else
 428                 xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
 429
 430         xgifb_reg_set(P3d4, 0x98, 0x01);
 431         xgifb_reg_set(P3d4, 0x9A, 0x02);
 432         if (HwDeviceExtension->jChipType == XG27)
 433                 XGINew_DDRII_Bootup_XG27(HwDeviceExtension, P3c4, pVBInfo);
 434         else
 435                 XGINew_DDR2_MRS_XG20(HwDeviceExtension, P3c4, pVBInfo);
 436 }
 437
 438 static void XGINew_SetDRAMDefaultRegister340(
 439                 struct xgi_hw_device_info *HwDeviceExtension,
 440                 unsigned long Port, struct vb_device_info *pVBInfo)
 441 {
 442         unsigned char temp, temp1, temp2, temp3, i, j, k;
 443
 444         unsigned long P3d4 = Port, P3c4 = Port - 0x10;
 445
 446         xgifb_reg_set(P3d4, 0x6D, pVBInfo->CR40[8][XGINew_RAMType]);
 447         xgifb_reg_set(P3d4, 0x68, pVBInfo->CR40[5][XGINew_RAMType]);
 448         xgifb_reg_set(P3d4, 0x69, pVBInfo->CR40[6][XGINew_RAMType]);
 449         xgifb_reg_set(P3d4, 0x6A, pVBInfo->CR40[7][XGINew_RAMType]);
 450
 451         temp2 = 0;
 452         for (i = 0; i < 4; i++) {
 453                 /* CR6B DQS fine tune delay */
 454                 temp = pVBInfo->CR6B[XGINew_RAMType][i];
 455                 for (j = 0; j < 4; j++) {
 456                         temp1 = ((temp >> (2 * j)) & 0x03) << 2;
 457                         temp2 |= temp1;
 458                         xgifb_reg_set(P3d4, 0x6B, temp2);
 459                         /* Insert read command for delay */
 460                         xgifb_reg_get(P3d4, 0x6B);
 461                         temp2 &= 0xF0;
 462                         temp2 += 0x10;
 463                 }
 464         }
 465
 466         temp2 = 0;
 467         for (i = 0; i < 4; i++) {
 468                 /* CR6E DQM fine tune delay */
 469                 temp = pVBInfo->CR6E[XGINew_RAMType][i];
 470                 for (j = 0; j < 4; j++) {
 471                         temp1 = ((temp >> (2 * j)) & 0x03) << 2;
 472                         temp2 |= temp1;
 473                         xgifb_reg_set(P3d4, 0x6E, temp2);
 474                         /* Insert read command for delay */
 475                         xgifb_reg_get(P3d4, 0x6E);
 476                         temp2 &= 0xF0;
 477                         temp2 += 0x10;
 478                 }
 479         }
 480
 481         temp3 = 0;
 482         for (k = 0; k < 4; k++) {
 483                 /* CR6E_D[1:0] select channel */
 484                 xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
 485                 temp2 = 0;
 486                 for (i = 0; i < 8; i++) {
 487                         /* CR6F DQ fine tune delay */
 488                         temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i];
 489                         for (j = 0; j < 4; j++) {
 490                                 temp1 = (temp >> (2 * j)) & 0x03;
 491                                 temp2 |= temp1;
 492                                 xgifb_reg_set(P3d4, 0x6F, temp2);
 493                                 /* Insert read command for delay */
 494                                 xgifb_reg_get(P3d4, 0x6F);
 495                                 temp2 &= 0xF8;
 496                                 temp2 += 0x08;
 497                         }
 498                 }
 499                 temp3 += 0x01;
 500         }
 501
 502         xgifb_reg_set(P3d4, 0x80, pVBInfo->CR40[9][XGINew_RAMType]); /* CR80 */
 503         xgifb_reg_set(P3d4, 0x81, pVBInfo->CR40[10][XGINew_RAMType]); /* CR81 */
 504
 505         temp2 = 0x80;
 506         /* CR89 terminator type select */
 507         temp = pVBInfo->CR89[XGINew_RAMType][0];
 508         for (j = 0; j < 4; j++) {
 509                 temp1 = (temp >> (2 * j)) & 0x03;
 510                 temp2 |= temp1;
 511                 xgifb_reg_set(P3d4, 0x89, temp2);
 512                 xgifb_reg_get(P3d4, 0x89); /* Insert read command for delay */
 513                 temp2 &= 0xF0;
 514                 temp2 += 0x10;
 515         }
 516
 517         temp = pVBInfo->CR89[XGINew_RAMType][1];
 518         temp1 = temp & 0x03;
 519         temp2 |= temp1;
 520         xgifb_reg_set(P3d4, 0x89, temp2);
 521
 522         temp = pVBInfo->CR40[3][XGINew_RAMType];
 523         temp1 = temp & 0x0F;
 524         temp2 = (temp >> 4) & 0x07;
 525         temp3 = temp & 0x80;
 526         xgifb_reg_set(P3d4, 0x45, temp1); /* CR45 */
 527         xgifb_reg_set(P3d4, 0x99, temp2); /* CR99 */
 528         xgifb_reg_or(P3d4, 0x40, temp3); /* CR40_D[7] */
 529         xgifb_reg_set(P3d4, 0x41, pVBInfo->CR40[0][XGINew_RAMType]); /* CR41 */
 530
 531         if (HwDeviceExtension->jChipType == XG27)
 532                 xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
 533
 534         for (j = 0; j <= 6; j++) /* CR90 - CR96 */
 535                 xgifb_reg_set(P3d4, (0x90 + j),
 536                                 pVBInfo->CR40[14 + j][XGINew_RAMType]);
 537
 538         for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
 539                 xgifb_reg_set(P3d4, (0xC3 + j),
 540                                 pVBInfo->CR40[21 + j][XGINew_RAMType]);
 541
 542         for (j = 0; j < 2; j++) /* CR8A - CR8B */
 543                 xgifb_reg_set(P3d4, (0x8A + j),
 544                                 pVBInfo->CR40[1 + j][XGINew_RAMType]);
 545
 546         if ((HwDeviceExtension->jChipType == XG41) ||
 547             (HwDeviceExtension->jChipType == XG42))
 548                 xgifb_reg_set(P3d4, 0x8C, 0x87);
 549
 550         xgifb_reg_set(P3d4, 0x59, pVBInfo->CR40[4][XGINew_RAMType]); /* CR59 */
 551
 552         xgifb_reg_set(P3d4, 0x83, 0x09); /* CR83 */
 553         xgifb_reg_set(P3d4, 0x87, 0x00); /* CR87 */
 554         xgifb_reg_set(P3d4, 0xCF, *pVBInfo->pCRCF); /* CRCF */
 555         if (XGINew_RAMType) {
 556                 /* xgifb_reg_set(P3c4, 0x17, 0xC0); */ /* SR17 DDRII */
 557                 xgifb_reg_set(P3c4, 0x17, 0x80); /* SR17 DDRII */
 558                 if (HwDeviceExtension->jChipType == XG27)
 559                         xgifb_reg_set(P3c4, 0x17, 0x02); /* SR17 DDRII */
 560
 561         } else {
 562                 xgifb_reg_set(P3c4, 0x17, 0x00); /* SR17 DDR */
 563         }
 564         xgifb_reg_set(P3c4, 0x1A, 0x87); /* SR1A */
 565
 566         temp = XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
 567         if (temp == 0) {
 568                 XGINew_DDR1x_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 569         } else {
 570                 xgifb_reg_set(P3d4, 0xB0, 0x80); /* DDRII Dual frequency mode */
 571                 XGINew_DDR2_DefaultRegister(HwDeviceExtension, P3d4, pVBInfo);
 572         }
 573         xgifb_reg_set(P3c4, 0x1B, pVBInfo->SR15[3][XGINew_RAMType]); /* SR1B */
 574 }
 575
 576 static void XGINew_SetDRAMSizingType(int index,
 577                 unsigned short DRAMTYPE_TABLE[][5],
 578                 struct vb_device_info *pVBInfo)
 579 {
 580         unsigned short data;
 581
 582         data = DRAMTYPE_TABLE[index][4];
 583         xgifb_reg_and_or(pVBInfo->P3c4, 0x13, 0x80, data);
 584         udelay(15);
 585         /* should delay 50 ns */
 586 }
 587
 588 static unsigned short XGINew_SetDRAMSizeReg(int index,
 589                 unsigned short DRAMTYPE_TABLE[][5],
 590                 struct vb_device_info *pVBInfo)
 591 {
 592         unsigned short data = 0, memsize = 0;
 593         int RankSize;
 594         unsigned char ChannelNo;
 595
 596         RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 32;
 597         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 598         data &= 0x80;
 599
 600         if (data == 0x80)
 601                 RankSize *= 2;
 602
 603         data = 0;
 604
 605         if (XGINew_ChannelAB == 3)
 606                 ChannelNo = 4;
 607         else
 608                 ChannelNo = XGINew_ChannelAB;
 609
 610         if (ChannelNo * RankSize <= 256) {
 611                 while ((RankSize >>= 1) > 0)
 612                         data += 0x10;
 613
 614                 memsize = data >> 4;
 615
 616                 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
 617                 xgifb_reg_set(pVBInfo->P3c4,
 618                               0x14,
 619                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 620                                (data & 0xF0));
 621
 622                 /* data |= XGINew_ChannelAB << 2; */
 623                 /* data |= (XGINew_DataBusWidth / 64) << 1; */
 624                 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
 625
 626                 /* should delay */
 627                 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
 628         }
 629         return memsize;
 630 }
 631
 632 static unsigned short XGINew_SetDRAMSize20Reg(int index,
 633                 unsigned short DRAMTYPE_TABLE[][5],
 634                 struct vb_device_info *pVBInfo)
 635 {
 636         unsigned short data = 0, memsize = 0;
 637         int RankSize;
 638         unsigned char ChannelNo;
 639
 640         RankSize = DRAMTYPE_TABLE[index][3] * XGINew_DataBusWidth / 8;
 641         data = xgifb_reg_get(pVBInfo->P3c4, 0x13);
 642         data &= 0x80;
 643
 644         if (data == 0x80)
 645                 RankSize *= 2;
 646
 647         data = 0;
 648
 649         if (XGINew_ChannelAB == 3)
 650                 ChannelNo = 4;
 651         else
 652                 ChannelNo = XGINew_ChannelAB;
 653
 654         if (ChannelNo * RankSize <= 256) {
 655                 while ((RankSize >>= 1) > 0)
 656                         data += 0x10;
 657
 658                 memsize = data >> 4;
 659
 660                 /* [2004/03/25] Vicent, Fix DRAM Sizing Error */
 661                 xgifb_reg_set(pVBInfo->P3c4,
 662                               0x14,
 663                               (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
 664                                 (data & 0xF0));
 665                 udelay(15);
 666
 667                 /* data |= XGINew_ChannelAB << 2; */
 668                 /* data |= (XGINew_DataBusWidth / 64) << 1; */
 669                 /* xgifb_reg_set(pVBInfo->P3c4, 0x14, data); */
 670
 671                 /* should delay */
 672                 /* XGINew_SetDRAMModeRegister340(pVBInfo); */
 673         }
 674         return memsize;
 675 }
 676
 677 static int XGINew_ReadWriteRest(unsigned short StopAddr,
 678                 unsigned short StartAddr, struct vb_device_info *pVBInfo)
 679 {
 680         int i;
 681         unsigned long Position = 0;
 682
 683         *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
 684
 685         for (i = StartAddr; i <= StopAddr; i++) {
 686                 Position = 1 << i;
 687                 *((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
 688         }
 689
 690         udelay(500); /* [Vicent] 2004/04/16.
 691                         Fix #1759 Memory Size error in Multi-Adapter. */
 692
 693         Position = 0;
 694
 695         if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
 696                 return 0;
 697
 698         for (i = StartAddr; i <= StopAddr; i++) {
 699                 Position = 1 << i;
 700                 if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) !=
 701                     Position)
 702                         return 0;
 703         }
 704         return 1;
 705 }
 706
 707 static unsigned char XGINew_CheckFrequence(struct vb_device_info *pVBInfo)
 708 {
 709         unsigned char data;
 710
 711         data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 712
 713         if ((data & 0x10) == 0) {
 714                 data = xgifb_reg_get(pVBInfo->P3c4, 0x39);
 715                 data = (data & 0x02) >> 1;
 716                 return data;
 717         } else {
 718                 return data & 0x01;
 719         }
 720 }
 721
 722 static void XGINew_CheckChannel(struct xgi_hw_device_info *HwDeviceExtension,
 723                 struct vb_device_info *pVBInfo)
 724 {
 725         unsigned char data;
 726
 727         switch (HwDeviceExtension->jChipType) {
 728         case XG20:
 729         case XG21:
 730                 data = xgifb_reg_get(pVBInfo->P3d4, 0x97);
 731                 data = data & 0x01;
 732                 XGINew_ChannelAB = 1; /* XG20 "JUST" one channel */
 733
 734                 if (data == 0) { /* Single_32_16 */
 735
 736                         if ((HwDeviceExtension->ulVideoMemorySize - 1)
 737                                         > 0x1000000) {
 738
 739                                 XGINew_DataBusWidth = 32; /* 32 bits */
 740                                 /* 22bit + 2 rank + 32bit */
 741                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 742                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 743                                 udelay(15);
 744
 745                                 if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 746                                         return;
 747
 748                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 749                                     0x800000) {
 750                                         /* 22bit + 1 rank + 32bit */
 751                                         xgifb_reg_set(pVBInfo->P3c4,
 752                                                       0x13,
 753                                                       0x31);
 754                                         xgifb_reg_set(pVBInfo->P3c4,
 755                                                       0x14,
 756                                                       0x42);
 757                                         udelay(15);
 758
 759                                         if (XGINew_ReadWriteRest(23,
 760                                                                  23,
 761                                                                  pVBInfo) == 1)
 762                                                 return;
 763                                 }
 764                         }
 765
 766                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 767                             0x800000) {
 768                                 XGINew_DataBusWidth = 16; /* 16 bits */
 769                                 /* 22bit + 2 rank + 16bit */
 770                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 771                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 772                                 udelay(15);
 773
 774                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 775                                         return;
 776                                 else
 777                                         xgifb_reg_set(pVBInfo->P3c4,
 778                                                       0x13,
 779                                                       0x31);
 780                                 udelay(15);
 781                         }
 782
 783                 } else { /* Dual_16_8 */
 784                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 785                             0x800000) {
 786                                 XGINew_DataBusWidth = 16; /* 16 bits */
 787                                 /* (0x31:12x8x2) 22bit + 2 rank */
 788                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 789                                 /* 0x41:16Mx16 bit*/
 790                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
 791                                 udelay(15);
 792
 793                                 if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 794                                         return;
 795
 796                                 if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 797                                     0x400000) {
 798                                         /* (0x31:12x8x2) 22bit + 1 rank */
 799                                         xgifb_reg_set(pVBInfo->P3c4,
 800                                                       0x13,
 801                                                       0x31);
 802                                         /* 0x31:8Mx16 bit*/
 803                                         xgifb_reg_set(pVBInfo->P3c4,
 804                                                       0x14,
 805                                                       0x31);
 806                                         udelay(15);
 807
 808                                         if (XGINew_ReadWriteRest(22,
 809                                                                  22,
 810                                                                  pVBInfo) == 1)
 811                                                 return;
 812                                 }
 813                         }
 814
 815                         if ((HwDeviceExtension->ulVideoMemorySize - 1) >
 816                             0x400000) {
 817                                 XGINew_DataBusWidth = 8; /* 8 bits */
 818                                 /* (0x31:12x8x2) 22bit + 2 rank */
 819                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
 820                                 /* 0x30:8Mx8 bit*/
 821                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 822                                 udelay(15);
 823
 824                                 if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
 825                                         return;
 826                                 else /* (0x31:12x8x2) 22bit + 1 rank */
 827                                         xgifb_reg_set(pVBInfo->P3c4,
 828                                                       0x13,
 829                                                       0x31);
 830                                 udelay(15);
 831                         }
 832                 }
 833                 break;
 834
 835         case XG27:
 836                 XGINew_DataBusWidth = 16; /* 16 bits */
 837                 XGINew_ChannelAB = 1; /* Single channel */
 838                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x51); /* 32Mx16 bit*/
 839                 break;
 840         case XG41:
 841                 if (XGINew_CheckFrequence(pVBInfo) == 1) {
 842                         XGINew_DataBusWidth = 32; /* 32 bits */
 843                         XGINew_ChannelAB = 3; /* Quad Channel */
 844                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 845                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 846
 847                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 848                                 return;
 849
 850                         XGINew_ChannelAB = 2; /* Dual channels */
 851                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 852
 853                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 854                                 return;
 855
 856                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x49);
 857
 858                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 859                                 return;
 860
 861                         XGINew_ChannelAB = 3;
 862                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 863                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 864
 865                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 866                                 return;
 867
 868                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 869
 870                         if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
 871                                 return;
 872                         else
 873                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x39);
 874                 } else { /* DDR */
 875                         XGINew_DataBusWidth = 64; /* 64 bits */
 876                         XGINew_ChannelAB = 2; /* Dual channels */
 877                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 878                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
 879
 880                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1)
 881                                 return;
 882
 883                         XGINew_ChannelAB = 1; /* Single channels */
 884                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 885
 886                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 887                                 return;
 888
 889                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x53);
 890
 891                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 892                                 return;
 893
 894                         XGINew_ChannelAB = 2; /* Dual channels */
 895                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 896                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
 897
 898                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 899                                 return;
 900
 901                         XGINew_ChannelAB = 1; /* Single channels */
 902                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 903
 904                         if (XGINew_ReadWriteRest(8, 4, pVBInfo) == 1)
 905                                 return;
 906                         else
 907                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x43);
 908                 }
 909
 910                 break;
 911
 912         case XG42:
 913                 /*
 914                  XG42 SR14 D[3] Reserve
 915                  D[2] = 1, Dual Channel
 916                  = 0, Single Channel
 917
 918                  It's Different from Other XG40 Series.
 919                  */
 920                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII, DDR2x */
 921                         XGINew_DataBusWidth = 32; /* 32 bits */
 922                         XGINew_ChannelAB = 2; /* 2 Channel */
 923                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 924                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x44);
 925
 926                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 927                                 return;
 928
 929                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 930                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x34);
 931                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 932                                 return;
 933
 934                         XGINew_ChannelAB = 1; /* Single Channel */
 935                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 936                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x40);
 937
 938                         if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
 939                                 return;
 940                         else {
 941                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 942                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
 943                         }
 944                 } else { /* DDR */
 945                         XGINew_DataBusWidth = 64; /* 64 bits */
 946                         XGINew_ChannelAB = 1; /* 1 channels */
 947                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 948                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
 949
 950                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 951                                 return;
 952                         else {
 953                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 954                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
 955                         }
 956                 }
 957
 958                 break;
 959
 960         default: /* XG40 */
 961
 962                 if (XGINew_CheckFrequence(pVBInfo) == 1) { /* DDRII */
 963                         XGINew_DataBusWidth = 32; /* 32 bits */
 964                         XGINew_ChannelAB = 3;
 965                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 966                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4C);
 967
 968                         if (XGINew_ReadWriteRest(25, 23, pVBInfo) == 1)
 969                                 return;
 970
 971                         XGINew_ChannelAB = 2; /* 2 channels */
 972                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x48);
 973
 974                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
 975                                 return;
 976
 977                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 978                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x3C);
 979
 980                         if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1) {
 981                                 XGINew_ChannelAB = 3; /* 4 channels */
 982                         } else {
 983                                 XGINew_ChannelAB = 2; /* 2 channels */
 984                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x38);
 985                         }
 986                 } else { /* DDR */
 987                         XGINew_DataBusWidth = 64; /* 64 bits */
 988                         XGINew_ChannelAB = 2; /* 2 channels */
 989                         xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xA1);
 990                         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x5A);
 991
 992                         if (XGINew_ReadWriteRest(25, 24, pVBInfo) == 1) {
 993                                 return;
 994                         } else {
 995                                 xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x21);
 996                                 xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x4A);
 997                         }
 998                 }
 999                 break;
1000         }
1001 }
1002
1003 static int XGINew_DDRSizing340(struct xgi_hw_device_info *HwDeviceExtension,
1004                 struct vb_device_info *pVBInfo)
1005 {
1006         int i;
1007         unsigned short memsize, addr;
1008
1009         xgifb_reg_set(pVBInfo->P3c4, 0x15, 0x00); /* noninterleaving */
1010         xgifb_reg_set(pVBInfo->P3c4, 0x1C, 0x00); /* nontiling */
1011         XGINew_CheckChannel(HwDeviceExtension, pVBInfo);
1012
1013         if (HwDeviceExtension->jChipType >= XG20) {
1014                 for (i = 0; i < 12; i++) {
1015                         XGINew_SetDRAMSizingType(i,
1016                                                  XGINew_DDRDRAM_TYPE20,
1017                                                  pVBInfo);
1018                         memsize = XGINew_SetDRAMSize20Reg(i,
1019                                                           XGINew_DDRDRAM_TYPE20,
1020                                                           pVBInfo);
1021                         if (memsize == 0)
1022                                 continue;
1023
1024                         addr = memsize + (XGINew_ChannelAB - 2) + 20;
1025                         if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1026                             (unsigned long) (1 << addr))
1027                                 continue;
1028
1029                         if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
1030                                 return 1;
1031                 }
1032         } else {
1033                 for (i = 0; i < 4; i++) {
1034                         XGINew_SetDRAMSizingType(i,
1035                                                  XGINew_DDRDRAM_TYPE340,
1036                                                  pVBInfo);
1037                         memsize = XGINew_SetDRAMSizeReg(i,
1038                                                         XGINew_DDRDRAM_TYPE340,
1039                                                         pVBInfo);
1040
1041                         if (memsize == 0)
1042                                 continue;
1043
1044                         addr = memsize + (XGINew_ChannelAB - 2) + 20;
1045                         if ((HwDeviceExtension->ulVideoMemorySize - 1) <
1046                             (unsigned long) (1 << addr))
1047                                 continue;
1048
1049                         if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
1050                                 return 1;
1051                 }
1052         }
1053         return 0;
1054 }
1055
1056 static void XGINew_SetDRAMSize_340(struct xgi_hw_device_info *HwDeviceExtension,
1057                 struct vb_device_info *pVBInfo)
1058 {
1059         unsigned short data;
1060
1061         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1062         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1063
1064         XGISetModeNew(HwDeviceExtension, 0x2e);
1065
1066         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1067         /* disable read cache */
1068         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
1069         XGI_DisplayOff(HwDeviceExtension, pVBInfo);
1070
1071         /* data = xgifb_reg_get(pVBInfo->P3c4, 0x1); */
1072         /* data |= 0x20 ; */
1073         /* xgifb_reg_set(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
1074         XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
1075         data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
1076         /* enable read cache */
1077         xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
1078 }
1079
1080 static void ReadVBIOSTablData(unsigned char ChipType,
1081                               struct vb_device_info *pVBInfo)
1082 {
1083         volatile unsigned char *pVideoMemory =
1084                 (unsigned char *) pVBInfo->ROMAddr;
1085         unsigned long i;
1086         unsigned char j, k;
1087         /* Volari customize data area end */
1088
1089         if (ChipType == XG21) {
1090                 pVBInfo->IF_DEF_LVDS = 0;
1091                 if (pVideoMemory[0x65] & 0x1) {
1092                         pVBInfo->IF_DEF_LVDS = 1;
1093                         i = pVideoMemory[0x316] | (pVideoMemory[0x317] << 8);
1094                         j = pVideoMemory[i - 1];
1095                         if (j != 0xff) {
1096                                 k = 0;
1097                                 do {
1098                                         pVBInfo->XG21_LVDSCapList[k].
1099                                                  LVDS_Capability
1100                                                 = pVideoMemory[i] |
1101                                                  (pVideoMemory[i + 1] << 8);
1102                                         pVBInfo->XG21_LVDSCapList[k].LVDSHT
1103                                                 = pVideoMemory[i + 2] |
1104                                                   (pVideoMemory[i + 3] << 8);
1105                                         pVBInfo->XG21_LVDSCapList[k].LVDSVT
1106                                                 = pVideoMemory[i + 4] |
1107                                                   (pVideoMemory[i + 5] << 8);
1108                                         pVBInfo->XG21_LVDSCapList[k].LVDSHDE
1109                                                 = pVideoMemory[i + 6] |
1110                                                   (pVideoMemory[i + 7] << 8);
1111                                         pVBInfo->XG21_LVDSCapList[k].LVDSVDE
1112                                                 = pVideoMemory[i + 8] |
1113                                                   (pVideoMemory[i + 9] << 8);
1114                                         pVBInfo->XG21_LVDSCapList[k].LVDSHFP
1115                                                 = pVideoMemory[i + 10] |
1116                                                   (pVideoMemory[i + 11] << 8);
1117                                         pVBInfo->XG21_LVDSCapList[k].LVDSVFP
1118                                                 = pVideoMemory[i + 12] |
1119                                                   (pVideoMemory[i + 13] << 8);
1120                                         pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
1121                                                 = pVideoMemory[i + 14] |
1122                                                   (pVideoMemory[i + 15] << 8);
1123                                         pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
1124                                                 = pVideoMemory[i + 16] |
1125                                                   (pVideoMemory[i + 17] << 8);
1126                                         pVBInfo->XG21_LVDSCapList[k].VCLKData1
1127                                                 = pVideoMemory[i + 18];
1128                                         pVBInfo->XG21_LVDSCapList[k].VCLKData2
1129                                                 = pVideoMemory[i + 19];
1130                                         pVBInfo->XG21_LVDSCapList[k].PSC_S1
1131                                                 = pVideoMemory[i + 20];
1132                                         pVBInfo->XG21_LVDSCapList[k].PSC_S2
1133                                                 = pVideoMemory[i + 21];
1134                                         pVBInfo->XG21_LVDSCapList[k].PSC_S3
1135                                                 = pVideoMemory[i + 22];
1136                                         pVBInfo->XG21_LVDSCapList[k].PSC_S4
1137                                                 = pVideoMemory[i + 23];
1138                                         pVBInfo->XG21_LVDSCapList[k].PSC_S5
1139                                                 = pVideoMemory[i + 24];
1140                                         i += 25;
1141                                         j--;
1142                                         k++;
1143                                 } while ((j > 0) &&
1144                                          (k < (sizeof(XGI21_LCDCapList) /
1145                                                sizeof(struct
1146                                                         XGI21_LVDSCapStruct))));
1147                         } else {
1148                                 pVBInfo->XG21_LVDSCapList[0].LVDS_Capability
1149                                                 = pVideoMemory[i] |
1150                                                   (pVideoMemory[i + 1] << 8);
1151                                 pVBInfo->XG21_LVDSCapList[0].LVDSHT
1152                                                 = pVideoMemory[i + 2] |
1153                                                   (pVideoMemory[i + 3] << 8);
1154                                 pVBInfo->XG21_LVDSCapList[0].LVDSVT
1155                                                 = pVideoMemory[i + 4] |
1156                                                   (pVideoMemory[i + 5] << 8);
1157                                 pVBInfo->XG21_LVDSCapList[0].LVDSHDE
1158                                                 = pVideoMemory[i + 6] |
1159                                                   (pVideoMemory[i + 7] << 8);
1160                                 pVBInfo->XG21_LVDSCapList[0].LVDSVDE
1161                                                 = pVideoMemory[i + 8] |
1162                                                   (pVideoMemory[i + 9] << 8);
1163                                 pVBInfo->XG21_LVDSCapList[0].LVDSHFP
1164                                                 = pVideoMemory[i + 10] |
1165                                                   (pVideoMemory[i + 11] << 8);
1166                                 pVBInfo->XG21_LVDSCapList[0].LVDSVFP
1167                                                 = pVideoMemory[i + 12] |
1168                                                   (pVideoMemory[i + 13] << 8);
1169                                 pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC
1170                                                 = pVideoMemory[i + 14] |
1171                                                   (pVideoMemory[i + 15] << 8);
1172                                 pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC
1173                                                 = pVideoMemory[i + 16] |
1174                                                   (pVideoMemory[i + 17] << 8);
1175                                 pVBInfo->XG21_LVDSCapList[0].VCLKData1
1176                                                 = pVideoMemory[i + 18];
1177                                 pVBInfo->XG21_LVDSCapList[0].VCLKData2
1178                                                 = pVideoMemory[i + 19];
1179                                 pVBInfo->XG21_LVDSCapList[0].PSC_S1
1180                                                 = pVideoMemory[i + 20];
1181                                 pVBInfo->XG21_LVDSCapList[0].PSC_S2
1182                                                 = pVideoMemory[i + 21];
1183                                 pVBInfo->XG21_LVDSCapList[0].PSC_S3
1184                                                 = pVideoMemory[i + 22];
1185                                 pVBInfo->XG21_LVDSCapList[0].PSC_S4
1186                                                 = pVideoMemory[i + 23];
1187                                 pVBInfo->XG21_LVDSCapList[0].PSC_S5
1188                                                 = pVideoMemory[i + 24];
1189                         }
1190                 }
1191         }
1192 }
1193
1194 static void XGINew_ChkSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
1195                 struct vb_device_info *pVBInfo)
1196 {
1197         unsigned short tempbx = 0, temp, tempcx, CR3CData;
1198
1199         temp = xgifb_reg_get(pVBInfo->P3d4, 0x32);
1200
1201         if (temp & Monitor1Sense)
1202                 tempbx |= ActiveCRT1;
1203         if (temp & LCDSense)
1204                 tempbx |= ActiveLCD;
1205         if (temp & Monitor2Sense)
1206                 tempbx |= ActiveCRT2;
1207         if (temp & TVSense) {
1208                 tempbx |= ActiveTV;
1209                 if (temp & AVIDEOSense)
1210                         tempbx |= (ActiveAVideo << 8);
1211                 if (temp & SVIDEOSense)
1212                         tempbx |= (ActiveSVideo << 8);
1213                 if (temp & SCARTSense)
1214                         tempbx |= (ActiveSCART << 8);
1215                 if (temp & HiTVSense)
1216                         tempbx |= (ActiveHiTV << 8);
1217                 if (temp & YPbPrSense)
1218                         tempbx |= (ActiveYPbPr << 8);
1219         }
1220
1221         tempcx = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1222         tempcx |= (xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8);
1223
1224         if (tempbx & tempcx) {
1225                 CR3CData = xgifb_reg_get(pVBInfo->P3d4, 0x3c);
1226                 if (!(CR3CData & DisplayDeviceFromCMOS)) {
1227                         tempcx = 0x1FF0;
1228                         if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1229                                 tempbx = 0x1FF0;
1230                 }
1231         } else {
1232                 tempcx = 0x1FF0;
1233                 if (*pVBInfo->pSoftSetting & ModeSoftSetting)
1234                         tempbx = 0x1FF0;
1235         }
1236
1237         tempbx &= tempcx;
1238         xgifb_reg_set(pVBInfo->P3d4, 0x3d, (tempbx & 0x00FF));
1239         xgifb_reg_set(pVBInfo->P3d4, 0x3e, ((tempbx & 0xFF00) >> 8));
1240 }
1241
1242 static void XGINew_SetModeScratch(struct xgi_hw_device_info *HwDeviceExtension,
1243                 struct vb_device_info *pVBInfo)
1244 {
1245         unsigned short temp, tempcl = 0, tempch = 0, CR31Data, CR38Data;
1246
1247         temp = xgifb_reg_get(pVBInfo->P3d4, 0x3d);
1248         temp |= xgifb_reg_get(pVBInfo->P3d4, 0x3e) << 8;
1249         temp |= (xgifb_reg_get(pVBInfo->P3d4, 0x31) & (DriverMode >> 8)) << 8;
1250
1251         if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
1252                 if (temp & ActiveCRT2)
1253                         tempcl = SetCRT2ToRAMDAC;
1254         }
1255
1256         if (temp & ActiveLCD) {
1257                 tempcl |= SetCRT2ToLCD;
1258                 if (temp & DriverMode) {
1259                         if (temp & ActiveTV) {
1260                                 tempch = SetToLCDA | EnableDualEdge;
1261                                 temp ^= SetCRT2ToLCD;
1262
1263                                 if ((temp >> 8) & ActiveAVideo)
1264                                         tempcl |= SetCRT2ToAVIDEO;
1265                                 if ((temp >> 8) & ActiveSVideo)
1266                                         tempcl |= SetCRT2ToSVIDEO;
1267                                 if ((temp >> 8) & ActiveSCART)
1268                                         tempcl |= SetCRT2ToSCART;
1269
1270                                 if (pVBInfo->IF_DEF_HiVision == 1) {
1271                                         if ((temp >> 8) & ActiveHiTV)
1272                                                 tempcl |= SetCRT2ToHiVisionTV;
1273                                 }
1274
1275                                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1276                                         if ((temp >> 8) & ActiveYPbPr)
1277                                                 tempch |= SetYPbPr;
1278                                 }
1279                         }
1280                 }
1281         } else {
1282                 if ((temp >> 8) & ActiveAVideo)
1283                         tempcl |= SetCRT2ToAVIDEO;
1284                 if ((temp >> 8) & ActiveSVideo)
1285                         tempcl |= SetCRT2ToSVIDEO;
1286                 if ((temp >> 8) & ActiveSCART)
1287                         tempcl |= SetCRT2ToSCART;
1288
1289                 if (pVBInfo->IF_DEF_HiVision == 1) {
1290                         if ((temp >> 8) & ActiveHiTV)
1291                                 tempcl |= SetCRT2ToHiVisionTV;
1292                 }
1293
1294                 if (pVBInfo->IF_DEF_YPbPr == 1) {
1295                         if ((temp >> 8) & ActiveYPbPr)
1296                                 tempch |= SetYPbPr;
1297                 }
1298         }
1299
1300         tempcl |= SetSimuScanMode;
1301         if ((!(temp & ActiveCRT1)) && ((temp & ActiveLCD) || (temp & ActiveTV)
1302                         || (temp & ActiveCRT2)))
1303                 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1304         if ((temp & ActiveLCD) && (temp & ActiveTV))
1305                 tempcl ^= (SetSimuScanMode | SwitchToCRT2);
1306         xgifb_reg_set(pVBInfo->P3d4, 0x30, tempcl);
1307
1308         CR31Data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
1309         CR31Data &= ~(SetNotSimuMode >> 8);
1310         if (!(temp & ActiveCRT1))
1311                 CR31Data |= (SetNotSimuMode >> 8);
1312         CR31Data &= ~(DisableCRT2Display >> 8);
1313         if (!((temp & ActiveLCD) || (temp & ActiveTV) || (temp & ActiveCRT2)))
1314                 CR31Data |= (DisableCRT2Display >> 8);
1315         xgifb_reg_set(pVBInfo->P3d4, 0x31, CR31Data);
1316
1317         CR38Data = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1318         CR38Data &= ~SetYPbPr;
1319         CR38Data |= tempch;
1320         xgifb_reg_set(pVBInfo->P3d4, 0x38, CR38Data);
1321
1322 }
1323
1324 static void XGINew_GetXG21Sense(struct xgi_hw_device_info *HwDeviceExtension,
1325                 struct vb_device_info *pVBInfo)
1326 {
1327         unsigned char Temp;
1328         volatile unsigned char *pVideoMemory =
1329                         (unsigned char *) pVBInfo->ROMAddr;
1330
1331         pVBInfo->IF_DEF_LVDS = 0;
1332
1333 #if 1
1334         if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
1335                 pVBInfo->IF_DEF_LVDS = 1;
1336                 xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1337                 /* LVDS on chip */
1338                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1339         } else {
1340 #endif
1341                 /* Enable GPIOA/B read  */
1342                 xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1343                 Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
1344                 if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
1345                         XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
1346                         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1347                         /* Enable read GPIOF */
1348                         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
1349                         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
1350                         if (!Temp)
1351                                 xgifb_reg_and_or(pVBInfo->P3d4,
1352                                                  0x38,
1353                                                  ~0xE0,
1354                                                  0x80); /* TMDS on chip */
1355                         else
1356                                 xgifb_reg_and_or(pVBInfo->P3d4,
1357                                                  0x38,
1358                                                  ~0xE0,
1359                                                  0xA0); /* Only DVO on chip */
1360                         /* Disable read GPIOF */
1361                         xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
1362                 }
1363 #if 1
1364         }
1365 #endif
1366 }
1367
1368 static void XGINew_GetXG27Sense(struct xgi_hw_device_info *HwDeviceExtension,
1369                 struct vb_device_info *pVBInfo)
1370 {
1371         unsigned char Temp, bCR4A;
1372
1373         pVBInfo->IF_DEF_LVDS = 0;
1374         bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1375         /* Enable GPIOA/B/C read  */
1376         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
1377         Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
1378         xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
1379
1380         if (Temp <= 0x02) {
1381                 pVBInfo->IF_DEF_LVDS = 1;
1382                 /* LVDS setting */
1383                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
1384                 xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
1385         } else {
1386                 /* TMDS/DVO setting */
1387                 xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
1388         }
1389         xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
1390
1391 }
1392
1393 static unsigned char GetXG21FPBits(struct vb_device_info *pVBInfo)
1394 {
1395         unsigned char CR38, CR4A, temp;
1396
1397         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1398         /* enable GPIOE read */
1399         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
1400         CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
1401         temp = 0;
1402         if ((CR38 & 0xE0) > 0x80) {
1403                 temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1404                 temp &= 0x08;
1405                 temp >>= 3;
1406         }
1407
1408         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1409
1410         return temp;
1411 }
1412
1413 static unsigned char GetXG27FPBits(struct vb_device_info *pVBInfo)
1414 {
1415         unsigned char CR4A, temp;
1416
1417         CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
1418         /* enable GPIOA/B/C read */
1419         xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
1420         temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
1421         if (temp <= 2)
1422                 temp &= 0x03;
1423         else
1424                 temp = ((temp & 0x04) >> 1) || ((~temp) & 0x01);
1425
1426         xgifb_reg_set(pVBInfo->P3d4, 0x4A, CR4A);
1427
1428         return temp;
1429 }
1430
1431 unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension)
1432 {
1433         struct vb_device_info VBINF;
1434         struct vb_device_info *pVBInfo = &VBINF;
1435         unsigned char i, temp = 0, temp1;
1436         /* VBIOSVersion[5]; */
1437         volatile unsigned char *pVideoMemory;
1438
1439         /* unsigned long j, k; */
1440
1441         unsigned long Temp;
1442
1443         pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
1444
1445         pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress;
1446
1447         pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
1448
1449         pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
1450
1451         /* Newdebugcode(0x99); */
1452
1453
1454         /* if (pVBInfo->ROMAddr == 0) */
1455         /* return(0); */
1456
1457         if (pVBInfo->FBAddr == NULL) {
1458                 printk("\n pVBInfo->FBAddr == 0 ");
1459                 return 0;
1460         }
1461         printk("1");
1462         if (pVBInfo->BaseAddr == 0) {
1463                 printk("\npVBInfo->BaseAddr == 0 ");
1464                 return 0;
1465         }
1466         printk("2");
1467
1468         outb(0x67, (pVBInfo->BaseAddr + 0x12)); /* 3c2 <- 67 ,ynlai */
1469
1470         pVBInfo->ISXPDOS = 0;
1471         printk("3");
1472
1473         printk("4");
1474
1475         /* VBIOSVersion[4] = 0x0; */
1476
1477         /* 09/07/99 modify by domao */
1478
1479         pVBInfo->P3c4 = pVBInfo->BaseAddr + 0x14;
1480         pVBInfo->P3d4 = pVBInfo->BaseAddr + 0x24;
1481         pVBInfo->P3c0 = pVBInfo->BaseAddr + 0x10;
1482         pVBInfo->P3ce = pVBInfo->BaseAddr + 0x1e;
1483         pVBInfo->P3c2 = pVBInfo->BaseAddr + 0x12;
1484         pVBInfo->P3ca = pVBInfo->BaseAddr + 0x1a;
1485         pVBInfo->P3c6 = pVBInfo->BaseAddr + 0x16;
1486         pVBInfo->P3c7 = pVBInfo->BaseAddr + 0x17;
1487         pVBInfo->P3c8 = pVBInfo->BaseAddr + 0x18;
1488         pVBInfo->P3c9 = pVBInfo->BaseAddr + 0x19;
1489         pVBInfo->P3da = pVBInfo->BaseAddr + 0x2A;
1490         pVBInfo->Part0Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_00;
1491         pVBInfo->Part1Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_04;
1492         pVBInfo->Part2Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_10;
1493         pVBInfo->Part3Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_12;
1494         pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
1495         pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
1496         printk("5");
1497
1498         if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
1499                 /* Run XGI_GetVBType before InitTo330Pointer */
1500                 XGI_GetVBType(pVBInfo);
1501
1502         InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
1503
1504         /* ReadVBIOSData */
1505         ReadVBIOSTablData(HwDeviceExtension->jChipType, pVBInfo);
1506
1507         /* 1.Openkey */
1508         xgifb_reg_set(pVBInfo->P3c4, 0x05, 0x86);
1509         printk("6");
1510
1511         /* GetXG21Sense (GPIO) */
1512         if (HwDeviceExtension->jChipType == XG21)
1513                 XGINew_GetXG21Sense(HwDeviceExtension, pVBInfo);
1514
1515         if (HwDeviceExtension->jChipType == XG27)
1516                 XGINew_GetXG27Sense(HwDeviceExtension, pVBInfo);
1517
1518         printk("7");
1519
1520         /* 2.Reset Extended register */
1521
1522         for (i = 0x06; i < 0x20; i++)
1523                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1524
1525         for (i = 0x21; i <= 0x27; i++)
1526                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1527
1528         /* for(i = 0x06; i <= 0x27; i++) */
1529         /* xgifb_reg_set(pVBInfo->P3c4, i, 0); */
1530
1531         printk("8");
1532
1533         for (i = 0x31; i <= 0x3B; i++)
1534                 xgifb_reg_set(pVBInfo->P3c4, i, 0);
1535         printk("9");
1536
1537         /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
1538         if (HwDeviceExtension->jChipType == XG42)
1539                 xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
1540
1541         /* for (i = 0x30; i <= 0x3F; i++) */
1542         /* xgifb_reg_set(pVBInfo->P3d4, i, 0); */
1543
1544         for (i = 0x79; i <= 0x7C; i++)
1545                 xgifb_reg_set(pVBInfo->P3d4, i, 0); /* shampoo 0208 */
1546
1547         printk("10");
1548
1549         if (HwDeviceExtension->jChipType >= XG20)
1550                 xgifb_reg_set(pVBInfo->P3d4, 0x97, *pVBInfo->pXGINew_CR97);
1551
1552         /* 3.SetMemoryClock
1553
1554          XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension,
1555                                                       pVBInfo);
1556         */
1557
1558         printk("11");
1559
1560         /* 4.SetDefExt1Regs begin */
1561         xgifb_reg_set(pVBInfo->P3c4, 0x07, *pVBInfo->pSR07);
1562         if (HwDeviceExtension->jChipType == XG27) {
1563                 xgifb_reg_set(pVBInfo->P3c4, 0x40, *pVBInfo->pSR40);
1564                 xgifb_reg_set(pVBInfo->P3c4, 0x41, *pVBInfo->pSR41);
1565         }
1566         xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
1567         xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
1568         /* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */
1569         /* alan, 2001/6/26 Frame buffer can read/write SR20 */
1570         xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
1571         /* Hsuan, 2006/01/01 H/W request for slow corner chip */
1572         xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
1573         if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
1574                 xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
1575
1576         /* SR11 = 0x0F; */
1577         /* xgifb_reg_set(pVBInfo->P3c4, 0x11, SR11); */
1578
1579         printk("12");
1580
1581         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1582                 /* Set AGP Rate */
1583                 /*
1584                 temp1 = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
1585                 temp1 &= 0x02;
1586                 if (temp1 == 0x02) {
1587                         outl(0x80000000, 0xcf8);
1588                         ChipsetID = inl(0x0cfc);
1589                         outl(0x8000002C, 0xcf8);
1590                         VendorID = inl(0x0cfc);
1591                         VendorID &= 0x0000FFFF;
1592                         outl(0x8001002C, 0xcf8);
1593                         GraphicVendorID = inl(0x0cfc);
1594                         GraphicVendorID &= 0x0000FFFF;
1595
1596                         if (ChipsetID == 0x7301039)
1597                                 xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x09);
1598
1599                         ChipsetID &= 0x0000FFFF;
1600
1601                         if ((ChipsetID == 0x700E) ||
1602                             (ChipsetID == 0x1022) ||
1603                             (ChipsetID == 0x1106) ||
1604                             (ChipsetID == 0x10DE)) {
1605                                 if (ChipsetID == 0x1106) {
1606                                         if ((VendorID == 0x1019) &&
1607                                             (GraphicVendorID == 0x1019))
1608                                                 xgifb_reg_set(pVBInfo->P3d4,
1609                                                               0x5F,
1610                                                               0x0D);
1611                                         else
1612                                                 xgifb_reg_set(pVBInfo->P3d4,
1613                                                               0x5F,
1614                                                               0x0B);
1615                                 } else {
1616                                         xgifb_reg_set(pVBInfo->P3d4,
1617                                                       0x5F,
1618                                                       0x0B);
1619                                 }
1620                         }
1621                 }
1622                 */
1623
1624                 printk("13");
1625
1626                 /* Set AGP customize registers (in SetDefAGPRegs) Start */
1627                 for (i = 0x47; i <= 0x4C; i++)
1628                         xgifb_reg_set(pVBInfo->P3d4,
1629                                       i,
1630                                       pVBInfo->AGPReg[i - 0x47]);
1631
1632                 for (i = 0x70; i <= 0x71; i++)
1633                         xgifb_reg_set(pVBInfo->P3d4,
1634                                       i,
1635                                       pVBInfo->AGPReg[6 + i - 0x70]);
1636
1637                 for (i = 0x74; i <= 0x77; i++)
1638                         xgifb_reg_set(pVBInfo->P3d4,
1639                                       i,
1640                                       pVBInfo->AGPReg[8 + i - 0x74]);
1641                 /* Set AGP customize registers (in SetDefAGPRegs) End */
1642                 /* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
1643                 /*        outl(0x80000000, 0xcf8); */
1644                 /*        ChipsetID = inl(0x0cfc); */
1645                 /*        if (ChipsetID == 0x25308086) */
1646                 /*            xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */
1647
1648                 HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension,
1649                                                         0x50,
1650                                                         0,
1651                                                         &Temp); /* Get */
1652                 Temp >>= 20;
1653                 Temp &= 0xF;
1654
1655                 if (Temp == 1)
1656                         xgifb_reg_set(pVBInfo->P3d4, 0x48, 0x20); /* CR48 */
1657                 printk("14");
1658         } /* != XG20 */
1659
1660         /* Set PCI */
1661         xgifb_reg_set(pVBInfo->P3c4, 0x23, *pVBInfo->pSR23);
1662         xgifb_reg_set(pVBInfo->P3c4, 0x24, *pVBInfo->pSR24);
1663         xgifb_reg_set(pVBInfo->P3c4, 0x25, pVBInfo->SR25[0]);
1664         printk("15");
1665
1666         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1667                 /* Set VB */
1668                 XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
1669                 /* alan, disable VideoCapture */
1670                 xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
1671                 xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
1672                 /* chk if BCLK>=100MHz */
1673                 temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B);
1674                 temp = (unsigned char) ((temp1 >> 4) & 0x0F);
1675
1676                 xgifb_reg_set(pVBInfo->Part1Port,
1677                               0x02,
1678                               (*pVBInfo->pCRT2Data_1_2));
1679
1680                 printk("16");
1681
1682                 xgifb_reg_set(pVBInfo->Part1Port, 0x2E, 0x08); /* use VB */
1683         } /* != XG20 */
1684
1685         xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
1686
1687         if ((HwDeviceExtension->jChipType == XG42) &&
1688             XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
1689                 /* Not DDR */
1690                 xgifb_reg_set(pVBInfo->P3c4,
1691                               0x31,
1692                               (*pVBInfo->pSR31 & 0x3F) | 0x40);
1693                 xgifb_reg_set(pVBInfo->P3c4,
1694                               0x32,
1695                               (*pVBInfo->pSR32 & 0xFC) | 0x01);
1696         } else {
1697                 xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
1698                 xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
1699         }
1700         xgifb_reg_set(pVBInfo->P3c4, 0x33, *pVBInfo->pSR33);
1701         printk("17");
1702
1703         /*
1704          SetPowerConsume (HwDeviceExtension, pVBInfo->P3c4);    */
1705
1706         if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
1707                 if (XGI_BridgeIsOn(pVBInfo) == 1) {
1708                         if (pVBInfo->IF_DEF_LVDS == 0) {
1709                                 xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
1710                                 xgifb_reg_set(pVBInfo->Part4Port,
1711                                               0x0D,
1712                                               *pVBInfo->pCRT2Data_4_D);
1713                                 xgifb_reg_set(pVBInfo->Part4Port,
1714                                               0x0E,
1715                                               *pVBInfo->pCRT2Data_4_E);
1716                                 xgifb_reg_set(pVBInfo->Part4Port,
1717                                               0x10,
1718                                               *pVBInfo->pCRT2Data_4_10);
1719                                 xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
1720                         }
1721
1722                         XGI_LockCRT2(HwDeviceExtension, pVBInfo);
1723                 }
1724         } /* != XG20 */
1725         printk("18");
1726
1727         printk("181");
1728
1729         printk("182");
1730
1731         XGI_SenseCRT1(pVBInfo);
1732
1733         printk("183");
1734         /* XGINew_DetectMonitor(HwDeviceExtension); */
1735         pVBInfo->IF_DEF_CH7007 = 0;
1736         if ((HwDeviceExtension->jChipType == XG21) &&
1737             (pVBInfo->IF_DEF_CH7007)) {
1738                 printk("184");
1739                 /* sense CRT2 */
1740                 XGI_GetSenseStatus(HwDeviceExtension, pVBInfo);
1741                 printk("185");
1742
1743         }
1744         if (HwDeviceExtension->jChipType == XG21) {
1745                 printk("186");
1746
1747                 xgifb_reg_and_or(pVBInfo->P3d4,
1748                                  0x32,
1749                                  ~Monitor1Sense,
1750                                  Monitor1Sense); /* Z9 default has CRT */
1751                 temp = GetXG21FPBits(pVBInfo);
1752                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
1753                 printk("187");
1754
1755         }
1756         if (HwDeviceExtension->jChipType == XG27) {
1757                 xgifb_reg_and_or(pVBInfo->P3d4,
1758                                  0x32,
1759                                  ~Monitor1Sense,
1760                                  Monitor1Sense); /* Z9 default has CRT */
1761                 temp = GetXG27FPBits(pVBInfo);
1762                 xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
1763         }
1764         printk("19");
1765
1766         XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
1767                                                       pVBInfo);
1768
1769         XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
1770                                          pVBInfo->P3d4,
1771                                          pVBInfo);
1772
1773         printk("20");
1774         XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
1775         printk("21");
1776
1777         printk("22");
1778
1779         /* SetDefExt2Regs begin */
1780         /*
1781         AGP = 1;
1782         temp = (unsigned char) xgifb_reg_get(pVBInfo->P3c4, 0x3A);
1783         temp &= 0x30;
1784         if (temp == 0x30)
1785                 AGP = 0;
1786
1787         if (AGP == 0)
1788                 *pVBInfo->pSR21 &= 0xEF;
1789
1790         xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1791         if (AGP == 1)
1792                 *pVBInfo->pSR22 &= 0x20;
1793         xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22);
1794         */
1795         /* base = 0x80000000; */
1796         /* OutPortLong(0xcf8, base); */
1797         /* Temp = (InPortLong(0xcfc) & 0xFFFF); */
1798         /* if (Temp == 0x1039) { */
1799         xgifb_reg_set(pVBInfo->P3c4,
1800                       0x22,
1801                       (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
1802         /* } else { */
1803         /*      xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
1804         /* } */
1805
1806         xgifb_reg_set(pVBInfo->P3c4, 0x21, *pVBInfo->pSR21);
1807
1808         printk("23");
1809
1810         XGINew_ChkSenseStatus(HwDeviceExtension, pVBInfo);
1811         XGINew_SetModeScratch(HwDeviceExtension, pVBInfo);
1812
1813         printk("24");
1814
1815         xgifb_reg_set(pVBInfo->P3d4, 0x8c, 0x87);
1816         xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x31);
1817         printk("25");
1818
1819         return 1;
1820 } /* end of init */