drivers/net/wireless/rtlwifi/rtl8192se/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../regd.h"
  34 #include "../cam.h"
  35 #include "../ps.h"
  36 #include "../pci.h"
  37 #include "reg.h"
  38 #include "def.h"
  39 #include "phy.h"
  40 #include "dm.h"
  41 #include "fw.h"
  42 #include "led.h"
  43 #include "hw.h"
  44
  45 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  46 {
  47         struct rtl_priv *rtlpriv = rtl_priv(hw);
  48         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50
  51         switch (variable) {
  52         case HW_VAR_RCR: {
  53                         *((u32 *) (val)) = rtlpci->receive_config;
  54                         break;
  55                 }
  56         case HW_VAR_RF_STATE: {
  57                         *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
  58                         break;
  59                 }
  60         case HW_VAR_FW_PSMODE_STATUS: {
  61                         *((bool *) (val)) = ppsc->fw_current_inpsmode;
  62                         break;
  63                 }
  64         case HW_VAR_CORRECT_TSF: {
  65                         u64 tsf;
  66                         u32 *ptsf_low = (u32 *)&tsf;
  67                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
  68
  69                         *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
  70                         *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
  71
  72                         *((u64 *) (val)) = tsf;
  73
  74                         break;
  75                 }
  76         case HW_VAR_MRC: {
  77                         *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
  78                         break;
  79                 }
  80         default: {
  81                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
  82                                  ("switch case not process\n"));
  83                         break;
  84                 }
  85         }
  86 }
  87
  88 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  89 {
  90         struct rtl_priv *rtlpriv = rtl_priv(hw);
  91         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  92         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  93         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  94         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  95         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  96
  97         switch (variable) {
  98         case HW_VAR_ETHER_ADDR:{
  99                         rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
 100                         rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
 101                         break;
 102                 }
 103         case HW_VAR_BASIC_RATE:{
 104                         u16 rate_cfg = ((u16 *) val)[0];
 105                         u8 rate_index = 0;
 106
 107                         if (rtlhal->version == VERSION_8192S_ACUT)
 108                                 rate_cfg = rate_cfg & 0x150;
 109                         else
 110                                 rate_cfg = rate_cfg & 0x15f;
 111
 112                         rate_cfg |= 0x01;
 113
 114                         rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
 115                         rtl_write_byte(rtlpriv, RRSR + 1,
 116                                        (rate_cfg >> 8) & 0xff);
 117
 118                         while (rate_cfg > 0x1) {
 119                                 rate_cfg = (rate_cfg >> 1);
 120                                 rate_index++;
 121                         }
 122                         rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
 123
 124                         break;
 125                 }
 126         case HW_VAR_BSSID:{
 127                         rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
 128                         rtl_write_word(rtlpriv, BSSIDR + 4,
 129                                        ((u16 *)(val + 4))[0]);
 130                         break;
 131                 }
 132         case HW_VAR_SIFS:{
 133                         rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
 134                         rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
 135                         break;
 136                 }
 137         case HW_VAR_SLOT_TIME:{
 138                         u8 e_aci;
 139
 140                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 141                                  ("HW_VAR_SLOT_TIME %x\n", val[0]));
 142
 143                         rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
 144
 145                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 146                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 147                                                 HW_VAR_AC_PARAM,
 148                                                 (u8 *)(&e_aci));
 149                         }
 150                         break;
 151                 }
 152         case HW_VAR_ACK_PREAMBLE:{
 153                         u8 reg_tmp;
 154                         u8 short_preamble = (bool) (*(u8 *) val);
 155                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 156                         if (short_preamble)
 157                                 reg_tmp |= 0x80;
 158
 159                         rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
 160                         break;
 161                 }
 162         case HW_VAR_AMPDU_MIN_SPACE:{
 163                         u8 min_spacing_to_set;
 164                         u8 sec_min_space;
 165
 166                         min_spacing_to_set = *((u8 *)val);
 167                         if (min_spacing_to_set <= 7) {
 168                                 if (rtlpriv->sec.pairwise_enc_algorithm ==
 169                                     NO_ENCRYPTION)
 170                                         sec_min_space = 0;
 171                                 else
 172                                         sec_min_space = 1;
 173
 174                                 if (min_spacing_to_set < sec_min_space)
 175                                         min_spacing_to_set = sec_min_space;
 176                                 if (min_spacing_to_set > 5)
 177                                         min_spacing_to_set = 5;
 178
 179                                 mac->min_space_cfg =
 180                                                 ((mac->min_space_cfg & 0xf8) |
 181                                                 min_spacing_to_set);
 182
 183                                 *val = min_spacing_to_set;
 184
 185                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 186                                          ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 187                                           mac->min_space_cfg));
 188
 189                                 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 190                                                mac->min_space_cfg);
 191                         }
 192                         break;
 193                 }
 194         case HW_VAR_SHORTGI_DENSITY:{
 195                         u8 density_to_set;
 196
 197                         density_to_set = *((u8 *) val);
 198                         mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
 199                         mac->min_space_cfg |= (density_to_set << 3);
 200
 201                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 202                                  ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 203                                   mac->min_space_cfg));
 204
 205                         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
 206                                        mac->min_space_cfg);
 207
 208                         break;
 209                 }
 210         case HW_VAR_AMPDU_FACTOR:{
 211                         u8 factor_toset;
 212                         u8 regtoset;
 213                         u8 factorlevel[18] = {
 214                                 2, 4, 4, 7, 7, 13, 13,
 215                                 13, 2, 7, 7, 13, 13,
 216                                 15, 15, 15, 15, 0};
 217                         u8 index = 0;
 218
 219                         factor_toset = *((u8 *) val);
 220                         if (factor_toset <= 3) {
 221                                 factor_toset = (1 << (factor_toset + 2));
 222                                 if (factor_toset > 0xf)
 223                                         factor_toset = 0xf;
 224
 225                                 for (index = 0; index < 17; index++) {
 226                                         if (factorlevel[index] > factor_toset)
 227                                                 factorlevel[index] =
 228                                                                  factor_toset;
 229                                 }
 230
 231                                 for (index = 0; index < 8; index++) {
 232                                         regtoset = ((factorlevel[index * 2]) |
 233                                                     (factorlevel[index *
 234                                                     2 + 1] << 4));
 235                                         rtl_write_byte(rtlpriv,
 236                                                        AGGLEN_LMT_L + index,
 237                                                        regtoset);
 238                                 }
 239
 240                                 regtoset = ((factorlevel[16]) |
 241                                             (factorlevel[17] << 4));
 242                                 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
 243
 244                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 245                                          ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
 246                                           factor_toset));
 247                         }
 248                         break;
 249                 }
 250         case HW_VAR_AC_PARAM:{
 251                         u8 e_aci = *((u8 *) val);
 252                         rtl92s_dm_init_edca_turbo(hw);
 253
 254                         if (rtlpci->acm_method != eAcmWay2_SW)
 255                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 256                                                  HW_VAR_ACM_CTRL,
 257                                                  (u8 *)(&e_aci));
 258                         break;
 259                 }
 260         case HW_VAR_ACM_CTRL:{
 261                         u8 e_aci = *((u8 *) val);
 262                         union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
 263                                                         mac->ac[0].aifs));
 264                         u8 acm = p_aci_aifsn->f.acm;
 265                         u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
 266
 267                         acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
 268                                    0x0 : 0x1);
 269
 270                         if (acm) {
 271                                 switch (e_aci) {
 272                                 case AC0_BE:
 273                                         acm_ctrl |= AcmHw_BeqEn;
 274                                         break;
 275                                 case AC2_VI:
 276                                         acm_ctrl |= AcmHw_ViqEn;
 277                                         break;
 278                                 case AC3_VO:
 279                                         acm_ctrl |= AcmHw_VoqEn;
 280                                         break;
 281                                 default:
 282                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 283                                                  ("HW_VAR_ACM_CTRL acm set "
 284                                                   "failed: eACI is %d\n", acm));
 285                                         break;
 286                                 }
 287                         } else {
 288                                 switch (e_aci) {
 289                                 case AC0_BE:
 290                                         acm_ctrl &= (~AcmHw_BeqEn);
 291                                         break;
 292                                 case AC2_VI:
 293                                         acm_ctrl &= (~AcmHw_ViqEn);
 294                                         break;
 295                                 case AC3_VO:
 296                                         acm_ctrl &= (~AcmHw_BeqEn);
 297                                         break;
 298                                 default:
 299                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 300                                                  ("switch case not process\n"));
 301                                         break;
 302                                 }
 303                         }
 304
 305                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 306                                  ("HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl));
 307                         rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
 308                         break;
 309                 }
 310         case HW_VAR_RCR:{
 311                         rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
 312                         rtlpci->receive_config = ((u32 *) (val))[0];
 313                         break;
 314                 }
 315         case HW_VAR_RETRY_LIMIT:{
 316                         u8 retry_limit = ((u8 *) (val))[0];
 317
 318                         rtl_write_word(rtlpriv, RETRY_LIMIT,
 319                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 320                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 321                         break;
 322                 }
 323         case HW_VAR_DUAL_TSF_RST: {
 324                         break;
 325                 }
 326         case HW_VAR_EFUSE_BYTES: {
 327                         rtlefuse->efuse_usedbytes = *((u16 *) val);
 328                         break;
 329                 }
 330         case HW_VAR_EFUSE_USAGE: {
 331                         rtlefuse->efuse_usedpercentage = *((u8 *) val);
 332                         break;
 333                 }
 334         case HW_VAR_IO_CMD: {
 335                         break;
 336                 }
 337         case HW_VAR_WPA_CONFIG: {
 338                         rtl_write_byte(rtlpriv, REG_SECR, *((u8 *) val));
 339                         break;
 340                 }
 341         case HW_VAR_SET_RPWM:{
 342                         break;
 343                 }
 344         case HW_VAR_H2C_FW_PWRMODE:{
 345                         break;
 346                 }
 347         case HW_VAR_FW_PSMODE_STATUS: {
 348                         ppsc->fw_current_inpsmode = *((bool *) val);
 349                         break;
 350                 }
 351         case HW_VAR_H2C_FW_JOINBSSRPT:{
 352                         break;
 353                 }
 354         case HW_VAR_AID:{
 355                         break;
 356                 }
 357         case HW_VAR_CORRECT_TSF:{
 358                         break;
 359                 }
 360         case HW_VAR_MRC: {
 361                         bool bmrc_toset = *((bool *)val);
 362                         u8 u1bdata = 0;
 363
 364                         if (bmrc_toset) {
 365                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 366                                               MASKBYTE0, 0x33);
 367                                 u1bdata = (u8)rtl_get_bbreg(hw,
 368                                                 ROFDM1_TRXPATHENABLE,
 369                                                 MASKBYTE0);
 370                                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 371                                               MASKBYTE0,
 372                                               ((u1bdata & 0xf0) | 0x03));
 373                                 u1bdata = (u8)rtl_get_bbreg(hw,
 374                                                 ROFDM0_TRXPATHENABLE,
 375                                                 MASKBYTE1);
 376                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 377                                               MASKBYTE1,
 378                                               (u1bdata | 0x04));
 379
 380                                 /* Update current settings. */
 381                                 rtlpriv->dm.current_mrc_switch = bmrc_toset;
 382                         } else {
 383                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 384                                               MASKBYTE0, 0x13);
 385                                 u1bdata = (u8)rtl_get_bbreg(hw,
 386                                                  ROFDM1_TRXPATHENABLE,
 387                                                  MASKBYTE0);
 388                                 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
 389                                               MASKBYTE0,
 390                                               ((u1bdata & 0xf0) | 0x01));
 391                                 u1bdata = (u8)rtl_get_bbreg(hw,
 392                                                 ROFDM0_TRXPATHENABLE,
 393                                                 MASKBYTE1);
 394                                 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
 395                                               MASKBYTE1, (u1bdata & 0xfb));
 396
 397                                 /* Update current settings. */
 398                                 rtlpriv->dm.current_mrc_switch = bmrc_toset;
 399                         }
 400
 401                         break;
 402                 }
 403         default:
 404                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 405                          ("switch case not process\n"));
 406                 break;
 407         }
 408
 409 }
 410
 411 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
 412 {
 413         struct rtl_priv *rtlpriv = rtl_priv(hw);
 414         u8 sec_reg_value = 0x0;
 415
 416         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("PairwiseEncAlgorithm = %d "
 417                  "GroupEncAlgorithm = %d\n",
 418                  rtlpriv->sec.pairwise_enc_algorithm,
 419                  rtlpriv->sec.group_enc_algorithm));
 420
 421         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 422                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 423                          ("not open hw encryption\n"));
 424                 return;
 425         }
 426
 427         sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
 428
 429         if (rtlpriv->sec.use_defaultkey) {
 430                 sec_reg_value |= SCR_TXUSEDK;
 431                 sec_reg_value |= SCR_RXUSEDK;
 432         }
 433
 434         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, ("The SECR-value %x\n",
 435                         sec_reg_value));
 436
 437         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 438
 439 }
 440
 441 static u8 _rtl92ce_halset_sysclk(struct ieee80211_hw *hw, u8 data)
 442 {
 443         struct rtl_priv *rtlpriv = rtl_priv(hw);
 444         u8 waitcount = 100;
 445         bool bresult = false;
 446         u8 tmpvalue;
 447
 448         rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
 449
 450         /* Wait the MAC synchronized. */
 451         udelay(400);
 452
 453         /* Check if it is set ready. */
 454         tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 455         bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
 456
 457         if ((data & (BIT(6) | BIT(7))) == false) {
 458                 waitcount = 100;
 459                 tmpvalue = 0;
 460
 461                 while (1) {
 462                         waitcount--;
 463
 464                         tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
 465                         if ((tmpvalue & BIT(6)))
 466                                 break;
 467
 468                         printk(KERN_ERR "wait for BIT(6) return value %x\n",
 469                                tmpvalue);
 470                         if (waitcount == 0)
 471                                 break;
 472
 473                         udelay(10);
 474                 }
 475
 476                 if (waitcount == 0)
 477                         bresult = false;
 478                 else
 479                         bresult = true;
 480         }
 481
 482         return bresult;
 483 }
 484
 485 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
 486 {
 487         struct rtl_priv *rtlpriv = rtl_priv(hw);
 488         u8 u1tmp;
 489
 490         /* The following config GPIO function */
 491         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 492         u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 493
 494         /* config GPIO3 to input */
 495         u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 496         rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 497
 498 }
 499
 500 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
 501 {
 502         struct rtl_priv *rtlpriv = rtl_priv(hw);
 503         u8 u1tmp;
 504         u8 retval = ERFON;
 505
 506         /* The following config GPIO function */
 507         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
 508         u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
 509
 510         /* config GPIO3 to input */
 511         u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
 512         rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
 513
 514         /* On some of the platform, driver cannot read correct
 515          * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
 516         mdelay(10);
 517
 518         /* check GPIO3 */
 519         u1tmp = rtl_read_byte(rtlpriv, GPIO_IN);
 520         retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
 521
 522         return retval;
 523 }
 524
 525 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
 526 {
 527         struct rtl_priv *rtlpriv = rtl_priv(hw);
 528         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 529         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 530
 531         u8 i;
 532         u8 tmpu1b;
 533         u16 tmpu2b;
 534         u8 pollingcnt = 20;
 535
 536         if (rtlpci->first_init) {
 537                 /* Reset PCIE Digital */
 538                 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 539                 tmpu1b &= 0xFE;
 540                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 541                 udelay(1);
 542                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
 543         }
 544
 545         /* Switch to SW IO control */
 546         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 547         if (tmpu1b & BIT(7)) {
 548                 tmpu1b &= ~(BIT(6) | BIT(7));
 549
 550                 /* Set failed, return to prevent hang. */
 551                 if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
 552                         return;
 553         }
 554
 555         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
 556         udelay(50);
 557         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
 558         udelay(50);
 559
 560         /* Clear FW RPWM for FW control LPS.*/
 561         rtl_write_byte(rtlpriv, RPWM, 0x0);
 562
 563         /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
 564         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 565         tmpu1b &= 0x73;
 566         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
 567         /* wait for BIT 10/11/15 to pull high automatically!! */
 568         mdelay(1);
 569
 570         rtl_write_byte(rtlpriv, CMDR, 0);
 571         rtl_write_byte(rtlpriv, TCR, 0);
 572
 573         /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
 574         tmpu1b = rtl_read_byte(rtlpriv, 0x562);
 575         tmpu1b |= 0x08;
 576         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 577         tmpu1b &= ~(BIT(3));
 578         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
 579
 580         /* Enable AFE clock source */
 581         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
 582         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
 583         /* Delay 1.5ms */
 584         mdelay(2);
 585         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
 586         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
 587
 588         /* Enable AFE Macro Block's Bandgap */
 589         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 590         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
 591         mdelay(1);
 592
 593         /* Enable AFE Mbias */
 594         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
 595         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
 596         mdelay(1);
 597
 598         /* Enable LDOA15 block  */
 599         tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
 600         rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
 601
 602         /* Set Digital Vdd to Retention isolation Path. */
 603         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 604         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
 605
 606         /* For warm reboot NIC disappera bug. */
 607         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 608         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
 609
 610         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
 611
 612         /* Enable AFE PLL Macro Block */
 613         /* We need to delay 100u before enabling PLL. */
 614         udelay(200);
 615         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
 616         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 617
 618         /* for divider reset  */
 619         udelay(100);
 620         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
 621                        BIT(4) | BIT(6)));
 622         udelay(10);
 623         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
 624         udelay(10);
 625
 626         /* Enable MAC 80MHZ clock  */
 627         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
 628         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
 629         mdelay(1);
 630
 631         /* Release isolation AFE PLL & MD */
 632         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
 633
 634         /* Enable MAC clock */
 635         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 636         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
 637
 638         /* Enable Core digital and enable IOREG R/W */
 639         tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
 640         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
 641
 642         tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
 643         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
 644
 645         /* enable REG_EN */
 646         rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
 647
 648         /* Switch the control path. */
 649         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
 650         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
 651
 652         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
 653         tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
 654         if (!_rtl92ce_halset_sysclk(hw, tmpu1b))
 655                 return; /* Set failed, return to prevent hang. */
 656
 657         rtl_write_word(rtlpriv, CMDR, 0x07FC);
 658
 659         /* MH We must enable the section of code to prevent load IMEM fail. */
 660         /* Load MAC register from WMAc temporarily We simulate macreg. */
 661         /* txt HW will provide MAC txt later  */
 662         rtl_write_byte(rtlpriv, 0x6, 0x30);
 663         rtl_write_byte(rtlpriv, 0x49, 0xf0);
 664
 665         rtl_write_byte(rtlpriv, 0x4b, 0x81);
 666
 667         rtl_write_byte(rtlpriv, 0xb5, 0x21);
 668
 669         rtl_write_byte(rtlpriv, 0xdc, 0xff);
 670         rtl_write_byte(rtlpriv, 0xdd, 0xff);
 671         rtl_write_byte(rtlpriv, 0xde, 0xff);
 672         rtl_write_byte(rtlpriv, 0xdf, 0xff);
 673
 674         rtl_write_byte(rtlpriv, 0x11a, 0x00);
 675         rtl_write_byte(rtlpriv, 0x11b, 0x00);
 676
 677         for (i = 0; i < 32; i++)
 678                 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
 679
 680         rtl_write_byte(rtlpriv, 0x236, 0xff);
 681
 682         rtl_write_byte(rtlpriv, 0x503, 0x22);
 683
 684         if (ppsc->support_aspm && !ppsc->support_backdoor)
 685                 rtl_write_byte(rtlpriv, 0x560, 0x40);
 686         else
 687                 rtl_write_byte(rtlpriv, 0x560, 0x00);
 688
 689         rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
 690
 691         /* Set RX Desc Address */
 692         rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
 693         rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
 694
 695         /* Set TX Desc Address */
 696         rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
 697         rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
 698         rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
 699         rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
 700         rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
 701         rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
 702         rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
 703         rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
 704         rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
 705
 706         rtl_write_word(rtlpriv, CMDR, 0x37FC);
 707
 708         /* To make sure that TxDMA can ready to download FW. */
 709         /* We should reset TxDMA if IMEM RPT was not ready. */
 710         do {
 711                 tmpu1b = rtl_read_byte(rtlpriv, TCR);
 712                 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
 713                         break;
 714
 715                 udelay(5);
 716         } while (pollingcnt--);
 717
 718         if (pollingcnt <= 0) {
 719                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 720                          ("Polling TXDMA_INIT_VALUE "
 721                          "timeout!! Current TCR(%#x)\n", tmpu1b));
 722                 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
 723                 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
 724                 udelay(2);
 725                 /* Reset TxDMA */
 726                 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
 727         }
 728
 729         /* After MACIO reset,we must refresh LED state. */
 730         if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
 731            (ppsc->rfoff_reason == 0)) {
 732                 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 733                 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 734                 enum rf_pwrstate rfpwr_state_toset;
 735                 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
 736
 737                 if (rfpwr_state_toset == ERFON)
 738                         rtl92se_sw_led_on(hw, pLed0);
 739         }
 740 }
 741
 742 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
 743 {
 744         struct rtl_priv *rtlpriv = rtl_priv(hw);
 745         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 746         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 747         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 748         u8 i;
 749         u16 tmpu2b;
 750
 751         /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
 752
 753         /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
 754         /* Turn on 0x40 Command register */
 755         rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
 756                         SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
 757                         RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
 758
 759         /* Set TCR TX DMA pre 2 FULL enable bit */
 760         rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
 761                         TXDMAPRE2FULL);
 762
 763         /* Set RCR      */
 764         rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
 765
 766         /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
 767
 768         /* 4. Timing Control Register  (Offset: 0x0080 - 0x009F) */
 769         /* Set CCK/OFDM SIFS */
 770         /* CCK SIFS shall always be 10us. */
 771         rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
 772         rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
 773
 774         /* Set AckTimeout */
 775         rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
 776
 777         /* Beacon related */
 778         rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
 779         rtl_write_word(rtlpriv, ATIMWND, 2);
 780
 781         /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
 782         /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
 783         /* Firmware allocate now, associate with FW internal setting.!!! */
 784
 785         /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
 786         /* 5.3 Set driver info, we only accept PHY status now. */
 787         /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO  */
 788         rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
 789
 790         /* 6. Adaptive Control Register  (Offset: 0x0160 - 0x01CF) */
 791         /* Set RRSR to all legacy rate and HT rate
 792          * CCK rate is supported by default.
 793          * CCK rate will be filtered out only when associated
 794          * AP does not support it.
 795          * Only enable ACK rate to OFDM 24M
 796          * Disable RRSR for CCK rate in A-Cut   */
 797
 798         if (rtlhal->version == VERSION_8192S_ACUT)
 799                 rtl_write_byte(rtlpriv, RRSR, 0xf0);
 800         else if (rtlhal->version == VERSION_8192S_BCUT)
 801                 rtl_write_byte(rtlpriv, RRSR, 0xff);
 802         rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
 803         rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
 804
 805         /* A-Cut IC do not support CCK rate. We forbid ARFR to */
 806         /* fallback to CCK rate */
 807         for (i = 0; i < 8; i++) {
 808                 /*Disable RRSR for CCK rate in A-Cut */
 809                 if (rtlhal->version == VERSION_8192S_ACUT)
 810                         rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
 811         }
 812
 813         /* Different rate use different AMPDU size */
 814         /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
 815         rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
 816         /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
 817         rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
 818         /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
 819         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
 820         /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
 821         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
 822         /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
 823         rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
 824
 825         /* Set Data / Response auto rate fallack retry count */
 826         rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
 827         rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
 828         rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
 829         rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
 830
 831         /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
 832         /* Set all rate to support SG */
 833         rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
 834
 835         /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
 836         /* Set NAV protection length */
 837         rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
 838         /* CF-END Threshold */
 839         rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
 840         /* Set AMPDU minimum space */
 841         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
 842         /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
 843         rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
 844
 845         /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
 846         /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
 847         /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
 848         /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
 849         /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
 850
 851         /* 14. Set driver info, we only accept PHY status now. */
 852         rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
 853
 854         /* 15. For EEPROM R/W Workaround */
 855         /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
 856         tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
 857         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
 858         tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 859         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
 860
 861         /* 17. For EFUSE */
 862         /* We may R/W EFUSE in EEPROM mode */
 863         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
 864                 u8      tempval;
 865
 866                 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
 867                 tempval &= 0xFE;
 868                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
 869
 870                 /* Change Program timing */
 871                 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
 872                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("EFUSE CONFIG OK\n"));
 873         }
 874
 875         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("OK\n"));
 876
 877 }
 878
 879 static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
 880 {
 881         struct rtl_priv *rtlpriv = rtl_priv(hw);
 882         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 883         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 884         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 885
 886         u8 reg_bw_opmode = 0;
 887         u32 reg_rrsr = 0;
 888         u8 regtmp = 0;
 889
 890         reg_bw_opmode = BW_OPMODE_20MHZ;
 891         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 892
 893         regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
 894         reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
 895         rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
 896         rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
 897
 898         /* Set Retry Limit here */
 899         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
 900                         (u8 *)(&rtlpci->shortretry_limit));
 901
 902         rtl_write_byte(rtlpriv, MLT, 0x8f);
 903
 904         /* For Min Spacing configuration. */
 905         switch (rtlphy->rf_type) {
 906         case RF_1T2R:
 907         case RF_1T1R:
 908                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
 909                 break;
 910         case RF_2T2R:
 911         case RF_2T2R_GREEN:
 912                 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
 913                 break;
 914         }
 915         rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
 916 }
 917
 918 int rtl92se_hw_init(struct ieee80211_hw *hw)
 919 {
 920         struct rtl_priv *rtlpriv = rtl_priv(hw);
 921         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 922         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 923         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 924         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 925         u8 tmp_byte = 0;
 926
 927         bool rtstatus = true;
 928         u8 tmp_u1b;
 929         int err = false;
 930         u8 i;
 931         int wdcapra_add[] = {
 932                 EDCAPARA_BE, EDCAPARA_BK,
 933                 EDCAPARA_VI, EDCAPARA_VO};
 934         u8 secr_value = 0x0;
 935
 936         rtlpci->being_init_adapter = true;
 937
 938         rtlpriv->intf_ops->disable_aspm(hw);
 939
 940         /* 1. MAC Initialize */
 941         /* Before FW download, we have to set some MAC register */
 942         _rtl92se_macconfig_before_fwdownload(hw);
 943
 944         rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
 945                         PMC_FSM) >> 16) & 0xF);
 946
 947         rtl8192se_gpiobit3_cfg_inputmode(hw);
 948
 949         /* 2. download firmware */
 950         rtstatus = rtl92s_download_fw(hw);
 951         if (!rtstatus) {
 952                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 953                          ("Failed to download FW. "
 954                          "Init HW without FW now.., Please copy FW into"
 955                          "/lib/firmware/rtlwifi\n"));
 956                 rtlhal->fw_ready = false;
 957         } else {
 958                 rtlhal->fw_ready = true;
 959         }
 960
 961         /* After FW download, we have to reset MAC register */
 962         _rtl92se_macconfig_after_fwdownload(hw);
 963
 964         /*Retrieve default FW Cmd IO map. */
 965         rtlhal->fwcmd_iomap =   rtl_read_word(rtlpriv, LBUS_MON_ADDR);
 966         rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
 967
 968         /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
 969         if (rtl92s_phy_mac_config(hw) != true) {
 970                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("MAC Config failed\n"));
 971                 return rtstatus;
 972         }
 973
 974         /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
 975         /* We must set flag avoid BB/RF config period later!! */
 976         rtl_write_dword(rtlpriv, CMDR, 0x37FC);
 977
 978         /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
 979         if (rtl92s_phy_bb_config(hw) != true) {
 980                 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, ("BB Config failed\n"));
 981                 return rtstatus;
 982         }
 983
 984         /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
 985         /* Before initalizing RF. We can not use FW to do RF-R/W. */
 986
 987         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 988
 989         /* RF Power Save */
 990 #if 0
 991         /* H/W or S/W RF OFF before sleep. */
 992         if (rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS) {
 993                 u32 rfoffreason = rtlpriv->psc.rfoff_reason;
 994
 995                 rtlpriv->psc.rfoff_reason = RF_CHANGE_BY_INIT;
 996                 rtlpriv->psc.rfpwr_state = ERFON;
 997                 rtl_ps_set_rf_state(hw, ERFOFF, rfoffreason, true);
 998         } else {
 999                 /* gpio radio on/off is out of adapter start */
1000                 if (rtlpriv->psc.hwradiooff == false) {
1001                         rtlpriv->psc.rfpwr_state = ERFON;
1002                         rtlpriv->psc.rfoff_reason = 0;
1003                 }
1004         }
1005 #endif
1006
1007         /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1008         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1009         if (rtlhal->version == VERSION_8192S_ACUT)
1010                 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1011         else
1012                 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1013
1014         if (rtl92s_phy_rf_config(hw) != true) {
1015                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("RF Config failed\n"));
1016                 return rtstatus;
1017         }
1018
1019         /* After read predefined TXT, we must set BB/MAC/RF
1020          * register as our requirement */
1021
1022         rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1023                                                            (enum radio_path)0,
1024                                                            RF_CHNLBW,
1025                                                            RFREG_OFFSET_MASK);
1026         rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1027                                                            (enum radio_path)1,
1028                                                            RF_CHNLBW,
1029                                                            RFREG_OFFSET_MASK);
1030
1031         /*---- Set CCK and OFDM Block "ON"----*/
1032         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1033         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1034
1035         /*3 Set Hardware(Do nothing now) */
1036         _rtl92se_hw_configure(hw);
1037
1038         /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1039         /* TX power index for different rate set. */
1040         /* Get original hw reg values */
1041         rtl92s_phy_get_hw_reg_originalvalue(hw);
1042         /* Write correct tx power index */
1043         rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1044
1045         /* We must set MAC address after firmware download. */
1046         for (i = 0; i < 6; i++)
1047                 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1048
1049         /* EEPROM R/W workaround */
1050         tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1051         rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1052
1053         rtl_write_byte(rtlpriv, 0x4d, 0x0);
1054
1055         if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1056                 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1057                 tmp_byte = tmp_byte | BIT(5);
1058                 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1059                 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1060         }
1061
1062         /* We enable high power and RA related mechanism after NIC
1063          * initialized. */
1064         rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1065
1066         /* Add to prevent ASPM bug. */
1067         /* Always enable hst and NIC clock request. */
1068         rtl92s_phy_switch_ephy_parameter(hw);
1069
1070         /* Security related
1071          * 1. Clear all H/W keys.
1072          * 2. Enable H/W encryption/decryption. */
1073         rtl_cam_reset_all_entry(hw);
1074         secr_value |= SCR_TXENCENABLE;
1075         secr_value |= SCR_RXENCENABLE;
1076         secr_value |= SCR_NOSKMC;
1077         rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1078
1079         for (i = 0; i < 4; i++)
1080                 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1081
1082         if (rtlphy->rf_type == RF_1T2R) {
1083                 bool mrc2set = true;
1084                 /* Turn on B-Path */
1085                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1086         }
1087
1088         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1089         rtl92s_dm_init(hw);
1090         rtlpci->being_init_adapter = false;
1091
1092         return err;
1093 }
1094
1095 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 * addr)
1096 {
1097 }
1098
1099 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1100 {
1101         struct rtl_priv *rtlpriv = rtl_priv(hw);
1102         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1103         u32 reg_rcr = rtlpci->receive_config;
1104
1105         if (rtlpriv->psc.rfpwr_state != ERFON)
1106                 return;
1107
1108         if (check_bssid == true) {
1109                 reg_rcr |= (RCR_CBSSID);
1110                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1111         } else if (check_bssid == false) {
1112                 reg_rcr &= (~RCR_CBSSID);
1113                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1114         }
1115
1116 }
1117
1118 static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1119                                      enum nl80211_iftype type)
1120 {
1121         struct rtl_priv *rtlpriv = rtl_priv(hw);
1122         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1123         u32 temp;
1124         bt_msr &= ~MSR_LINK_MASK;
1125
1126         switch (type) {
1127         case NL80211_IFTYPE_UNSPECIFIED:
1128                 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1129                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1130                          ("Set Network type to NO LINK!\n"));
1131                 break;
1132         case NL80211_IFTYPE_ADHOC:
1133                 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1134                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1135                          ("Set Network type to Ad Hoc!\n"));
1136                 break;
1137         case NL80211_IFTYPE_STATION:
1138                 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1139                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1140                          ("Set Network type to STA!\n"));
1141                 break;
1142         case NL80211_IFTYPE_AP:
1143                 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1144                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1145                          ("Set Network type to AP!\n"));
1146                 break;
1147         default:
1148                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1149                          ("Network type %d not support!\n", type));
1150                 return 1;
1151                 break;
1152
1153         }
1154
1155         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1156
1157         temp = rtl_read_dword(rtlpriv, TCR);
1158         rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1159         rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1160
1161
1162         return 0;
1163 }
1164
1165 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1166 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1167 {
1168         struct rtl_priv *rtlpriv = rtl_priv(hw);
1169
1170         if (_rtl92se_set_media_status(hw, type))
1171                 return -EOPNOTSUPP;
1172
1173         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1174                 if (type != NL80211_IFTYPE_AP)
1175                         rtl92se_set_check_bssid(hw, true);
1176         } else {
1177                 rtl92se_set_check_bssid(hw, false);
1178         }
1179
1180         return 0;
1181 }
1182
1183 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1184 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1185 {
1186         struct rtl_priv *rtlpriv = rtl_priv(hw);
1187         rtl92s_dm_init_edca_turbo(hw);
1188
1189         switch (aci) {
1190         case AC1_BK:
1191                 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1192                 break;
1193         case AC0_BE:
1194                 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1195                 break;
1196         case AC2_VI:
1197                 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1198                 break;
1199         case AC3_VO:
1200                 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1201                 break;
1202         default:
1203                 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1204                 break;
1205         }
1206 }
1207
1208 void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1209 {
1210         struct rtl_priv *rtlpriv = rtl_priv(hw);
1211         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1212
1213         rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1214         /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1215         rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1216
1217         rtlpci->irq_enabled = true;
1218 }
1219
1220 void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1221 {
1222         struct rtl_priv *rtlpriv = rtl_priv(hw);
1223         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1224
1225         rtl_write_dword(rtlpriv, INTA_MASK, 0);
1226         rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1227
1228         rtlpci->irq_enabled = false;
1229         synchronize_irq(rtlpci->pdev->irq);
1230 }
1231
1232
1233 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1234 {
1235         struct rtl_priv *rtlpriv = rtl_priv(hw);
1236         u8 waitcnt = 100;
1237         bool result = false;
1238         u8 tmp;
1239
1240         rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1241
1242         /* Wait the MAC synchronized. */
1243         udelay(400);
1244
1245         /* Check if it is set ready. */
1246         tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1247         result = ((tmp & BIT(7)) == (data & BIT(7)));
1248
1249         if ((data & (BIT(6) | BIT(7))) == false) {
1250                 waitcnt = 100;
1251                 tmp = 0;
1252
1253                 while (1) {
1254                         waitcnt--;
1255                         tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1256
1257                         if ((tmp & BIT(6)))
1258                                 break;
1259
1260                         printk(KERN_ERR "wait for BIT(6) return value %x\n",
1261                                tmp);
1262
1263                         if (waitcnt == 0)
1264                                 break;
1265                         udelay(10);
1266                 }
1267
1268                 if (waitcnt == 0)
1269                         result = false;
1270                 else
1271                         result = true;
1272         }
1273
1274         return result;
1275 }
1276
1277 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1278 {
1279         struct rtl_priv *rtlpriv = rtl_priv(hw);
1280         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1281         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1282         u8 u1btmp;
1283
1284         if (rtlhal->driver_going2unload)
1285                 rtl_write_byte(rtlpriv, 0x560, 0x0);
1286
1287         /* Power save for BB/RF */
1288         u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1289         u1btmp |= BIT(0);
1290         rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1291         rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1292         rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1293         rtl_write_word(rtlpriv, CMDR, 0x57FC);
1294         udelay(100);
1295         rtl_write_word(rtlpriv, CMDR, 0x77FC);
1296         rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1297         udelay(10);
1298         rtl_write_word(rtlpriv, CMDR, 0x37FC);
1299         udelay(10);
1300         rtl_write_word(rtlpriv, CMDR, 0x77FC);
1301         udelay(10);
1302         rtl_write_word(rtlpriv, CMDR, 0x57FC);
1303         rtl_write_word(rtlpriv, CMDR, 0x0000);
1304
1305         if (rtlhal->driver_going2unload) {
1306                 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1307                 u1btmp &= ~(BIT(0));
1308                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1309         }
1310
1311         u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1312
1313         /* Add description. After switch control path. register
1314          * after page1 will be invisible. We can not do any IO
1315          * for register>0x40. After resume&MACIO reset, we need
1316          * to remember previous reg content. */
1317         if (u1btmp & BIT(7)) {
1318                 u1btmp &= ~(BIT(6) | BIT(7));
1319                 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1320                         printk(KERN_ERR "Switch ctrl path fail\n");
1321                         return;
1322                 }
1323         }
1324
1325         /* Power save for MAC */
1326         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS  &&
1327                 !rtlhal->driver_going2unload) {
1328                 /* enable LED function */
1329                 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1330         /* SW/HW radio off or halt adapter!! For example S3/S4 */
1331         } else {
1332                 /* LED function disable. Power range is about 8mA now. */
1333                 /* if write 0xF1 disconnet_pci power
1334                  *       ifconfig wlan0 down power are both high 35:70 */
1335                 /* if write oxF9 disconnet_pci power
1336                  * ifconfig wlan0 down power are both low  12:45*/
1337                 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1338         }
1339
1340         rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1341         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1342         rtl_write_byte(rtlpriv,  AFE_PLL_CTRL, 0x00);
1343         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1344         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1345         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1346
1347 }
1348
1349 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1350 {
1351         struct rtl_priv *rtlpriv = rtl_priv(hw);
1352         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1353         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1354         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1355
1356         if (rtlpci->up_first_time == 1)
1357                 return;
1358
1359         if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1360                 rtl92se_sw_led_on(hw, pLed0);
1361         else
1362                 rtl92se_sw_led_off(hw, pLed0);
1363 }
1364
1365
1366 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1367 {
1368         struct rtl_priv *rtlpriv = rtl_priv(hw);
1369         u16 tmpu2b;
1370         u8 tmpu1b;
1371
1372         rtlpriv->psc.pwrdomain_protect = true;
1373
1374         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1375         if (tmpu1b & BIT(7)) {
1376                 tmpu1b &= ~(BIT(6) | BIT(7));
1377                 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1378                         rtlpriv->psc.pwrdomain_protect = false;
1379                         return;
1380                 }
1381         }
1382
1383         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1384         rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1385
1386         /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1387         tmpu1b = rtl_read_byte(rtlpriv, SYS_FUNC_EN + 1);
1388
1389         /* If IPS we need to turn LED on. So we not
1390          * not disable BIT 3/7 of reg3. */
1391         if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1392                 tmpu1b &= 0xFB;
1393         else
1394                 tmpu1b &= 0x73;
1395
1396         rtl_write_byte(rtlpriv, SYS_FUNC_EN + 1, tmpu1b);
1397         /* wait for BIT 10/11/15 to pull high automatically!! */
1398         mdelay(1);
1399
1400         rtl_write_byte(rtlpriv, CMDR, 0);
1401         rtl_write_byte(rtlpriv, TCR, 0);
1402
1403         /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1404         tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1405         tmpu1b |= 0x08;
1406         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1407         tmpu1b &= ~(BIT(3));
1408         rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1409
1410         /* Enable AFE clock source */
1411         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1412         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1413         /* Delay 1.5ms */
1414         udelay(1500);
1415         tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1416         rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1417
1418         /* Enable AFE Macro Block's Bandgap */
1419         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1420         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1421         mdelay(1);
1422
1423         /* Enable AFE Mbias */
1424         tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1425         rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1426         mdelay(1);
1427
1428         /* Enable LDOA15 block */
1429         tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1430         rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1431
1432         /* Set Digital Vdd to Retention isolation Path. */
1433         tmpu2b = rtl_read_word(rtlpriv, SYS_ISO_CTRL);
1434         rtl_write_word(rtlpriv, SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1435
1436
1437         /* For warm reboot NIC disappera bug. */
1438         tmpu2b = rtl_read_word(rtlpriv, SYS_FUNC_EN);
1439         rtl_write_word(rtlpriv, SYS_FUNC_EN, (tmpu2b | BIT(13)));
1440
1441         rtl_write_byte(rtlpriv, SYS_ISO_CTRL + 1, 0x68);
1442
1443         /* Enable AFE PLL Macro Block */
1444         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1445         rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1446         /* Enable MAC 80MHZ clock */
1447         tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1448         rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1449         mdelay(1);
1450
1451         /* Release isolation AFE PLL & MD */
1452         rtl_write_byte(rtlpriv, SYS_ISO_CTRL, 0xA6);
1453
1454         /* Enable MAC clock */
1455         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1456         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1457
1458         /* Enable Core digital and enable IOREG R/W */
1459         tmpu2b = rtl_read_word(rtlpriv, SYS_FUNC_EN);
1460         rtl_write_word(rtlpriv, SYS_FUNC_EN, (tmpu2b | BIT(11)));
1461         /* enable REG_EN */
1462         rtl_write_word(rtlpriv, SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1463
1464         /* Switch the control path. */
1465         tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1466         rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1467
1468         tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1469         tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1470         if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1471                 rtlpriv->psc.pwrdomain_protect = false;
1472                 return;
1473         }
1474
1475         rtl_write_word(rtlpriv, CMDR, 0x37FC);
1476
1477         /* After MACIO reset,we must refresh LED state. */
1478         _rtl92se_gen_refreshledstate(hw);
1479
1480         rtlpriv->psc.pwrdomain_protect = false;
1481 }
1482
1483 void rtl92se_card_disable(struct ieee80211_hw *hw)
1484 {
1485         struct rtl_priv *rtlpriv = rtl_priv(hw);
1486         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1487         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1488         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1489         enum nl80211_iftype opmode;
1490         u8 wait = 30;
1491
1492         rtlpriv->intf_ops->enable_aspm(hw);
1493
1494         if (rtlpci->driver_is_goingto_unload ||
1495                 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1496                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1497
1498         /* we should chnge GPIO to input mode
1499          * this will drop away current about 25mA*/
1500         rtl8192se_gpiobit3_cfg_inputmode(hw);
1501
1502         /* this is very important for ips power save */
1503         while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1504                 if (rtlpriv->psc.pwrdomain_protect)
1505                         mdelay(20);
1506                 else
1507                         break;
1508         }
1509
1510         mac->link_state = MAC80211_NOLINK;
1511         opmode = NL80211_IFTYPE_UNSPECIFIED;
1512         _rtl92se_set_media_status(hw, opmode);
1513
1514         _rtl92s_phy_set_rfhalt(hw);
1515         udelay(100);
1516 }
1517
1518 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1519                              u32 *p_intb)
1520 {
1521         struct rtl_priv *rtlpriv = rtl_priv(hw);
1522         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1523
1524         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1525         rtl_write_dword(rtlpriv, ISR, *p_inta);
1526
1527         *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1528         rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1529 }
1530
1531 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1532 {
1533         struct rtl_priv *rtlpriv = rtl_priv(hw);
1534         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1535         u16 bcntime_cfg = 0;
1536         u16 bcn_cw = 6, bcn_ifs = 0xf;
1537         u16 atim_window = 2;
1538
1539         /* ATIM Window (in unit of TU). */
1540         rtl_write_word(rtlpriv, ATIMWND, atim_window);
1541
1542         /* Beacon interval (in unit of TU). */
1543         rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1544
1545         /* DrvErlyInt (in unit of TU). (Time to send
1546          * interrupt to notify driver to change
1547          * beacon content) */
1548         rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1549
1550         /* BcnDMATIM(in unit of us). Indicates the
1551          * time before TBTT to perform beacon queue DMA  */
1552         rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1553
1554         /* Force beacon frame transmission even
1555          * after receiving beacon frame from
1556          * other ad hoc STA */
1557         rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1558
1559         /* Beacon Time Configuration */
1560         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1561                 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1562
1563         /* TODO: bcn_ifs may required to be changed on ASIC */
1564         bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1565
1566         /*for beacon changed */
1567         rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1568 }
1569
1570 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1571 {
1572         struct rtl_priv *rtlpriv = rtl_priv(hw);
1573         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1574         u16 bcn_interval = mac->beacon_interval;
1575
1576         /* Beacon interval (in unit of TU). */
1577         rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1578         /* 2008.10.24 added by tynli for beacon changed. */
1579         rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1580 }
1581
1582 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1583                 u32 add_msr, u32 rm_msr)
1584 {
1585         struct rtl_priv *rtlpriv = rtl_priv(hw);
1586         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1587
1588         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1589                  ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1590
1591         if (add_msr)
1592                 rtlpci->irq_mask[0] |= add_msr;
1593
1594         if (rm_msr)
1595                 rtlpci->irq_mask[0] &= (~rm_msr);
1596
1597         rtl92se_disable_interrupt(hw);
1598         rtl92se_enable_interrupt(hw);
1599 }
1600
1601 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1602 {
1603         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1604         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1605         u8 efuse_id;
1606
1607         rtlhal->ic_class = IC_INFERIORITY_A;
1608
1609         /* Only retrieving while using EFUSE. */
1610         if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1611                 !rtlefuse->autoload_failflag) {
1612                 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1613
1614                 if (efuse_id == 0xfe)
1615                         rtlhal->ic_class = IC_INFERIORITY_B;
1616         }
1617 }
1618
1619 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1620 {
1621         struct rtl_priv *rtlpriv = rtl_priv(hw);
1622         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1623         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1624         u16 i, usvalue;
1625         u16     eeprom_id;
1626         u8 tempval;
1627         u8 hwinfo[HWSET_MAX_SIZE_92S];
1628         u8 rf_path, index;
1629
1630         if (rtlefuse->epromtype == EEPROM_93C46) {
1631                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1632                          ("RTL819X Not boot from eeprom, check it !!"));
1633         } else if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1634                 rtl_efuse_shadow_map_update(hw);
1635
1636                 memcpy((void *)hwinfo, (void *)
1637                         &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1638                         HWSET_MAX_SIZE_92S);
1639         }
1640
1641         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, ("MAP\n"),
1642                       hwinfo, HWSET_MAX_SIZE_92S);
1643
1644         eeprom_id = *((u16 *)&hwinfo[0]);
1645         if (eeprom_id != RTL8190_EEPROM_ID) {
1646                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1647                          ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
1648                 rtlefuse->autoload_failflag = true;
1649         } else {
1650                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1651                 rtlefuse->autoload_failflag = false;
1652         }
1653
1654         if (rtlefuse->autoload_failflag == true)
1655                 return;
1656
1657         _rtl8192se_get_IC_Inferiority(hw);
1658
1659         /* Read IC Version && Channel Plan */
1660         /* VID, DID      SE     0xA-D */
1661         rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1662         rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1663         rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1664         rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1665         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1666
1667         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1668                         ("EEPROMId = 0x%4x\n", eeprom_id));
1669         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1670                         ("EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid));
1671         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1672                         ("EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did));
1673         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1674                         ("EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid));
1675         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1676                         ("EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid));
1677
1678         for (i = 0; i < 6; i += 2) {
1679                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1680                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1681         }
1682
1683         for (i = 0; i < 6; i++)
1684                 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1685
1686         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1687                  (MAC_FMT "\n", MAC_ARG(rtlefuse->dev_addr)));
1688
1689         /* Get Tx Power Level by Channel */
1690         /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1691         /* 92S suupport RF A & B */
1692         for (rf_path = 0; rf_path < 2; rf_path++) {
1693                 for (i = 0; i < 3; i++) {
1694                         /* Read CCK RF A & B Tx power  */
1695                         rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1696                         hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1697
1698                         /* Read OFDM RF A & B Tx power for 1T */
1699                         rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1700                         hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1701
1702                         /* Read OFDM RF A & B Tx power for 2T */
1703                         rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][i]
1704                                  = hwinfo[EEPROM_TXPOWERBASE + 12 +
1705                                    rf_path * 3 + i];
1706                 }
1707         }
1708
1709         for (rf_path = 0; rf_path < 2; rf_path++)
1710                 for (i = 0; i < 3; i++)
1711                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1712                                 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1713                                 i, rtlefuse->eeprom_chnlarea_txpwr_cck
1714                                         [rf_path][i]));
1715         for (rf_path = 0; rf_path < 2; rf_path++)
1716                 for (i = 0; i < 3; i++)
1717                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1718                                 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1719                                  rf_path, i,
1720                                  rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1721                                                 [rf_path][i]));
1722         for (rf_path = 0; rf_path < 2; rf_path++)
1723                 for (i = 0; i < 3; i++)
1724                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1725                                 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1726                                  rf_path, i,
1727                                  rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1728                                         [rf_path][i]));
1729
1730         for (rf_path = 0; rf_path < 2; rf_path++) {
1731
1732                 /* Assign dedicated channel tx power */
1733                 for (i = 0; i < 14; i++)        {
1734                         /* channel 1~3 use the same Tx Power Level. */
1735                         if (i < 3)
1736                                 index = 0;
1737                         /* Channel 4-8 */
1738                         else if (i < 8)
1739                                 index = 1;
1740                         /* Channel 9-14 */
1741                         else
1742                                 index = 2;
1743
1744                         /* Record A & B CCK /OFDM - 1T/2T Channel area
1745                          * tx power */
1746                         rtlefuse->txpwrlevel_cck[rf_path][i]  =
1747                                 rtlefuse->eeprom_chnlarea_txpwr_cck
1748                                                         [rf_path][index];
1749                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i]  =
1750                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1751                                                         [rf_path][index];
1752                         rtlefuse->txpwrlevel_ht40_2s[rf_path][i]  =
1753                                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif
1754                                                         [rf_path][index];
1755                 }
1756
1757                 for (i = 0; i < 14; i++) {
1758                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1759                                 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1760                                  "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1761                                  rtlefuse->txpwrlevel_cck[rf_path][i],
1762                                  rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1763                                  rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
1764                 }
1765         }
1766
1767         for (rf_path = 0; rf_path < 2; rf_path++) {
1768                 for (i = 0; i < 3; i++) {
1769                         /* Read Power diff limit. */
1770                         rtlefuse->eeprom_pwrgroup[rf_path][i] =
1771                                 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1772                 }
1773         }
1774
1775         for (rf_path = 0; rf_path < 2; rf_path++) {
1776                 /* Fill Pwr group */
1777                 for (i = 0; i < 14; i++) {
1778                         /* Chanel 1-3 */
1779                         if (i < 3)
1780                                 index = 0;
1781                         /* Channel 4-8 */
1782                         else if (i < 8)
1783                                 index = 1;
1784                         /* Channel 9-13 */
1785                         else
1786                                 index = 2;
1787
1788                         rtlefuse->pwrgroup_ht20[rf_path][i] =
1789                                 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1790                                 0xf);
1791                         rtlefuse->pwrgroup_ht40[rf_path][i] =
1792                                 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1793                                 0xf0) >> 4);
1794
1795                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1796                                 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1797                                  rf_path, i,
1798                                  rtlefuse->pwrgroup_ht20[rf_path][i]));
1799                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1800                                 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1801                                  rf_path, i,
1802                                  rtlefuse->pwrgroup_ht40[rf_path][i]));
1803                         }
1804         }
1805
1806         for (i = 0; i < 14; i++) {
1807                 /* Read tx power difference between HT OFDM 20/40 MHZ */
1808                 /* channel 1-3 */
1809                 if (i < 3)
1810                         index = 0;
1811                 /* Channel 4-8 */
1812                 else if (i < 8)
1813                         index = 1;
1814                 /* Channel 9-14 */
1815                 else
1816                         index = 2;
1817
1818                 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_HT20_DIFF +
1819                            index]) & 0xff;
1820                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1821                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1822                                                  ((tempval >> 4) & 0xF);
1823
1824                 /* Read OFDM<->HT tx power diff */
1825                 /* Channel 1-3 */
1826                 if (i < 3)
1827                         index = 0;
1828                 /* Channel 4-8 */
1829                 else if (i < 8)
1830                         index = 0x11;
1831                 /* Channel 9-14 */
1832                 else
1833                         index = 1;
1834
1835                 tempval = (*(u8 *)&hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index])
1836                                   & 0xff;
1837                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1838                                  (tempval & 0xF);
1839                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1840                                  ((tempval >> 4) & 0xF);
1841
1842                 tempval = (*(u8 *)&hwinfo[TX_PWR_SAFETY_CHK]);
1843                 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1844         }
1845
1846         rtlefuse->eeprom_regulatory = 0;
1847         if (rtlefuse->eeprom_version >= 2) {
1848                 /* BIT(0)~2 */
1849                 if (rtlefuse->eeprom_version >= 4)
1850                         rtlefuse->eeprom_regulatory =
1851                                  (hwinfo[EEPROM_REGULATORY] & 0x7);
1852                 else /* BIT(0) */
1853                         rtlefuse->eeprom_regulatory =
1854                                  (hwinfo[EEPROM_REGULATORY] & 0x1);
1855         }
1856         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1857                 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
1858
1859         for (i = 0; i < 14; i++)
1860                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1861                         ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1862                          rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
1863         for (i = 0; i < 14; i++)
1864                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1865                         ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1866                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
1867         for (i = 0; i < 14; i++)
1868                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1869                         ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1870                          rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
1871         for (i = 0; i < 14; i++)
1872                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1873                         ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1874                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
1875
1876         RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TxPwrSafetyFlag = %d\n",
1877                 rtlefuse->txpwr_safetyflag));
1878
1879         /* Read RF-indication and Tx Power gain
1880          * index diff of legacy to HT OFDM rate. */
1881         tempval = (*(u8 *)&hwinfo[EEPROM_RFIND_POWERDIFF]) & 0xff;
1882         rtlefuse->eeprom_txpowerdiff = tempval;
1883         rtlefuse->legacy_httxpowerdiff =
1884                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1885
1886         RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TxPowerDiff = %#x\n",
1887                 rtlefuse->eeprom_txpowerdiff));
1888
1889         /* Get TSSI value for each path. */
1890         usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1891         rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1892         usvalue = *(u8 *)&hwinfo[EEPROM_TSSI_B];
1893         rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1894
1895         RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1896                  rtlefuse->eeprom_tssi[RF90_PATH_A],
1897                  rtlefuse->eeprom_tssi[RF90_PATH_B]));
1898
1899         /* Read antenna tx power offset of B/C/D to A  from EEPROM */
1900         /* and read ThermalMeter from EEPROM */
1901         tempval = *(u8 *)&hwinfo[EEPROM_THERMALMETER];
1902         rtlefuse->eeprom_thermalmeter = tempval;
1903         RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("thermalmeter = 0x%x\n",
1904                 rtlefuse->eeprom_thermalmeter));
1905
1906         /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1907         rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1908         rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1909
1910         /* Read CrystalCap from EEPROM */
1911         tempval = (*(u8 *)&hwinfo[EEPROM_CRYSTALCAP]) >> 4;
1912         rtlefuse->eeprom_crystalcap = tempval;
1913         /* CrystalCap, BIT(12)~15 */
1914         rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1915
1916         /* Read IC Version && Channel Plan */
1917         /* Version ID, Channel plan */
1918         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1919         rtlefuse->txpwr_fromeprom = true;
1920         RTPRINT(rtlpriv, FINIT, INIT_TxPower, ("EEPROM ChannelPlan = 0x%4x\n",
1921                 rtlefuse->eeprom_channelplan));
1922
1923         /* Read Customer ID or Board Type!!! */
1924         tempval = *(u8 *)&hwinfo[EEPROM_BOARDTYPE];
1925         /* Change RF type definition */
1926         if (tempval == 0)
1927                 rtlphy->rf_type = RF_2T2R;
1928         else if (tempval == 1)
1929                 rtlphy->rf_type = RF_1T2R;
1930         else if (tempval == 2)
1931                 rtlphy->rf_type = RF_1T2R;
1932         else if (tempval == 3)
1933                 rtlphy->rf_type = RF_1T1R;
1934
1935         /* 1T2R but 1SS (1x1 receive combining) */
1936         rtlefuse->b1x1_recvcombine = false;
1937         if (rtlphy->rf_type == RF_1T2R) {
1938                 tempval = rtl_read_byte(rtlpriv, 0x07);
1939                 if (!(tempval & BIT(0))) {
1940                         rtlefuse->b1x1_recvcombine = true;
1941                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1942                                 ("RF_TYPE=1T2R but only 1SS\n"));
1943                 }
1944         }
1945         rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
1946         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMID];
1947
1948         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("EEPROM Customer ID: 0x%2x",
1949                         rtlefuse->eeprom_oemid));
1950
1951         /* set channel paln to world wide 13 */
1952         rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1953 }
1954
1955 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
1956 {
1957         struct rtl_priv *rtlpriv = rtl_priv(hw);
1958         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1959         u8 tmp_u1b = 0;
1960
1961         tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
1962
1963         if (tmp_u1b & BIT(4)) {
1964                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
1965                 rtlefuse->epromtype = EEPROM_93C46;
1966         } else {
1967                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
1968                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1969         }
1970
1971         if (tmp_u1b & BIT(5)) {
1972                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1973                 rtlefuse->autoload_failflag = false;
1974                 _rtl92se_read_adapter_info(hw);
1975         } else {
1976                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
1977                 rtlefuse->autoload_failflag = true;
1978         }
1979 }
1980
1981 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
1982                                           struct ieee80211_sta *sta)
1983 {
1984         struct rtl_priv *rtlpriv = rtl_priv(hw);
1985         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1986         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1987         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1988         u32 ratr_value;
1989         u8 ratr_index = 0;
1990         u8 nmode = mac->ht_enable;
1991         u8 mimo_ps = IEEE80211_SMPS_OFF;
1992         u16 shortgi_rate = 0;
1993         u32 tmp_ratr_value = 0;
1994         u8 curtxbw_40mhz = mac->bw_40;
1995         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1996                                 1 : 0;
1997         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1998                                 1 : 0;
1999         enum wireless_mode wirelessmode = mac->mode;
2000
2001         if (rtlhal->current_bandtype == BAND_ON_5G)
2002                 ratr_value = sta->supp_rates[1] << 4;
2003         else
2004                 ratr_value = sta->supp_rates[0];
2005         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2006                         sta->ht_cap.mcs.rx_mask[0] << 12);
2007         switch (wirelessmode) {
2008         case WIRELESS_MODE_B:
2009                 ratr_value &= 0x0000000D;
2010                 break;
2011         case WIRELESS_MODE_G:
2012                 ratr_value &= 0x00000FF5;
2013                 break;
2014         case WIRELESS_MODE_N_24G:
2015         case WIRELESS_MODE_N_5G:
2016                 nmode = 1;
2017                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2018                         ratr_value &= 0x0007F005;
2019                 } else {
2020                         u32 ratr_mask;
2021
2022                         if (get_rf_type(rtlphy) == RF_1T2R ||
2023                             get_rf_type(rtlphy) == RF_1T1R) {
2024                                 if (curtxbw_40mhz)
2025                                         ratr_mask = 0x000ff015;
2026                                 else
2027                                         ratr_mask = 0x000ff005;
2028                         } else {
2029                                 if (curtxbw_40mhz)
2030                                         ratr_mask = 0x0f0ff015;
2031                                 else
2032                                         ratr_mask = 0x0f0ff005;
2033                         }
2034
2035                         ratr_value &= ratr_mask;
2036                 }
2037                 break;
2038         default:
2039                 if (rtlphy->rf_type == RF_1T2R)
2040                         ratr_value &= 0x000ff0ff;
2041                 else
2042                         ratr_value &= 0x0f0ff0ff;
2043
2044                 break;
2045         }
2046
2047         if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2048                 ratr_value &= 0x0FFFFFFF;
2049         else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2050                 ratr_value &= 0x0FFFFFF0;
2051
2052         if (nmode && ((curtxbw_40mhz &&
2053                          curshortgi_40mhz) || (!curtxbw_40mhz &&
2054                                                  curshortgi_20mhz))) {
2055
2056                 ratr_value |= 0x10000000;
2057                 tmp_ratr_value = (ratr_value >> 12);
2058
2059                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2060                         if ((1 << shortgi_rate) & tmp_ratr_value)
2061                                 break;
2062                 }
2063
2064                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2065                     (shortgi_rate << 4) | (shortgi_rate);
2066
2067                 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2068         }
2069
2070         rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2071         if (ratr_value & 0xfffff000)
2072                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2073         else
2074                 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2075
2076         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2077                  ("%x\n", rtl_read_dword(rtlpriv, ARFR0)));
2078 }
2079
2080 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2081                                          struct ieee80211_sta *sta,
2082                                          u8 rssi_level)
2083 {
2084         struct rtl_priv *rtlpriv = rtl_priv(hw);
2085         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2086         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2087         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2088         struct rtl_sta_info *sta_entry = NULL;
2089         u32 ratr_bitmap;
2090         u8 ratr_index = 0;
2091         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2092                                 ? 1 : 0;
2093         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2094                                 1 : 0;
2095         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2096                                 1 : 0;
2097         enum wireless_mode wirelessmode = 0;
2098         bool shortgi = false;
2099         u32 ratr_value = 0;
2100         u8 shortgi_rate = 0;
2101         u32 mask = 0;
2102         u32 band = 0;
2103         bool bmulticast = false;
2104         u8 macid = 0;
2105         u8 mimo_ps = IEEE80211_SMPS_OFF;
2106
2107         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2108         wirelessmode = sta_entry->wireless_mode;
2109         if (mac->opmode == NL80211_IFTYPE_STATION)
2110                 curtxbw_40mhz = mac->bw_40;
2111         else if (mac->opmode == NL80211_IFTYPE_AP ||
2112                 mac->opmode == NL80211_IFTYPE_ADHOC)
2113                 macid = sta->aid + 1;
2114
2115         if (rtlhal->current_bandtype == BAND_ON_5G)
2116                 ratr_bitmap = sta->supp_rates[1] << 4;
2117         else
2118                 ratr_bitmap = sta->supp_rates[0];
2119         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2120                         sta->ht_cap.mcs.rx_mask[0] << 12);
2121         switch (wirelessmode) {
2122         case WIRELESS_MODE_B:
2123                 band |= WIRELESS_11B;
2124                 ratr_index = RATR_INX_WIRELESS_B;
2125                 if (ratr_bitmap & 0x0000000c)
2126                         ratr_bitmap &= 0x0000000d;
2127                 else
2128                         ratr_bitmap &= 0x0000000f;
2129                 break;
2130         case WIRELESS_MODE_G:
2131                 band |= (WIRELESS_11G | WIRELESS_11B);
2132                 ratr_index = RATR_INX_WIRELESS_GB;
2133
2134                 if (rssi_level == 1)
2135                         ratr_bitmap &= 0x00000f00;
2136                 else if (rssi_level == 2)
2137                         ratr_bitmap &= 0x00000ff0;
2138                 else
2139                         ratr_bitmap &= 0x00000ff5;
2140                 break;
2141         case WIRELESS_MODE_A:
2142                 band |= WIRELESS_11A;
2143                 ratr_index = RATR_INX_WIRELESS_A;
2144                 ratr_bitmap &= 0x00000ff0;
2145                 break;
2146         case WIRELESS_MODE_N_24G:
2147         case WIRELESS_MODE_N_5G:
2148                 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2149                 ratr_index = RATR_INX_WIRELESS_NGB;
2150
2151                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2152                         if (rssi_level == 1)
2153                                 ratr_bitmap &= 0x00070000;
2154                         else if (rssi_level == 2)
2155                                 ratr_bitmap &= 0x0007f000;
2156                         else
2157                                 ratr_bitmap &= 0x0007f005;
2158                 } else {
2159                         if (rtlphy->rf_type == RF_1T2R ||
2160                                 rtlphy->rf_type == RF_1T1R) {
2161                                 if (rssi_level == 1) {
2162                                                 ratr_bitmap &= 0x000f0000;
2163                                 } else if (rssi_level == 3) {
2164                                         ratr_bitmap &= 0x000fc000;
2165                                 } else if (rssi_level == 5) {
2166                                                 ratr_bitmap &= 0x000ff000;
2167                                 } else {
2168                                         if (curtxbw_40mhz)
2169                                                 ratr_bitmap &= 0x000ff015;
2170                                         else
2171                                                 ratr_bitmap &= 0x000ff005;
2172                                 }
2173                         } else {
2174                                 if (rssi_level == 1) {
2175                                         ratr_bitmap &= 0x0f8f0000;
2176                                 } else if (rssi_level == 3) {
2177                                         ratr_bitmap &= 0x0f8fc000;
2178                                 } else if (rssi_level == 5) {
2179                                         ratr_bitmap &= 0x0f8ff000;
2180                                 } else {
2181                                         if (curtxbw_40mhz)
2182                                                 ratr_bitmap &= 0x0f8ff015;
2183                                         else
2184                                                 ratr_bitmap &= 0x0f8ff005;
2185                                 }
2186                         }
2187                 }
2188
2189                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2190                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2191                         if (macid == 0)
2192                                 shortgi = true;
2193                         else if (macid == 1)
2194                                 shortgi = false;
2195                 }
2196                 break;
2197         default:
2198                 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2199                 ratr_index = RATR_INX_WIRELESS_NGB;
2200
2201                 if (rtlphy->rf_type == RF_1T2R)
2202                         ratr_bitmap &= 0x000ff0ff;
2203                 else
2204                         ratr_bitmap &= 0x0f8ff0ff;
2205                 break;
2206         }
2207
2208         if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2209                 ratr_bitmap &= 0x0FFFFFFF;
2210         else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2211                 ratr_bitmap &= 0x0FFFFFF0;
2212
2213         if (shortgi) {
2214                 ratr_bitmap |= 0x10000000;
2215                 /* Get MAX MCS available. */
2216                 ratr_value = (ratr_bitmap >> 12);
2217                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2218                         if ((1 << shortgi_rate) & ratr_value)
2219                                 break;
2220                 }
2221
2222                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2223                         (shortgi_rate << 4) | (shortgi_rate);
2224                 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2225         }
2226
2227         mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2228
2229         RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, ("mask = %x, bitmap = %x\n",
2230                         mask, ratr_bitmap));
2231         rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2232         rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2233
2234         if (macid != 0)
2235                 sta_entry->ratr_index = ratr_index;
2236 }
2237
2238 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2239                 struct ieee80211_sta *sta, u8 rssi_level)
2240 {
2241         struct rtl_priv *rtlpriv = rtl_priv(hw);
2242
2243         if (rtlpriv->dm.useramask)
2244                 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2245         else
2246                 rtl92se_update_hal_rate_table(hw, sta);
2247 }
2248
2249 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2250 {
2251         struct rtl_priv *rtlpriv = rtl_priv(hw);
2252         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2253         u16 sifs_timer;
2254
2255         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2256                                       (u8 *)&mac->slot_time);
2257         sifs_timer = 0x0e0e;
2258         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2259
2260 }
2261
2262 /* this ifunction is for RFKILL, it's different with windows,
2263  * because UI will disable wireless when GPIO Radio Off.
2264  * And here we not check or Disable/Enable ASPM like windows*/
2265 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2266 {
2267         struct rtl_priv *rtlpriv = rtl_priv(hw);
2268         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2269         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2270         enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2271         unsigned long flag = 0;
2272         bool actuallyset = false;
2273         bool turnonbypowerdomain = false;
2274
2275         /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2276         if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2277                 return false;
2278
2279         if (ppsc->swrf_processing)
2280                 return false;
2281
2282         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2283         if (ppsc->rfchange_inprogress) {
2284                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2285                 return false;
2286         } else {
2287                 ppsc->rfchange_inprogress = true;
2288                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2289         }
2290
2291         /* cur_rfstate = ppsc->rfpwr_state;*/
2292
2293         /* because after _rtl92s_phy_set_rfhalt, all power
2294          * closed, so we must open some power for GPIO check,
2295          * or we will always check GPIO RFOFF here,
2296          * And we should close power after GPIO check */
2297         if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2298                 _rtl92se_power_domain_init(hw);
2299                 turnonbypowerdomain = true;
2300         }
2301
2302         rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2303
2304         if ((ppsc->hwradiooff == true) && (rfpwr_toset == ERFON)) {
2305                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2306                          ("RFKILL-HW Radio ON, RF ON\n"));
2307
2308                 rfpwr_toset = ERFON;
2309                 ppsc->hwradiooff = false;
2310                 actuallyset = true;
2311         } else if ((ppsc->hwradiooff == false) && (rfpwr_toset == ERFOFF)) {
2312                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2313                          ("RFKILL-HW Radio OFF, RF OFF\n"));
2314
2315                 rfpwr_toset = ERFOFF;
2316                 ppsc->hwradiooff = true;
2317                 actuallyset = true;
2318         }
2319
2320         if (actuallyset) {
2321                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2322                 ppsc->rfchange_inprogress = false;
2323                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2324
2325         /* this not include ifconfig wlan0 down case */
2326         /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2327         } else {
2328                 /* because power_domain_init may be happen when
2329                  * _rtl92s_phy_set_rfhalt, this will open some powers
2330                  * and cause current increasing about 40 mA for ips,
2331                  * rfoff and ifconfig down, so we set
2332                  * _rtl92s_phy_set_rfhalt again here */
2333                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2334                         turnonbypowerdomain) {
2335                         _rtl92s_phy_set_rfhalt(hw);
2336                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2337                 }
2338
2339                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2340                 ppsc->rfchange_inprogress = false;
2341                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2342         }
2343
2344         *valid = 1;
2345         return !ppsc->hwradiooff;
2346
2347 }
2348
2349 /* Is_wepkey just used for WEP used as group & pairwise key
2350  * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2351 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2352         bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2353 {
2354         struct rtl_priv *rtlpriv = rtl_priv(hw);
2355         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2356         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2357         u8 *macaddr = p_macaddr;
2358
2359         u32 entry_id = 0;
2360         bool is_pairwise = false;
2361
2362         static u8 cam_const_addr[4][6] = {
2363                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2364                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2365                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2366                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2367         };
2368         static u8 cam_const_broad[] = {
2369                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2370         };
2371
2372         if (clear_all) {
2373                 u8 idx = 0;
2374                 u8 cam_offset = 0;
2375                 u8 clear_number = 5;
2376
2377                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
2378
2379                 for (idx = 0; idx < clear_number; idx++) {
2380                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2381                         rtl_cam_empty_entry(hw, cam_offset + idx);
2382
2383                         if (idx < 5) {
2384                                 memset(rtlpriv->sec.key_buf[idx], 0,
2385                                        MAX_KEY_LEN);
2386                                 rtlpriv->sec.key_len[idx] = 0;
2387                         }
2388                 }
2389
2390         } else {
2391                 switch (enc_algo) {
2392                 case WEP40_ENCRYPTION:
2393                         enc_algo = CAM_WEP40;
2394                         break;
2395                 case WEP104_ENCRYPTION:
2396                         enc_algo = CAM_WEP104;
2397                         break;
2398                 case TKIP_ENCRYPTION:
2399                         enc_algo = CAM_TKIP;
2400                         break;
2401                 case AESCCMP_ENCRYPTION:
2402                         enc_algo = CAM_AES;
2403                         break;
2404                 default:
2405                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2406                                         ("switch case not process\n"));
2407                         enc_algo = CAM_TKIP;
2408                         break;
2409                 }
2410
2411                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2412                         macaddr = cam_const_addr[key_index];
2413                         entry_id = key_index;
2414                 } else {
2415                         if (is_group) {
2416                                 macaddr = cam_const_broad;
2417                                 entry_id = key_index;
2418                         } else {
2419                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2420                                         entry_id = rtl_cam_get_free_entry(hw,
2421                                                                  p_macaddr);
2422                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2423                                                 RT_TRACE(rtlpriv,
2424                                                    COMP_SEC, DBG_EMERG,
2425                                                    ("Can not find free hw"
2426                                                    " security cam entry\n"));
2427                                                 return;
2428                                         }
2429                                 } else {
2430                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2431                                 }
2432
2433                                 key_index = PAIRWISE_KEYIDX;
2434                                 is_pairwise = true;
2435                         }
2436                 }
2437
2438                 if (rtlpriv->sec.key_len[key_index] == 0) {
2439                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2440                                  ("delete one entry, entry_id is %d\n",
2441                                  entry_id));
2442                         if (mac->opmode == NL80211_IFTYPE_AP)
2443                                 rtl_cam_del_entry(hw, p_macaddr);
2444                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2445                 } else {
2446                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2447                                  ("The insert KEY length is %d\n",
2448                                   rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
2449                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2450                                  ("The insert KEY  is %x %x\n",
2451                                   rtlpriv->sec.key_buf[0][0],
2452                                   rtlpriv->sec.key_buf[0][1]));
2453
2454                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2455                                  ("add one entry\n"));
2456                         if (is_pairwise) {
2457                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2458                                       "Pairwiase Key content :",
2459                                        rtlpriv->sec.pairwise_key,
2460                                        rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2461
2462                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2463                                          ("set Pairwiase key\n"));
2464
2465                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2466                                         entry_id, enc_algo,
2467                                         CAM_CONFIG_NO_USEDK,
2468                                         rtlpriv->sec.key_buf[key_index]);
2469                         } else {
2470                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2471                                          ("set group key\n"));
2472
2473                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2474                                         rtl_cam_add_one_entry(hw,
2475                                                 rtlefuse->dev_addr,
2476                                                 PAIRWISE_KEYIDX,
2477                                                 CAM_PAIRWISE_KEY_POSITION,
2478                                                 enc_algo, CAM_CONFIG_NO_USEDK,
2479                                                 rtlpriv->sec.key_buf[entry_id]);
2480                                 }
2481
2482                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2483                                               entry_id, enc_algo,
2484                                               CAM_CONFIG_NO_USEDK,
2485                                               rtlpriv->sec.key_buf[entry_id]);
2486                         }
2487
2488                 }
2489         }
2490 }
2491
2492 void rtl92se_suspend(struct ieee80211_hw *hw)
2493 {
2494         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2495
2496         rtlpci->up_first_time = true;
2497 }
2498
2499 void rtl92se_resume(struct ieee80211_hw *hw)
2500 {
2501         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2502         u32 val;
2503
2504         pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2505         if ((val & 0x0000ff00) != 0)
2506                 pci_write_config_dword(rtlpci->pdev, 0x40,
2507                         val & 0xffff00ff);
2508 }