drivers/net/wireless/rtlwifi/rtl8192ce/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../efuse.h"
  32 #include "../base.h"
  33 #include "../cam.h"
  34 #include "../ps.h"
  35 #include "../pci.h"
  36 #include "reg.h"
  37 #include "def.h"
  38 #include "phy.h"
  39 #include "dm.h"
  40 #include "fw.h"
  41 #include "led.h"
  42 #include "hw.h"
  43
  44 #define LLT_CONFIG      5
  45
  46 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  47                                       u8 set_bits, u8 clear_bits)
  48 {
  49         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  50         struct rtl_priv *rtlpriv = rtl_priv(hw);
  51
  52         rtlpci->reg_bcn_ctrl_val |= set_bits;
  53         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  54
  55         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  56 }
  57
  58 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
  59 {
  60         struct rtl_priv *rtlpriv = rtl_priv(hw);
  61         u8 tmp1byte;
  62
  63         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  64         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  65         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  66         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  67         tmp1byte &= ~(BIT(0));
  68         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  69 }
  70
  71 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
  72 {
  73         struct rtl_priv *rtlpriv = rtl_priv(hw);
  74         u8 tmp1byte;
  75
  76         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  77         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  78         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  79         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  80         tmp1byte |= BIT(0);
  81         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  82 }
  83
  84 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
  85 {
  86         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
  87 }
  88
  89 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
  90 {
  91         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
  92 }
  93
  94 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
  95 {
  96         struct rtl_priv *rtlpriv = rtl_priv(hw);
  97         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  98         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  99
 100         switch (variable) {
 101         case HW_VAR_RCR:
 102                 *((u32 *) (val)) = rtlpci->receive_config;
 103                 break;
 104         case HW_VAR_RF_STATE:
 105                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 106                 break;
 107         case HW_VAR_FWLPS_RF_ON:{
 108                         enum rf_pwrstate rfState;
 109                         u32 val_rcr;
 110
 111                         rtlpriv->cfg->ops->get_hw_reg(hw,
 112                                                       HW_VAR_RF_STATE,
 113                                                       (u8 *) (&rfState));
 114                         if (rfState == ERFOFF) {
 115                                 *((bool *) (val)) = true;
 116                         } else {
 117                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 118                                 val_rcr &= 0x00070000;
 119                                 if (val_rcr)
 120                                         *((bool *) (val)) = false;
 121                                 else
 122                                         *((bool *) (val)) = true;
 123                         }
 124                         break;
 125                 }
 126         case HW_VAR_FW_PSMODE_STATUS:
 127                 *((bool *) (val)) = ppsc->b_fw_current_inpsmode;
 128                 break;
 129         case HW_VAR_CORRECT_TSF:{
 130                 u64 tsf;
 131                 u32 *ptsf_low = (u32 *)&tsf;
 132                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 133
 134                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 135                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 136
 137                 *((u64 *) (val)) = tsf;
 138
 139                 break;
 140                 }
 141         case HW_VAR_MGT_FILTER:
 142                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
 143                 break;
 144         case HW_VAR_CTRL_FILTER:
 145                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
 146                 break;
 147         case HW_VAR_DATA_FILTER:
 148                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
 149                 break;
 150         default:
 151                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 152                          ("switch case not process\n"));
 153                 break;
 154         }
 155 }
 156
 157 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 158 {
 159         struct rtl_priv *rtlpriv = rtl_priv(hw);
 160         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 161         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 162         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 163         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 164         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 165         u8 idx;
 166
 167         switch (variable) {
 168         case HW_VAR_ETHER_ADDR:{
 169                         for (idx = 0; idx < ETH_ALEN; idx++) {
 170                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
 171                                                val[idx]);
 172                         }
 173                         break;
 174                 }
 175         case HW_VAR_BASIC_RATE:{
 176                         u16 b_rate_cfg = ((u16 *) val)[0];
 177                         u8 rate_index = 0;
 178                         b_rate_cfg = b_rate_cfg & 0x15f;
 179                         b_rate_cfg |= 0x01;
 180                         rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 181                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
 182                                        (b_rate_cfg >> 8)&0xff);
 183                         while (b_rate_cfg > 0x1) {
 184                                 b_rate_cfg = (b_rate_cfg >> 1);
 185                                 rate_index++;
 186                         }
 187                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 188                                        rate_index);
 189                         break;
 190                 }
 191         case HW_VAR_BSSID:{
 192                         for (idx = 0; idx < ETH_ALEN; idx++) {
 193                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 194                                                val[idx]);
 195                         }
 196                         break;
 197                 }
 198         case HW_VAR_SIFS:{
 199                         rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 200                         rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 201
 202                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 203                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 204
 205                         if (!mac->ht_enable)
 206                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 207                                                0x0e0e);
 208                         else
 209                                 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 210                                                *((u16 *) val));
 211                         break;
 212                 }
 213         case HW_VAR_SLOT_TIME:{
 214                         u8 e_aci;
 215
 216                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 217                                  ("HW_VAR_SLOT_TIME %x\n", val[0]));
 218
 219                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 220
 221                         for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 222                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 223                                                               HW_VAR_AC_PARAM,
 224                                                               (u8 *) (&e_aci));
 225                         }
 226                         break;
 227                 }
 228         case HW_VAR_ACK_PREAMBLE:{
 229                         u8 reg_tmp;
 230                         u8 short_preamble = (bool) (*(u8 *) val);
 231                         reg_tmp = (mac->cur_40_prime_sc) << 5;
 232                         if (short_preamble)
 233                                 reg_tmp |= 0x80;
 234
 235                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
 236                         break;
 237                 }
 238         case HW_VAR_AMPDU_MIN_SPACE:{
 239                         u8 min_spacing_to_set;
 240                         u8 sec_min_space;
 241
 242                         min_spacing_to_set = *((u8 *) val);
 243                         if (min_spacing_to_set <= 7) {
 244                                 sec_min_space = 0;
 245
 246                                 if (min_spacing_to_set < sec_min_space)
 247                                         min_spacing_to_set = sec_min_space;
 248
 249                                 mac->min_space_cfg = ((mac->min_space_cfg &
 250                                                        0xf8) |
 251                                                       min_spacing_to_set);
 252
 253                                 *val = min_spacing_to_set;
 254
 255                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 256                                          ("Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 257                                           mac->min_space_cfg));
 258
 259                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 260                                                mac->min_space_cfg);
 261                         }
 262                         break;
 263                 }
 264         case HW_VAR_SHORTGI_DENSITY:{
 265                         u8 density_to_set;
 266
 267                         density_to_set = *((u8 *) val);
 268                         mac->min_space_cfg |= (density_to_set << 3);
 269
 270                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 271                                  ("Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 272                                   mac->min_space_cfg));
 273
 274                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 275                                        mac->min_space_cfg);
 276
 277                         break;
 278                 }
 279         case HW_VAR_AMPDU_FACTOR:{
 280                         u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 281
 282                         u8 factor_toset;
 283                         u8 *p_regtoset = NULL;
 284                         u8 index = 0;
 285
 286                         p_regtoset = regtoset_normal;
 287
 288                         factor_toset = *((u8 *) val);
 289                         if (factor_toset <= 3) {
 290                                 factor_toset = (1 << (factor_toset + 2));
 291                                 if (factor_toset > 0xf)
 292                                         factor_toset = 0xf;
 293
 294                                 for (index = 0; index < 4; index++) {
 295                                         if ((p_regtoset[index] & 0xf0) >
 296                                             (factor_toset << 4))
 297                                                 p_regtoset[index] =
 298                                                     (p_regtoset[index] & 0x0f) |
 299                                                     (factor_toset << 4);
 300
 301                                         if ((p_regtoset[index] & 0x0f) >
 302                                             factor_toset)
 303                                                 p_regtoset[index] =
 304                                                     (p_regtoset[index] & 0xf0) |
 305                                                     (factor_toset);
 306
 307                                         rtl_write_byte(rtlpriv,
 308                                                        (REG_AGGLEN_LMT + index),
 309                                                        p_regtoset[index]);
 310
 311                                 }
 312
 313                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 314                                          ("Set HW_VAR_AMPDU_FACTOR: %#x\n",
 315                                           factor_toset));
 316                         }
 317                         break;
 318                 }
 319         case HW_VAR_AC_PARAM:{
 320                         u8 e_aci = *((u8 *) val);
 321                         u32 u4b_ac_param = 0;
 322
 323                         u4b_ac_param |= (u32) mac->ac[e_aci].aifs;
 324                         u4b_ac_param |= ((u32) mac->ac[e_aci].cw_min
 325                                          & 0xF) << AC_PARAM_ECW_MIN_OFFSET;
 326                         u4b_ac_param |= ((u32) mac->ac[e_aci].cw_max &
 327                                          0xF) << AC_PARAM_ECW_MAX_OFFSET;
 328                         u4b_ac_param |= (u32) mac->ac[e_aci].tx_op
 329                             << AC_PARAM_TXOP_LIMIT_OFFSET;
 330
 331                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 332                                  ("queue:%x, ac_param:%x\n", e_aci,
 333                                   u4b_ac_param));
 334
 335                         switch (e_aci) {
 336                         case AC1_BK:
 337                                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
 338                                                 u4b_ac_param);
 339                                 break;
 340                         case AC0_BE:
 341                                 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
 342                                                 u4b_ac_param);
 343                                 break;
 344                         case AC2_VI:
 345                                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
 346                                                 u4b_ac_param);
 347                                 break;
 348                         case AC3_VO:
 349                                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
 350                                                 u4b_ac_param);
 351                                 break;
 352                         default:
 353                                 RT_ASSERT(false,
 354                                   ("SetHwReg8185(): invalid aci: %d !\n",
 355                                    e_aci));
 356                                 break;
 357                         }
 358
 359                         if (rtlpci->acm_method != eAcmWay2_SW)
 360                                 rtlpriv->cfg->ops->set_hw_reg(hw,
 361                                                               HW_VAR_ACM_CTRL,
 362                                                               (u8 *) (&e_aci));
 363                         break;
 364                 }
 365         case HW_VAR_ACM_CTRL:{
 366                         u8 e_aci = *((u8 *) val);
 367                         union aci_aifsn *p_aci_aifsn =
 368                             (union aci_aifsn *)(&(mac->ac[0].aifs));
 369                         u8 acm = p_aci_aifsn->f.acm;
 370                         u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 371
 372                         acm_ctrl =
 373                             acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 374
 375                         if (acm) {
 376                                 switch (e_aci) {
 377                                 case AC0_BE:
 378                                         acm_ctrl |= AcmHw_BeqEn;
 379                                         break;
 380                                 case AC2_VI:
 381                                         acm_ctrl |= AcmHw_ViqEn;
 382                                         break;
 383                                 case AC3_VO:
 384                                         acm_ctrl |= AcmHw_VoqEn;
 385                                         break;
 386                                 default:
 387                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 388                                                  ("HW_VAR_ACM_CTRL acm set "
 389                                                   "failed: eACI is %d\n", acm));
 390                                         break;
 391                                 }
 392                         } else {
 393                                 switch (e_aci) {
 394                                 case AC0_BE:
 395                                         acm_ctrl &= (~AcmHw_BeqEn);
 396                                         break;
 397                                 case AC2_VI:
 398                                         acm_ctrl &= (~AcmHw_ViqEn);
 399                                         break;
 400                                 case AC3_VO:
 401                                         acm_ctrl &= (~AcmHw_BeqEn);
 402                                         break;
 403                                 default:
 404                                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 405                                                  ("switch case not process\n"));
 406                                         break;
 407                                 }
 408                         }
 409
 410                         RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 411                                  ("SetHwReg8190pci(): [HW_VAR_ACM_CTRL] "
 412                                   "Write 0x%X\n", acm_ctrl));
 413                         rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 414                         break;
 415                 }
 416         case HW_VAR_RCR:{
 417                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
 418                         rtlpci->receive_config = ((u32 *) (val))[0];
 419                         break;
 420                 }
 421         case HW_VAR_RETRY_LIMIT:{
 422                         u8 retry_limit = ((u8 *) (val))[0];
 423
 424                         rtl_write_word(rtlpriv, REG_RL,
 425                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 426                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
 427                         break;
 428                 }
 429         case HW_VAR_DUAL_TSF_RST:
 430                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 431                 break;
 432         case HW_VAR_EFUSE_BYTES:
 433                 rtlefuse->efuse_usedbytes = *((u16 *) val);
 434                 break;
 435         case HW_VAR_EFUSE_USAGE:
 436                 rtlefuse->efuse_usedpercentage = *((u8 *) val);
 437                 break;
 438         case HW_VAR_IO_CMD:
 439                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
 440                 break;
 441         case HW_VAR_WPA_CONFIG:
 442                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *) val));
 443                 break;
 444         case HW_VAR_SET_RPWM:{
 445                         u8 rpwm_val;
 446
 447                         rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 448                         udelay(1);
 449
 450                         if (rpwm_val & BIT(7)) {
 451                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 452                                                (*(u8 *) val));
 453                         } else {
 454                                 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 455                                                ((*(u8 *) val) | BIT(7)));
 456                         }
 457
 458                         break;
 459                 }
 460         case HW_VAR_H2C_FW_PWRMODE:{
 461                         u8 psmode = (*(u8 *) val);
 462
 463                         if ((psmode != FW_PS_ACTIVE_MODE) &&
 464                             (!IS_92C_SERIAL(rtlhal->version))) {
 465                                 rtl92c_dm_rf_saving(hw, true);
 466                         }
 467
 468                         rtl92c_set_fw_pwrmode_cmd(hw, (*(u8 *) val));
 469                         break;
 470                 }
 471         case HW_VAR_FW_PSMODE_STATUS:
 472                 ppsc->b_fw_current_inpsmode = *((bool *) val);
 473                 break;
 474         case HW_VAR_H2C_FW_JOINBSSRPT:{
 475                         u8 mstatus = (*(u8 *) val);
 476                         u8 tmp_regcr, tmp_reg422;
 477                         bool b_recover = false;
 478
 479                         if (mstatus == RT_MEDIA_CONNECT) {
 480                                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 481                                                               NULL);
 482
 483                                 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 484                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 485                                                (tmp_regcr | BIT(0)));
 486
 487                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 488                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
 489
 490                                 tmp_reg422 =
 491                                     rtl_read_byte(rtlpriv,
 492                                                   REG_FWHW_TXQ_CTRL + 2);
 493                                 if (tmp_reg422 & BIT(6))
 494                                         b_recover = true;
 495                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 496                                                tmp_reg422 & (~BIT(6)));
 497
 498                                 rtl92c_set_fw_rsvdpagepkt(hw, 0);
 499
 500                                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 501                                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
 502
 503                                 if (b_recover) {
 504                                         rtl_write_byte(rtlpriv,
 505                                                        REG_FWHW_TXQ_CTRL + 2,
 506                                                        tmp_reg422);
 507                                 }
 508
 509                                 rtl_write_byte(rtlpriv, REG_CR + 1,
 510                                                (tmp_regcr & ~(BIT(0))));
 511                         }
 512                         rtl92c_set_fw_joinbss_report_cmd(hw, (*(u8 *) val));
 513
 514                         break;
 515                 }
 516         case HW_VAR_AID:{
 517                         u16 u2btmp;
 518                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 519                         u2btmp &= 0xC000;
 520                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 521                                                 mac->assoc_id));
 522
 523                         break;
 524                 }
 525         case HW_VAR_CORRECT_TSF:{
 526                         u8 btype_ibss = ((u8 *) (val))[0];
 527
 528                         /*btype_ibss = (mac->opmode == NL80211_IFTYPE_ADHOC) ?
 529                                         1 : 0;*/
 530
 531                         if (btype_ibss == true)
 532                                 _rtl92ce_stop_tx_beacon(hw);
 533
 534                         _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
 535
 536                         rtl_write_dword(rtlpriv, REG_TSFTR,
 537                                         (u32) (mac->tsf & 0xffffffff));
 538                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 539                                         (u32) ((mac->tsf >> 32)&0xffffffff));
 540
 541                         _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
 542
 543                         if (btype_ibss == true)
 544                                 _rtl92ce_resume_tx_beacon(hw);
 545
 546                         break;
 547
 548                 }
 549         case HW_VAR_MGT_FILTER:
 550                 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *) val);
 551                 break;
 552         case HW_VAR_CTRL_FILTER:
 553                 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *) val);
 554                 break;
 555         case HW_VAR_DATA_FILTER:
 556                 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *) val);
 557                 break;
 558         default:
 559                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
 560                                                         "not process\n"));
 561                 break;
 562         }
 563 }
 564
 565 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 566 {
 567         struct rtl_priv *rtlpriv = rtl_priv(hw);
 568         bool status = true;
 569         long count = 0;
 570         u32 value = _LLT_INIT_ADDR(address) |
 571             _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
 572
 573         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 574
 575         do {
 576                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 577                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 578                         break;
 579
 580                 if (count > POLLING_LLT_THRESHOLD) {
 581                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 582                                  ("Failed to polling write LLT done at "
 583                                   "address %d!\n", address));
 584                         status = false;
 585                         break;
 586                 }
 587         } while (++count);
 588
 589         return status;
 590 }
 591
 592 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
 593 {
 594         struct rtl_priv *rtlpriv = rtl_priv(hw);
 595         unsigned short i;
 596         u8 txpktbuf_bndy;
 597         u8 maxPage;
 598         bool status;
 599
 600 #if LLT_CONFIG == 1
 601         maxPage = 255;
 602         txpktbuf_bndy = 252;
 603 #elif LLT_CONFIG == 2
 604         maxPage = 127;
 605         txpktbuf_bndy = 124;
 606 #elif LLT_CONFIG == 3
 607         maxPage = 255;
 608         txpktbuf_bndy = 174;
 609 #elif LLT_CONFIG == 4
 610         maxPage = 255;
 611         txpktbuf_bndy = 246;
 612 #elif LLT_CONFIG == 5
 613         maxPage = 255;
 614         txpktbuf_bndy = 246;
 615 #endif
 616
 617 #if LLT_CONFIG == 1
 618         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
 619         rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
 620 #elif LLT_CONFIG == 2
 621         rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
 622 #elif LLT_CONFIG == 3
 623         rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
 624 #elif LLT_CONFIG == 4
 625         rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
 626 #elif LLT_CONFIG == 5
 627         rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
 628
 629         rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
 630 #endif
 631
 632         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
 633         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 634
 635         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 636         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 637
 638         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 639         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 640         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 641
 642         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 643                 status = _rtl92ce_llt_write(hw, i, i + 1);
 644                 if (true != status)
 645                         return status;
 646         }
 647
 648         status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 649         if (true != status)
 650                 return status;
 651
 652         for (i = txpktbuf_bndy; i < maxPage; i++) {
 653                 status = _rtl92ce_llt_write(hw, i, (i + 1));
 654                 if (true != status)
 655                         return status;
 656         }
 657
 658         status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
 659         if (true != status)
 660                 return status;
 661
 662         return true;
 663 }
 664
 665 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
 666 {
 667         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 668         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 669         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 670         struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
 671
 672         if (rtlpci->up_first_time)
 673                 return;
 674
 675         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 676                 rtl92ce_sw_led_on(hw, pLed0);
 677         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 678                 rtl92ce_sw_led_on(hw, pLed0);
 679         else
 680                 rtl92ce_sw_led_off(hw, pLed0);
 681
 682 }
 683
 684 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
 685 {
 686         struct rtl_priv *rtlpriv = rtl_priv(hw);
 687         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 688         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 689
 690         unsigned char bytetmp;
 691         unsigned short wordtmp;
 692         u16 retry;
 693
 694         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 695         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 696         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
 697
 698         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
 699         udelay(2);
 700
 701         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 702         udelay(2);
 703
 704         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 705         udelay(2);
 706
 707         retry = 0;
 708         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
 709                                                 rtl_read_dword(rtlpriv, 0xEC),
 710                                                 bytetmp));
 711
 712         while ((bytetmp & BIT(0)) && retry < 1000) {
 713                 retry++;
 714                 udelay(50);
 715                 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
 716                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("reg0xec:%x:%x\n",
 717                                                         rtl_read_dword(rtlpriv,
 718                                                                        0xEC),
 719                                                         bytetmp));
 720                 udelay(50);
 721         }
 722
 723         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
 724
 725         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
 726         udelay(2);
 727
 728         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 729
 730         if (_rtl92ce_llt_table_init(hw) == false)
 731                 return false;;
 732
 733         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 734         rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
 735
 736         rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
 737
 738         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 739         wordtmp &= 0xf;
 740         wordtmp |= 0xF771;
 741         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 742
 743         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 744         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 745         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 746
 747         rtl_write_byte(rtlpriv, 0x4d0, 0x0);
 748
 749         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 750                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 751                         DMA_BIT_MASK(32));
 752         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 753                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 754                         DMA_BIT_MASK(32));
 755         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 756                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 757         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 758                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 759         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 760                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 761         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 762                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 763         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 764                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 765                         DMA_BIT_MASK(32));
 766         rtl_write_dword(rtlpriv, REG_RX_DESA,
 767                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 768                         DMA_BIT_MASK(32));
 769
 770         if (IS_92C_SERIAL(rtlhal->version))
 771                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
 772         else
 773                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
 774
 775         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 776
 777         bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 778         rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
 779         do {
 780                 retry++;
 781                 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
 782         } while ((retry < 200) && (bytetmp & BIT(7)));
 783
 784         _rtl92ce_gen_refresh_led_state(hw);
 785
 786         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 787
 788         return true;;
 789 }
 790
 791 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
 792 {
 793         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 794         struct rtl_priv *rtlpriv = rtl_priv(hw);
 795         u8 reg_bw_opmode;
 796         u32 reg_ratr, reg_prsr;
 797
 798         reg_bw_opmode = BW_OPMODE_20MHZ;
 799         reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 800             RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 801         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 802
 803         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
 804
 805         rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
 806
 807         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 808
 809         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
 810
 811         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
 812
 813         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
 814
 815         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 816
 817         rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
 818
 819         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 820
 821         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 822         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 823         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 824         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 825
 826         rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
 827
 828         rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
 829
 830         rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
 831
 832         rtlpci->reg_bcn_ctrl_val = 0x1f;
 833         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 834
 835         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 836
 837         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 838
 839         rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
 840         rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
 841
 842         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 843
 844         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
 845
 846         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
 847
 848         rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
 849
 850         rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
 851         rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
 852
 853         rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
 854
 855         rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
 856
 857         rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
 858         rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
 859
 860 }
 861
 862 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
 863 {
 864         struct rtl_priv *rtlpriv = rtl_priv(hw);
 865         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 866
 867         rtl_write_byte(rtlpriv, 0x34b, 0x93);
 868         rtl_write_word(rtlpriv, 0x350, 0x870c);
 869         rtl_write_byte(rtlpriv, 0x352, 0x1);
 870
 871         if (ppsc->b_support_backdoor)
 872                 rtl_write_byte(rtlpriv, 0x349, 0x1b);
 873         else
 874                 rtl_write_byte(rtlpriv, 0x349, 0x03);
 875
 876         rtl_write_word(rtlpriv, 0x350, 0x2718);
 877         rtl_write_byte(rtlpriv, 0x352, 0x1);
 878 }
 879
 880 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
 881 {
 882         struct rtl_priv *rtlpriv = rtl_priv(hw);
 883         u8 sec_reg_value;
 884
 885         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 886                  ("PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 887                   rtlpriv->sec.pairwise_enc_algorithm,
 888                   rtlpriv->sec.group_enc_algorithm));
 889
 890         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 891                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("not open "
 892                                                         "hw encryption\n"));
 893                 return;
 894         }
 895
 896         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
 897
 898         if (rtlpriv->sec.use_defaultkey) {
 899                 sec_reg_value |= SCR_TxUseDK;
 900                 sec_reg_value |= SCR_RxUseDK;
 901         }
 902
 903         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 904
 905         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 906
 907         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
 908                  ("The SECR-value %x\n", sec_reg_value));
 909
 910         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 911
 912 }
 913
 914 int rtl92ce_hw_init(struct ieee80211_hw *hw)
 915 {
 916         struct rtl_priv *rtlpriv = rtl_priv(hw);
 917         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 918         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 919         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 920         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 921         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 922         static bool iqk_initialized; /* initialized to false */
 923         bool rtstatus = true;
 924         bool is92c;
 925         int err;
 926         u8 tmp_u1b;
 927
 928         rtlpci->being_init_adapter = true;
 929         rtlpriv->intf_ops->disable_aspm(hw);
 930         rtstatus = _rtl92ce_init_mac(hw);
 931         if (rtstatus != true) {
 932                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Init MAC failed\n"));
 933                 err = 1;
 934                 return err;
 935         }
 936
 937         err = rtl92c_download_fw(hw);
 938         if (err) {
 939                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 940                          ("Failed to download FW. Init HW "
 941                           "without FW now..\n"));
 942                 err = 1;
 943                 rtlhal->bfw_ready = false;
 944                 return err;
 945         } else {
 946                 rtlhal->bfw_ready = true;
 947         }
 948
 949         rtlhal->last_hmeboxnum = 0;
 950         rtl92c_phy_mac_config(hw);
 951         rtl92c_phy_bb_config(hw);
 952         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 953         rtl92c_phy_rf_config(hw);
 954         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
 955                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 956         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
 957                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
 958         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
 959         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
 960         rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
 961         _rtl92ce_hw_configure(hw);
 962         rtl_cam_reset_all_entry(hw);
 963         rtl92ce_enable_hw_security_config(hw);
 964         ppsc->rfpwr_state = ERFON;
 965         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
 966         _rtl92ce_enable_aspm_back_door(hw);
 967         rtlpriv->intf_ops->enable_aspm(hw);
 968         if (ppsc->rfpwr_state == ERFON) {
 969                 rtl92c_phy_set_rfpath_switch(hw, 1);
 970                 if (iqk_initialized)
 971                         rtl92c_phy_iq_calibrate(hw, true);
 972                 else {
 973                         rtl92c_phy_iq_calibrate(hw, false);
 974                         iqk_initialized = true;
 975                 }
 976
 977                 rtl92c_dm_check_txpower_tracking(hw);
 978                 rtl92c_phy_lc_calibrate(hw);
 979         }
 980
 981         is92c = IS_92C_SERIAL(rtlhal->version);
 982         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
 983         if (!(tmp_u1b & BIT(0))) {
 984                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
 985                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path A\n"));
 986         }
 987
 988         if (!(tmp_u1b & BIT(1)) && is92c) {
 989                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
 990                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("PA BIAS path B\n"));
 991         }
 992
 993         if (!(tmp_u1b & BIT(4))) {
 994                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
 995                 tmp_u1b &= 0x0F;
 996                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
 997                 udelay(10);
 998                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
 999                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, ("under 1.5V\n"));
1000         }
1001         rtl92c_dm_init(hw);
1002         rtlpci->being_init_adapter = false;
1003         return err;
1004 }
1005
1006 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
1007 {
1008         struct rtl_priv *rtlpriv = rtl_priv(hw);
1009         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1010         enum version_8192c version = VERSION_UNKNOWN;
1011         u32 value32;
1012
1013         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1014         if (value32 & TRP_VAUX_EN) {
1015                 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1016                            VERSION_A_CHIP_88C;
1017         } else {
1018                 version = (value32 & TYPE_ID) ? VERSION_B_CHIP_92C :
1019                            VERSION_B_CHIP_88C;
1020         }
1021
1022         switch (version) {
1023         case VERSION_B_CHIP_92C:
1024                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1025                          ("Chip Version ID: VERSION_B_CHIP_92C.\n"));
1026                 break;
1027         case VERSION_B_CHIP_88C:
1028                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1029                          ("Chip Version ID: VERSION_B_CHIP_88C.\n"));
1030                 break;
1031         case VERSION_A_CHIP_92C:
1032                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1033                          ("Chip Version ID: VERSION_A_CHIP_92C.\n"));
1034                 break;
1035         case VERSION_A_CHIP_88C:
1036                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1037                          ("Chip Version ID: VERSION_A_CHIP_88C.\n"));
1038                 break;
1039         default:
1040                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1041                          ("Chip Version ID: Unknown. Bug?\n"));
1042                 break;
1043         }
1044
1045         switch (version & 0x3) {
1046         case CHIP_88C:
1047                 rtlphy->rf_type = RF_1T1R;
1048                 break;
1049         case CHIP_92C:
1050                 rtlphy->rf_type = RF_2T2R;
1051                 break;
1052         case CHIP_92C_1T2R:
1053                 rtlphy->rf_type = RF_1T2R;
1054                 break;
1055         default:
1056                 rtlphy->rf_type = RF_1T1R;
1057                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1058                          ("ERROR RF_Type is set!!"));
1059                 break;
1060         }
1061
1062         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1063                  ("Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1064                   "RF_2T2R" : "RF_1T1R"));
1065
1066         return version;
1067 }
1068
1069 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1070                                      enum nl80211_iftype type)
1071 {
1072         struct rtl_priv *rtlpriv = rtl_priv(hw);
1073         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1074         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1075         bt_msr &= 0xfc;
1076
1077         if (type == NL80211_IFTYPE_UNSPECIFIED ||
1078             type == NL80211_IFTYPE_STATION) {
1079                 _rtl92ce_stop_tx_beacon(hw);
1080                 _rtl92ce_enable_bcn_sub_func(hw);
1081         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1082                 _rtl92ce_resume_tx_beacon(hw);
1083                 _rtl92ce_disable_bcn_sub_func(hw);
1084         } else {
1085                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1086                          ("Set HW_VAR_MEDIA_STATUS: "
1087                           "No such media status(%x).\n", type));
1088         }
1089
1090         switch (type) {
1091         case NL80211_IFTYPE_UNSPECIFIED:
1092                 bt_msr |= MSR_NOLINK;
1093                 ledaction = LED_CTL_LINK;
1094                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1095                          ("Set Network type to NO LINK!\n"));
1096                 break;
1097         case NL80211_IFTYPE_ADHOC:
1098                 bt_msr |= MSR_ADHOC;
1099                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1100                          ("Set Network type to Ad Hoc!\n"));
1101                 break;
1102         case NL80211_IFTYPE_STATION:
1103                 bt_msr |= MSR_INFRA;
1104                 ledaction = LED_CTL_LINK;
1105                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1106                          ("Set Network type to STA!\n"));
1107                 break;
1108         case NL80211_IFTYPE_AP:
1109                 bt_msr |= MSR_AP;
1110                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1111                          ("Set Network type to AP!\n"));
1112                 break;
1113         default:
1114                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1115                          ("Network type %d not support!\n", type));
1116                 return 1;
1117                 break;
1118
1119         }
1120
1121         rtl_write_byte(rtlpriv, (MSR), bt_msr);
1122         rtlpriv->cfg->ops->led_control(hw, ledaction);
1123         if ((bt_msr & 0xfc) == MSR_AP)
1124                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1125         else
1126                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1127         return 0;
1128 }
1129
1130 static void _rtl92ce_set_check_bssid(struct ieee80211_hw *hw,
1131                                      enum nl80211_iftype type)
1132 {
1133         struct rtl_priv *rtlpriv = rtl_priv(hw);
1134         u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1135         u8 filterout_non_associated_bssid = false;
1136
1137         switch (type) {
1138         case NL80211_IFTYPE_ADHOC:
1139         case NL80211_IFTYPE_STATION:
1140                 filterout_non_associated_bssid = true;
1141                 break;
1142         case NL80211_IFTYPE_UNSPECIFIED:
1143         case NL80211_IFTYPE_AP:
1144         default:
1145                 break;
1146         }
1147
1148         if (filterout_non_associated_bssid == true) {
1149                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1150                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1151                                               (u8 *) (&reg_rcr));
1152                 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1153         } else if (filterout_non_associated_bssid == false) {
1154                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1155                 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1156                 rtlpriv->cfg->ops->set_hw_reg(hw,
1157                                               HW_VAR_RCR, (u8 *) (&reg_rcr));
1158         }
1159 }
1160
1161 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1162 {
1163         if (_rtl92ce_set_media_status(hw, type))
1164                 return -EOPNOTSUPP;
1165         _rtl92ce_set_check_bssid(hw, type);
1166         return 0;
1167 }
1168
1169 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1170 {
1171         struct rtl_priv *rtlpriv = rtl_priv(hw);
1172         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1173
1174         u32 u4b_ac_param;
1175
1176         rtl92c_dm_init_edca_turbo(hw);
1177
1178         u4b_ac_param = (u32) mac->ac[aci].aifs;
1179         u4b_ac_param |=
1180             ((u32) mac->ac[aci].cw_min & 0xF) << AC_PARAM_ECW_MIN_OFFSET;
1181         u4b_ac_param |=
1182             ((u32) mac->ac[aci].cw_max & 0xF) << AC_PARAM_ECW_MAX_OFFSET;
1183         u4b_ac_param |= (u32) mac->ac[aci].tx_op << AC_PARAM_TXOP_LIMIT_OFFSET;
1184         RT_TRACE(rtlpriv, COMP_QOS, DBG_DMESG,
1185                  ("queue:%x, ac_param:%x aifs:%x cwmin:%x cwmax:%x txop:%x\n",
1186                   aci, u4b_ac_param, mac->ac[aci].aifs, mac->ac[aci].cw_min,
1187                   mac->ac[aci].cw_max, mac->ac[aci].tx_op));
1188         switch (aci) {
1189         case AC1_BK:
1190                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, u4b_ac_param);
1191                 break;
1192         case AC0_BE:
1193                 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param);
1194                 break;
1195         case AC2_VI:
1196                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, u4b_ac_param);
1197                 break;
1198         case AC3_VO:
1199                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, u4b_ac_param);
1200                 break;
1201         default:
1202                 RT_ASSERT(false, ("invalid aci: %d !\n", aci));
1203                 break;
1204         }
1205 }
1206
1207 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1208 {
1209         struct rtl_priv *rtlpriv = rtl_priv(hw);
1210         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1211
1212         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1213         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1214         rtlpci->irq_enabled = true;
1215 }
1216
1217 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1218 {
1219         struct rtl_priv *rtlpriv = rtl_priv(hw);
1220         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1221
1222         rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1223         rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1224         rtlpci->irq_enabled = false;
1225 }
1226
1227 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1228 {
1229         struct rtl_priv *rtlpriv = rtl_priv(hw);
1230         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1231         u8 u1b_tmp;
1232
1233         rtlpriv->intf_ops->enable_aspm(hw);
1234         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1235         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1236         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1237         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1238         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1239         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1240         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->bfw_ready)
1241                 rtl92c_firmware_selfreset(hw);
1242         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1243         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1244         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1245         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1246         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1247                         (u1b_tmp << 8));
1248         rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1249         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1250         rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1251         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1252         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1253         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1254         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1255 }
1256
1257 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1258 {
1259         struct rtl_priv *rtlpriv = rtl_priv(hw);
1260         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1261         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1262         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1263         enum nl80211_iftype opmode;
1264
1265         mac->link_state = MAC80211_NOLINK;
1266         opmode = NL80211_IFTYPE_UNSPECIFIED;
1267         _rtl92ce_set_media_status(hw, opmode);
1268         if (rtlpci->driver_is_goingto_unload ||
1269             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1270                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1271         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1272         _rtl92ce_poweroff_adapter(hw);
1273 }
1274
1275 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1276                                   u32 *p_inta, u32 *p_intb)
1277 {
1278         struct rtl_priv *rtlpriv = rtl_priv(hw);
1279         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1280
1281         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1282         rtl_write_dword(rtlpriv, ISR, *p_inta);
1283
1284         /*
1285          * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1286          * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1287          */
1288 }
1289
1290 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1291 {
1292
1293         struct rtl_priv *rtlpriv = rtl_priv(hw);
1294         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1295         u16 bcn_interval, atim_window;
1296
1297         bcn_interval = mac->beacon_interval;
1298         atim_window = 2;        /*FIX MERGE */
1299         rtl92ce_disable_interrupt(hw);
1300         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1301         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1302         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1303         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1304         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1305         rtl_write_byte(rtlpriv, 0x606, 0x30);
1306         rtl92ce_enable_interrupt(hw);
1307 }
1308
1309 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1310 {
1311         struct rtl_priv *rtlpriv = rtl_priv(hw);
1312         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1313         u16 bcn_interval = mac->beacon_interval;
1314
1315         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1316                  ("beacon_interval:%d\n", bcn_interval));
1317         rtl92ce_disable_interrupt(hw);
1318         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1319         rtl92ce_enable_interrupt(hw);
1320 }
1321
1322 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1323                                    u32 add_msr, u32 rm_msr)
1324 {
1325         struct rtl_priv *rtlpriv = rtl_priv(hw);
1326         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1327
1328         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1329                  ("add_msr:%x, rm_msr:%x\n", add_msr, rm_msr));
1330         if (add_msr)
1331                 rtlpci->irq_mask[0] |= add_msr;
1332         if (rm_msr)
1333                 rtlpci->irq_mask[0] &= (~rm_msr);
1334         rtl92ce_disable_interrupt(hw);
1335         rtl92ce_enable_interrupt(hw);
1336 }
1337
1338 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1339                                                  bool autoload_fail,
1340                                                  u8 *hwinfo)
1341 {
1342         struct rtl_priv *rtlpriv = rtl_priv(hw);
1343         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1344         u8 rf_path, index, tempval;
1345         u16 i;
1346
1347         for (rf_path = 0; rf_path < 2; rf_path++) {
1348                 for (i = 0; i < 3; i++) {
1349                         if (!autoload_fail) {
1350                                 rtlefuse->
1351                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1352                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1353                                 rtlefuse->
1354                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1355                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1356                                            i];
1357                         } else {
1358                                 rtlefuse->
1359                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
1360                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1361                                 rtlefuse->
1362                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1363                                     EEPROM_DEFAULT_TXPOWERLEVEL;
1364                         }
1365                 }
1366         }
1367
1368         for (i = 0; i < 3; i++) {
1369                 if (!autoload_fail)
1370                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1371                 else
1372                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1373                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_A][i] =
1374                     (tempval & 0xf);
1375                 rtlefuse->eeprom_chnlarea_txpwr_ht40_2sdiif[RF90_PATH_B][i] =
1376                     ((tempval & 0xf0) >> 4);
1377         }
1378
1379         for (rf_path = 0; rf_path < 2; rf_path++)
1380                 for (i = 0; i < 3; i++)
1381                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1382                                 ("RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1383                                  i,
1384                                  rtlefuse->
1385                                  eeprom_chnlarea_txpwr_cck[rf_path][i]));
1386         for (rf_path = 0; rf_path < 2; rf_path++)
1387                 for (i = 0; i < 3; i++)
1388                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1389                                 ("RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1390                                  rf_path, i,
1391                                  rtlefuse->
1392                                  eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]));
1393         for (rf_path = 0; rf_path < 2; rf_path++)
1394                 for (i = 0; i < 3; i++)
1395                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1396                                 ("RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1397                                  rf_path, i,
1398                                  rtlefuse->
1399                                  eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1400                                  [i]));
1401
1402         for (rf_path = 0; rf_path < 2; rf_path++) {
1403                 for (i = 0; i < 14; i++) {
1404                         index = _rtl92c_get_chnl_group((u8) i);
1405
1406                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1407                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1408                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1409                             rtlefuse->
1410                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1411
1412                         if ((rtlefuse->
1413                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1414                              rtlefuse->
1415                              eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path][index])
1416                             > 0) {
1417                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1418                                     rtlefuse->
1419                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1420                                     [index] -
1421                                     rtlefuse->
1422                                     eeprom_chnlarea_txpwr_ht40_2sdiif[rf_path]
1423                                     [index];
1424                         } else {
1425                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1426                         }
1427                 }
1428
1429                 for (i = 0; i < 14; i++) {
1430                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1431                                 ("RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = "
1432                                  "[0x%x / 0x%x / 0x%x]\n", rf_path, i,
1433                                  rtlefuse->txpwrlevel_cck[rf_path][i],
1434                                  rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1435                                  rtlefuse->txpwrlevel_ht40_2s[rf_path][i]));
1436                 }
1437         }
1438
1439         for (i = 0; i < 3; i++) {
1440                 if (!autoload_fail) {
1441                         rtlefuse->eeprom_pwrlimit_ht40[i] =
1442                             hwinfo[EEPROM_TXPWR_GROUP + i];
1443                         rtlefuse->eeprom_pwrlimit_ht20[i] =
1444                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1445                 } else {
1446                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1447                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1448                 }
1449         }
1450
1451         for (rf_path = 0; rf_path < 2; rf_path++) {
1452                 for (i = 0; i < 14; i++) {
1453                         index = _rtl92c_get_chnl_group((u8) i);
1454
1455                         if (rf_path == RF90_PATH_A) {
1456                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1457                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
1458                                      & 0xf);
1459                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1460                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
1461                                      & 0xf);
1462                         } else if (rf_path == RF90_PATH_B) {
1463                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
1464                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
1465                                       & 0xf0) >> 4);
1466                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
1467                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
1468                                       & 0xf0) >> 4);
1469                         }
1470
1471                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1472                                 ("RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1473                                  rf_path, i,
1474                                  rtlefuse->pwrgroup_ht20[rf_path][i]));
1475                         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1476                                 ("RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1477                                  rf_path, i,
1478                                  rtlefuse->pwrgroup_ht40[rf_path][i]));
1479                 }
1480         }
1481
1482         for (i = 0; i < 14; i++) {
1483                 index = _rtl92c_get_chnl_group((u8) i);
1484
1485                 if (!autoload_fail)
1486                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1487                 else
1488                         tempval = EEPROM_DEFAULT_HT20_DIFF;
1489
1490                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1491                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1492                     ((tempval >> 4) & 0xF);
1493
1494                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1495                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1496
1497                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1498                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1499
1500                 index = _rtl92c_get_chnl_group((u8) i);
1501
1502                 if (!autoload_fail)
1503                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1504                 else
1505                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1506
1507                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1508                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1509                     ((tempval >> 4) & 0xF);
1510         }
1511
1512         rtlefuse->legacy_ht_txpowerdiff =
1513             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1514
1515         for (i = 0; i < 14; i++)
1516                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1517                         ("RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1518                          rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]));
1519         for (i = 0; i < 14; i++)
1520                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1521                         ("RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1522                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]));
1523         for (i = 0; i < 14; i++)
1524                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1525                         ("RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1526                          rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]));
1527         for (i = 0; i < 14; i++)
1528                 RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1529                         ("RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1530                          rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]));
1531
1532         if (!autoload_fail)
1533                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1534         else
1535                 rtlefuse->eeprom_regulatory = 0;
1536         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1537                 ("eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory));
1538
1539         if (!autoload_fail) {
1540                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1541                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1542         } else {
1543                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1544                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1545         }
1546         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1547                 ("TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1548                  rtlefuse->eeprom_tssi[RF90_PATH_A],
1549                  rtlefuse->eeprom_tssi[RF90_PATH_B]));
1550
1551         if (!autoload_fail)
1552                 tempval = hwinfo[EEPROM_THERMAL_METER];
1553         else
1554                 tempval = EEPROM_DEFAULT_THERMALMETER;
1555         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1556
1557         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1558                 rtlefuse->b_apk_thermalmeterignore = true;
1559
1560         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1561         RTPRINT(rtlpriv, FINIT, INIT_TxPower,
1562                 ("thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter));
1563 }
1564
1565 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1566 {
1567         struct rtl_priv *rtlpriv = rtl_priv(hw);
1568         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1569         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1570         u16 i, usvalue;
1571         u8 hwinfo[HWSET_MAX_SIZE];
1572         u16 eeprom_id;
1573
1574         if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1575                 rtl_efuse_shadow_map_update(hw);
1576
1577                 memcpy((void *)hwinfo,
1578                        (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1579                        HWSET_MAX_SIZE);
1580         } else if (rtlefuse->epromtype == EEPROM_93C46) {
1581                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1582                          ("RTL819X Not boot from eeprom, check it !!"));
1583         }
1584
1585         RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, ("MAP\n"),
1586                       hwinfo, HWSET_MAX_SIZE);
1587
1588         eeprom_id = *((u16 *)&hwinfo[0]);
1589         if (eeprom_id != RTL8190_EEPROM_ID) {
1590                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1591                          ("EEPROM ID(%#x) is invalid!!\n", eeprom_id));
1592                 rtlefuse->autoload_failflag = true;
1593         } else {
1594                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1595                 rtlefuse->autoload_failflag = false;
1596         }
1597
1598         if (rtlefuse->autoload_failflag == true)
1599                 return;
1600
1601         for (i = 0; i < 6; i += 2) {
1602                 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1603                 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1604         }
1605
1606         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1607                  (MAC_FMT "\n", MAC_ARG(rtlefuse->dev_addr)));
1608
1609         _rtl92ce_read_txpower_info_from_hwpg(hw,
1610                                              rtlefuse->autoload_failflag,
1611                                              hwinfo);
1612
1613         rtlefuse->eeprom_channelplan = *(u8 *)&hwinfo[EEPROM_CHANNELPLAN];
1614         rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1615         rtlefuse->b_txpwr_fromeprom = true;
1616         rtlefuse->eeprom_oemid = *(u8 *)&hwinfo[EEPROM_CUSTOMER_ID];
1617
1618         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1619                  ("EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid));
1620
1621         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1622                 switch (rtlefuse->eeprom_oemid) {
1623                 case EEPROM_CID_DEFAULT:
1624                         if (rtlefuse->eeprom_did == 0x8176) {
1625                                 if ((rtlefuse->eeprom_svid == 0x103C &&
1626                                      rtlefuse->eeprom_smid == 0x1629))
1627                                         rtlhal->oem_id = RT_CID_819x_HP;
1628                                 else
1629                                         rtlhal->oem_id = RT_CID_DEFAULT;
1630                         } else {
1631                                 rtlhal->oem_id = RT_CID_DEFAULT;
1632                         }
1633                         break;
1634                 case EEPROM_CID_TOSHIBA:
1635                         rtlhal->oem_id = RT_CID_TOSHIBA;
1636                         break;
1637                 case EEPROM_CID_QMI:
1638                         rtlhal->oem_id = RT_CID_819x_QMI;
1639                         break;
1640                 case EEPROM_CID_WHQL:
1641                 default:
1642                         rtlhal->oem_id = RT_CID_DEFAULT;
1643                         break;
1644
1645                 }
1646         }
1647
1648 }
1649
1650 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1651 {
1652         struct rtl_priv *rtlpriv = rtl_priv(hw);
1653         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1654         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1655
1656         switch (rtlhal->oem_id) {
1657         case RT_CID_819x_HP:
1658                 pcipriv->ledctl.bled_opendrain = true;
1659                 break;
1660         case RT_CID_819x_Lenovo:
1661         case RT_CID_DEFAULT:
1662         case RT_CID_TOSHIBA:
1663         case RT_CID_CCX:
1664         case RT_CID_819x_Acer:
1665         case RT_CID_WHQL:
1666         default:
1667                 break;
1668         }
1669         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1670                  ("RT Customized ID: 0x%02X\n", rtlhal->oem_id));
1671 }
1672
1673 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1674 {
1675         struct rtl_priv *rtlpriv = rtl_priv(hw);
1676         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1677         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1678         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1679         u8 tmp_u1b;
1680
1681         rtlhal->version = _rtl92ce_read_chip_version(hw);
1682         if (get_rf_type(rtlphy) == RF_1T1R)
1683                 rtlpriv->dm.brfpath_rxenable[0] = true;
1684         else
1685                 rtlpriv->dm.brfpath_rxenable[0] =
1686                     rtlpriv->dm.brfpath_rxenable[1] = true;
1687         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("VersionID = 0x%4x\n",
1688                                                 rtlhal->version));
1689         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1690         if (tmp_u1b & BIT(4)) {
1691                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EEPROM\n"));
1692                 rtlefuse->epromtype = EEPROM_93C46;
1693         } else {
1694                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, ("Boot from EFUSE\n"));
1695                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1696         }
1697         if (tmp_u1b & BIT(5)) {
1698                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, ("Autoload OK\n"));
1699                 rtlefuse->autoload_failflag = false;
1700                 _rtl92ce_read_adapter_info(hw);
1701         } else {
1702                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("Autoload ERR!!\n"));
1703         }
1704
1705         _rtl92ce_hal_customized_behavior(hw);
1706 }
1707
1708 void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw)
1709 {
1710         struct rtl_priv *rtlpriv = rtl_priv(hw);
1711         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1712         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1713
1714         u32 ratr_value = (u32) mac->basic_rates;
1715         u8 *p_mcsrate = mac->mcs;
1716         u8 ratr_index = 0;
1717         u8 b_nmode = mac->ht_enable;
1718         u8 mimo_ps = 1;
1719         u16 shortgi_rate;
1720         u32 tmp_ratr_value;
1721         u8 b_curtxbw_40mhz = mac->bw_40;
1722         u8 b_curshortgi_40mhz = mac->sgi_40;
1723         u8 b_curshortgi_20mhz = mac->sgi_20;
1724         enum wireless_mode wirelessmode = mac->mode;
1725
1726         ratr_value |= EF2BYTE((*(u16 *) (p_mcsrate))) << 12;
1727
1728         switch (wirelessmode) {
1729         case WIRELESS_MODE_B:
1730                 if (ratr_value & 0x0000000c)
1731                         ratr_value &= 0x0000000d;
1732                 else
1733                         ratr_value &= 0x0000000f;
1734                 break;
1735         case WIRELESS_MODE_G:
1736                 ratr_value &= 0x00000FF5;
1737                 break;
1738         case WIRELESS_MODE_N_24G:
1739         case WIRELESS_MODE_N_5G:
1740                 b_nmode = 1;
1741                 if (mimo_ps == 0) {
1742                         ratr_value &= 0x0007F005;
1743                 } else {
1744                         u32 ratr_mask;
1745
1746                         if (get_rf_type(rtlphy) == RF_1T2R ||
1747                             get_rf_type(rtlphy) == RF_1T1R)
1748                                 ratr_mask = 0x000ff005;
1749                         else
1750                                 ratr_mask = 0x0f0ff005;
1751
1752                         ratr_value &= ratr_mask;
1753                 }
1754                 break;
1755         default:
1756                 if (rtlphy->rf_type == RF_1T2R)
1757                         ratr_value &= 0x000ff0ff;
1758                 else
1759                         ratr_value &= 0x0f0ff0ff;
1760
1761                 break;
1762         }
1763
1764         ratr_value &= 0x0FFFFFFF;
1765
1766         if (b_nmode && ((b_curtxbw_40mhz &&
1767                          b_curshortgi_40mhz) || (!b_curtxbw_40mhz &&
1768                                                  b_curshortgi_20mhz))) {
1769
1770                 ratr_value |= 0x10000000;
1771                 tmp_ratr_value = (ratr_value >> 12);
1772
1773                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1774                         if ((1 << shortgi_rate) & tmp_ratr_value)
1775                                 break;
1776                 }
1777
1778                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1779                     (shortgi_rate << 4) | (shortgi_rate);
1780         }
1781
1782         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1783
1784         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1785                  ("%x\n", rtl_read_dword(rtlpriv, REG_ARFR0)));
1786 }
1787
1788 void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
1789 {
1790         struct rtl_priv *rtlpriv = rtl_priv(hw);
1791         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1792         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1793         u32 ratr_bitmap = (u32) mac->basic_rates;
1794         u8 *p_mcsrate = mac->mcs;
1795         u8 ratr_index;
1796         u8 b_curtxbw_40mhz = mac->bw_40;
1797         u8 b_curshortgi_40mhz = mac->sgi_40;
1798         u8 b_curshortgi_20mhz = mac->sgi_20;
1799         enum wireless_mode wirelessmode = mac->mode;
1800         bool b_shortgi = false;
1801         u8 rate_mask[5];
1802         u8 macid = 0;
1803         u8 mimops = 1;
1804
1805         ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
1806         switch (wirelessmode) {
1807         case WIRELESS_MODE_B:
1808                 ratr_index = RATR_INX_WIRELESS_B;
1809                 if (ratr_bitmap & 0x0000000c)
1810                         ratr_bitmap &= 0x0000000d;
1811                 else
1812                         ratr_bitmap &= 0x0000000f;
1813                 break;
1814         case WIRELESS_MODE_G:
1815                 ratr_index = RATR_INX_WIRELESS_GB;
1816
1817                 if (rssi_level == 1)
1818                         ratr_bitmap &= 0x00000f00;
1819                 else if (rssi_level == 2)
1820                         ratr_bitmap &= 0x00000ff0;
1821                 else
1822                         ratr_bitmap &= 0x00000ff5;
1823                 break;
1824         case WIRELESS_MODE_A:
1825                 ratr_index = RATR_INX_WIRELESS_A;
1826                 ratr_bitmap &= 0x00000ff0;
1827                 break;
1828         case WIRELESS_MODE_N_24G:
1829         case WIRELESS_MODE_N_5G:
1830                 ratr_index = RATR_INX_WIRELESS_NGB;
1831
1832                 if (mimops == 0) {
1833                         if (rssi_level == 1)
1834                                 ratr_bitmap &= 0x00070000;
1835                         else if (rssi_level == 2)
1836                                 ratr_bitmap &= 0x0007f000;
1837                         else
1838                                 ratr_bitmap &= 0x0007f005;
1839                 } else {
1840                         if (rtlphy->rf_type == RF_1T2R ||
1841                             rtlphy->rf_type == RF_1T1R) {
1842                                 if (b_curtxbw_40mhz) {
1843                                         if (rssi_level == 1)
1844                                                 ratr_bitmap &= 0x000f0000;
1845                                         else if (rssi_level == 2)
1846                                                 ratr_bitmap &= 0x000ff000;
1847                                         else
1848                                                 ratr_bitmap &= 0x000ff015;
1849                                 } else {
1850                                         if (rssi_level == 1)
1851                                                 ratr_bitmap &= 0x000f0000;
1852                                         else if (rssi_level == 2)
1853                                                 ratr_bitmap &= 0x000ff000;
1854                                         else
1855                                                 ratr_bitmap &= 0x000ff005;
1856                                 }
1857                         } else {
1858                                 if (b_curtxbw_40mhz) {
1859                                         if (rssi_level == 1)
1860                                                 ratr_bitmap &= 0x0f0f0000;
1861                                         else if (rssi_level == 2)
1862                                                 ratr_bitmap &= 0x0f0ff000;
1863                                         else
1864                                                 ratr_bitmap &= 0x0f0ff015;
1865                                 } else {
1866                                         if (rssi_level == 1)
1867                                                 ratr_bitmap &= 0x0f0f0000;
1868                                         else if (rssi_level == 2)
1869                                                 ratr_bitmap &= 0x0f0ff000;
1870                                         else
1871                                                 ratr_bitmap &= 0x0f0ff005;
1872                                 }
1873                         }
1874                 }
1875
1876                 if ((b_curtxbw_40mhz && b_curshortgi_40mhz) ||
1877                     (!b_curtxbw_40mhz && b_curshortgi_20mhz)) {
1878
1879                         if (macid == 0)
1880                                 b_shortgi = true;
1881                         else if (macid == 1)
1882                                 b_shortgi = false;
1883                 }
1884                 break;
1885         default:
1886                 ratr_index = RATR_INX_WIRELESS_NGB;
1887
1888                 if (rtlphy->rf_type == RF_1T2R)
1889                         ratr_bitmap &= 0x000ff0ff;
1890                 else
1891                         ratr_bitmap &= 0x0f0ff0ff;
1892                 break;
1893         }
1894         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
1895                  ("ratr_bitmap :%x\n", ratr_bitmap));
1896         *(u32 *)&rate_mask = EF4BYTE((ratr_bitmap & 0x0fffffff) |
1897                                        (ratr_index << 28));
1898         rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80;
1899         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, ("Rate_index:%x, "
1900                                                  "ratr_val:%x, %x:%x:%x:%x:%x\n",
1901                                                  ratr_index, ratr_bitmap,
1902                                                  rate_mask[0], rate_mask[1],
1903                                                  rate_mask[2], rate_mask[3],
1904                                                  rate_mask[4]));
1905         rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
1906 }
1907
1908 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
1909 {
1910         struct rtl_priv *rtlpriv = rtl_priv(hw);
1911         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1912         u16 sifs_timer;
1913
1914         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
1915                                       (u8 *)&mac->slot_time);
1916         if (!mac->ht_enable)
1917                 sifs_timer = 0x0a0a;
1918         else
1919                 sifs_timer = 0x1010;
1920         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
1921 }
1922
1923 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
1924 {
1925         struct rtl_priv *rtlpriv = rtl_priv(hw);
1926         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1927         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1928         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
1929         u8 u1tmp;
1930         bool b_actuallyset = false;
1931         unsigned long flag;
1932
1933         if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
1934                 return false;
1935
1936         if (ppsc->b_swrf_processing)
1937                 return false;
1938
1939         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
1940         if (ppsc->rfchange_inprogress) {
1941                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1942                 return false;
1943         } else {
1944                 ppsc->rfchange_inprogress = true;
1945                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1946         }
1947
1948         cur_rfstate = ppsc->rfpwr_state;
1949
1950         if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
1951             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) {
1952                 rtlpriv->intf_ops->disable_aspm(hw);
1953                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
1954         }
1955
1956         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
1957                        REG_MAC_PINMUX_CFG)&~(BIT(3)));
1958
1959         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1960         e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
1961
1962         if ((ppsc->b_hwradiooff == true) && (e_rfpowerstate_toset == ERFON)) {
1963                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1964                          ("GPIOChangeRF  - HW Radio ON, RF ON\n"));
1965
1966                 e_rfpowerstate_toset = ERFON;
1967                 ppsc->b_hwradiooff = false;
1968                 b_actuallyset = true;
1969         } else if ((ppsc->b_hwradiooff == false)
1970                    && (e_rfpowerstate_toset == ERFOFF)) {
1971                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1972                          ("GPIOChangeRF  - HW Radio OFF, RF OFF\n"));
1973
1974                 e_rfpowerstate_toset = ERFOFF;
1975                 ppsc->b_hwradiooff = true;
1976                 b_actuallyset = true;
1977         }
1978
1979         if (b_actuallyset) {
1980                 if (e_rfpowerstate_toset == ERFON) {
1981                         if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
1982                             RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM)) {
1983                                 rtlpriv->intf_ops->disable_aspm(hw);
1984                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
1985                         }
1986                 }
1987
1988                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
1989                 ppsc->rfchange_inprogress = false;
1990                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
1991
1992                 if (e_rfpowerstate_toset == ERFOFF) {
1993                         if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) {
1994                                 rtlpriv->intf_ops->enable_aspm(hw);
1995                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
1996                         }
1997                 }
1998
1999         } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2000                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2001                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2002
2003                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) {
2004                         rtlpriv->intf_ops->enable_aspm(hw);
2005                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2006                 }
2007
2008                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2009                 ppsc->rfchange_inprogress = false;
2010                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2011         } else {
2012                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2013                 ppsc->rfchange_inprogress = false;
2014                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2015         }
2016
2017         *valid = 1;
2018         return !ppsc->b_hwradiooff;
2019
2020 }
2021
2022 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2023                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2024                      bool is_wepkey, bool clear_all)
2025 {
2026         struct rtl_priv *rtlpriv = rtl_priv(hw);
2027         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2028         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2029         u8 *macaddr = p_macaddr;
2030         u32 entry_id = 0;
2031         bool is_pairwise = false;
2032
2033         static u8 cam_const_addr[4][6] = {
2034                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2035                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2036                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2037                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2038         };
2039         static u8 cam_const_broad[] = {
2040                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2041         };
2042
2043         if (clear_all) {
2044                 u8 idx = 0;
2045                 u8 cam_offset = 0;
2046                 u8 clear_number = 5;
2047
2048                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, ("clear_all\n"));
2049
2050                 for (idx = 0; idx < clear_number; idx++) {
2051                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2052                         rtl_cam_empty_entry(hw, cam_offset + idx);
2053
2054                         if (idx < 5) {
2055                                 memset(rtlpriv->sec.key_buf[idx], 0,
2056                                        MAX_KEY_LEN);
2057                                 rtlpriv->sec.key_len[idx] = 0;
2058                         }
2059                 }
2060
2061         } else {
2062                 switch (enc_algo) {
2063                 case WEP40_ENCRYPTION:
2064                         enc_algo = CAM_WEP40;
2065                         break;
2066                 case WEP104_ENCRYPTION:
2067                         enc_algo = CAM_WEP104;
2068                         break;
2069                 case TKIP_ENCRYPTION:
2070                         enc_algo = CAM_TKIP;
2071                         break;
2072                 case AESCCMP_ENCRYPTION:
2073                         enc_algo = CAM_AES;
2074                         break;
2075                 default:
2076                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, ("switch case "
2077                                         "not process\n"));
2078                         enc_algo = CAM_TKIP;
2079                         break;
2080                 }
2081
2082                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2083                         macaddr = cam_const_addr[key_index];
2084                         entry_id = key_index;
2085                 } else {
2086                         if (is_group) {
2087                                 macaddr = cam_const_broad;
2088                                 entry_id = key_index;
2089                         } else {
2090                                 key_index = PAIRWISE_KEYIDX;
2091                                 entry_id = CAM_PAIRWISE_KEY_POSITION;
2092                                 is_pairwise = true;
2093                         }
2094                 }
2095
2096                 if (rtlpriv->sec.key_len[key_index] == 0) {
2097                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2098                                  ("delete one entry\n"));
2099                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2100                 } else {
2101                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2102                                  ("The insert KEY length is %d\n",
2103                                   rtlpriv->sec.key_len[PAIRWISE_KEYIDX]));
2104                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2105                                  ("The insert KEY  is %x %x\n",
2106                                   rtlpriv->sec.key_buf[0][0],
2107                                   rtlpriv->sec.key_buf[0][1]));
2108
2109                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2110                                  ("add one entry\n"));
2111                         if (is_pairwise) {
2112                                 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2113                                               "Pairwiase Key content :",
2114                                               rtlpriv->sec.pairwise_key,
2115                                               rtlpriv->sec.
2116                                               key_len[PAIRWISE_KEYIDX]);
2117
2118                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2119                                          ("set Pairwiase key\n"));
2120
2121                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2122                                                       entry_id, enc_algo,
2123                                                       CAM_CONFIG_NO_USEDK,
2124                                                       rtlpriv->sec.
2125                                                       key_buf[key_index]);
2126                         } else {
2127                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2128                                          ("set group key\n"));
2129
2130                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2131                                         rtl_cam_add_one_entry(hw,
2132                                                 rtlefuse->dev_addr,
2133                                                 PAIRWISE_KEYIDX,
2134                                                 CAM_PAIRWISE_KEY_POSITION,
2135                                                 enc_algo,
2136                                                 CAM_CONFIG_NO_USEDK,
2137                                                 rtlpriv->sec.key_buf
2138                                                 [entry_id]);
2139                                 }
2140
2141                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2142                                                 entry_id, enc_algo,
2143                                                 CAM_CONFIG_NO_USEDK,
2144                                                 rtlpriv->sec.key_buf[entry_id]);
2145                         }
2146
2147                 }
2148         }
2149 }