drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2004 - 2009 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2800pci
  23         Abstract: rt2800pci device specific routines.
  24         Supported chipsets: RT2800E & RT2800ED.
  25  */
  26
  27 #include <linux/crc-ccitt.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/eeprom_93cx6.h>
  36
  37 #include "rt2x00.h"
  38 #include "rt2x00pci.h"
  39 #include "rt2x00soc.h"
  40 #include "rt2800pci.h"
  41
  42 #ifdef CONFIG_RT2800PCI_PCI_MODULE
  43 #define CONFIG_RT2800PCI_PCI
  44 #endif
  45
  46 #ifdef CONFIG_RT2800PCI_WISOC_MODULE
  47 #define CONFIG_RT2800PCI_WISOC
  48 #endif
  49
  50 /*
  51  * Allow hardware encryption to be disabled.
  52  */
  53 static int modparam_nohwcrypt = 1;
  54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  56
  57 /*
  58  * Register access.
  59  * All access to the CSR registers will go through the methods
  60  * rt2800_register_read and rt2800_register_write.
  61  * BBP and RF register require indirect register access,
  62  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  63  * These indirect registers work with busy bits,
  64  * and we will try maximal REGISTER_BUSY_COUNT times to access
  65  * the register while taking a REGISTER_BUSY_DELAY us delay
  66  * between each attampt. When the busy bit is still set at that time,
  67  * the access attempt is considered to have failed,
  68  * and we will print an error.
  69  * The _lock versions must be used if you already hold the csr_mutex
  70  */
  71 #define WAIT_FOR_BBP(__dev, __reg) \
  72         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  73 #define WAIT_FOR_RFCSR(__dev, __reg) \
  74         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  75 #define WAIT_FOR_RF(__dev, __reg) \
  76         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  77 #define WAIT_FOR_MCU(__dev, __reg) \
  78         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  79                             H2M_MAILBOX_CSR_OWNER, (__reg))
  80
  81 static void rt2800pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  82                                 const unsigned int word, const u8 value)
  83 {
  84         u32 reg;
  85
  86         mutex_lock(&rt2x00dev->csr_mutex);
  87
  88         /*
  89          * Wait until the BBP becomes available, afterwards we
  90          * can safely write the new data into the register.
  91          */
  92         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
  93                 reg = 0;
  94                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
  95                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
  96                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
  97                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
  98                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
  99
 100                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 101         }
 102
 103         mutex_unlock(&rt2x00dev->csr_mutex);
 104 }
 105
 106 static void rt2800pci_bbp_read(struct rt2x00_dev *rt2x00dev,
 107                                const unsigned int word, u8 *value)
 108 {
 109         u32 reg;
 110
 111         mutex_lock(&rt2x00dev->csr_mutex);
 112
 113         /*
 114          * Wait until the BBP becomes available, afterwards we
 115          * can safely write the read request into the register.
 116          * After the data has been written, we wait until hardware
 117          * returns the correct value, if at any time the register
 118          * doesn't become available in time, reg will be 0xffffffff
 119          * which means we return 0xff to the caller.
 120          */
 121         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 122                 reg = 0;
 123                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 124                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 125                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 126                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 127
 128                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 129
 130                 WAIT_FOR_BBP(rt2x00dev, &reg);
 131         }
 132
 133         *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 134
 135         mutex_unlock(&rt2x00dev->csr_mutex);
 136 }
 137
 138 static inline void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
 139                                     const unsigned int word, const u8 value)
 140 {
 141         rt2800pci_bbp_write(rt2x00dev, word, value);
 142 }
 143
 144 static inline void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
 145                                    const unsigned int word, u8 *value)
 146 {
 147         rt2800pci_bbp_read(rt2x00dev, word, value);
 148 }
 149
 150 static void rt2800pci_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 151                                   const unsigned int word, const u8 value)
 152 {
 153         u32 reg;
 154
 155         mutex_lock(&rt2x00dev->csr_mutex);
 156
 157         /*
 158          * Wait until the RFCSR becomes available, afterwards we
 159          * can safely write the new data into the register.
 160          */
 161         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 162                 reg = 0;
 163                 rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 164                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 165                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 166                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 167
 168                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 169         }
 170
 171         mutex_unlock(&rt2x00dev->csr_mutex);
 172 }
 173
 174 static void rt2800pci_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 175                                  const unsigned int word, u8 *value)
 176 {
 177         u32 reg;
 178
 179         mutex_lock(&rt2x00dev->csr_mutex);
 180
 181         /*
 182          * Wait until the RFCSR becomes available, afterwards we
 183          * can safely write the read request into the register.
 184          * After the data has been written, we wait until hardware
 185          * returns the correct value, if at any time the register
 186          * doesn't become available in time, reg will be 0xffffffff
 187          * which means we return 0xff to the caller.
 188          */
 189         if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 190                 reg = 0;
 191                 rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 192                 rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 193                 rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 194
 195                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 196
 197                 WAIT_FOR_RFCSR(rt2x00dev, &reg);
 198         }
 199
 200         *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 201
 202         mutex_unlock(&rt2x00dev->csr_mutex);
 203 }
 204
 205 static inline void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 206                                       const unsigned int word, const u8 value)
 207 {
 208         rt2800pci_rfcsr_write(rt2x00dev, word, value);
 209 }
 210
 211 static inline void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 212                                      const unsigned int word, u8 *value)
 213 {
 214         rt2800pci_rfcsr_read(rt2x00dev, word, value);
 215 }
 216
 217 static void rt2800pci_rf_write(struct rt2x00_dev *rt2x00dev,
 218                                const unsigned int word, const u32 value)
 219 {
 220         u32 reg;
 221
 222         mutex_lock(&rt2x00dev->csr_mutex);
 223
 224         /*
 225          * Wait until the RF becomes available, afterwards we
 226          * can safely write the new data into the register.
 227          */
 228         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 229                 reg = 0;
 230                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 231                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 232                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 233                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 234
 235                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 236                 rt2x00_rf_write(rt2x00dev, word, value);
 237         }
 238
 239         mutex_unlock(&rt2x00dev->csr_mutex);
 240 }
 241
 242 static inline void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 243                                    const unsigned int word, const u32 value)
 244 {
 245         rt2800pci_rf_write(rt2x00dev, word, value);
 246 }
 247
 248 static void rt2800pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 249                                   const u8 command, const u8 token,
 250                                   const u8 arg0, const u8 arg1)
 251 {
 252         u32 reg;
 253
 254         /*
 255          * RT2880 and RT3052 don't support MCU requests.
 256          */
 257         if (rt2x00_rt(&rt2x00dev->chip, RT2880) ||
 258             rt2x00_rt(&rt2x00dev->chip, RT3052))
 259                 return;
 260
 261         mutex_lock(&rt2x00dev->csr_mutex);
 262
 263         /*
 264          * Wait until the MCU becomes available, afterwards we
 265          * can safely write the new data into the register.
 266          */
 267         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 268                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 269                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 270                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 271                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 272                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 273
 274                 reg = 0;
 275                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 276                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 277         }
 278
 279         mutex_unlock(&rt2x00dev->csr_mutex);
 280 }
 281
 282 static inline void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 283                                       const u8 command, const u8 token,
 284                                       const u8 arg0, const u8 arg1)
 285 {
 286         rt2800pci_mcu_request(rt2x00dev, command, token, arg0, arg1);
 287 }
 288
 289 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
 290 {
 291         unsigned int i;
 292         u32 reg;
 293
 294         for (i = 0; i < 200; i++) {
 295                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
 296
 297                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
 298                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
 299                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
 300                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
 301                         break;
 302
 303                 udelay(REGISTER_BUSY_DELAY);
 304         }
 305
 306         if (i == 200)
 307                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
 308
 309         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
 310         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
 311 }
 312
 313 #ifdef CONFIG_RT2800PCI_WISOC
 314 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
 315 {
 316         u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
 317
 318         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
 319 }
 320 #else
 321 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
 322 {
 323 }
 324 #endif /* CONFIG_RT2800PCI_WISOC */
 325
 326 #ifdef CONFIG_RT2800PCI_PCI
 327 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 328 {
 329         struct rt2x00_dev *rt2x00dev = eeprom->data;
 330         u32 reg;
 331
 332         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 333
 334         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 335         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 336         eeprom->reg_data_clock =
 337             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 338         eeprom->reg_chip_select =
 339             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 340 }
 341
 342 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 343 {
 344         struct rt2x00_dev *rt2x00dev = eeprom->data;
 345         u32 reg = 0;
 346
 347         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 348         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 349         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 350                            !!eeprom->reg_data_clock);
 351         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 352                            !!eeprom->reg_chip_select);
 353
 354         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
 355 }
 356
 357 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 358 {
 359         struct eeprom_93cx6 eeprom;
 360         u32 reg;
 361
 362         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 363
 364         eeprom.data = rt2x00dev;
 365         eeprom.register_read = rt2800pci_eepromregister_read;
 366         eeprom.register_write = rt2800pci_eepromregister_write;
 367         eeprom.width = !rt2x00_get_field32(reg, E2PROM_CSR_TYPE) ?
 368             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
 369         eeprom.reg_data_in = 0;
 370         eeprom.reg_data_out = 0;
 371         eeprom.reg_data_clock = 0;
 372         eeprom.reg_chip_select = 0;
 373
 374         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 375                                EEPROM_SIZE / sizeof(u16));
 376 }
 377
 378 static void rt2800pci_efuse_read(struct rt2x00_dev *rt2x00dev,
 379                                  unsigned int i)
 380 {
 381         u32 reg;
 382
 383         rt2800_register_read(rt2x00dev, EFUSE_CTRL, &reg);
 384         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
 385         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
 386         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
 387         rt2800_register_write(rt2x00dev, EFUSE_CTRL, reg);
 388
 389         /* Wait until the EEPROM has been loaded */
 390         rt2800_regbusy_read(rt2x00dev, EFUSE_CTRL, EFUSE_CTRL_KICK, &reg);
 391
 392         /* Apparently the data is read from end to start */
 393         rt2800_register_read(rt2x00dev, EFUSE_DATA3,
 394                                 (u32 *)&rt2x00dev->eeprom[i]);
 395         rt2800_register_read(rt2x00dev, EFUSE_DATA2,
 396                                 (u32 *)&rt2x00dev->eeprom[i + 2]);
 397         rt2800_register_read(rt2x00dev, EFUSE_DATA1,
 398                                 (u32 *)&rt2x00dev->eeprom[i + 4]);
 399         rt2800_register_read(rt2x00dev, EFUSE_DATA0,
 400                                 (u32 *)&rt2x00dev->eeprom[i + 6]);
 401 }
 402
 403 static void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 404 {
 405         unsigned int i;
 406
 407         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
 408                 rt2800pci_efuse_read(rt2x00dev, i);
 409 }
 410 #else
 411 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 412 {
 413 }
 414
 415 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 416 {
 417 }
 418 #endif /* CONFIG_RT2800PCI_PCI */
 419
 420 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 421 static const struct rt2x00debug rt2800pci_rt2x00debug = {
 422         .owner  = THIS_MODULE,
 423         .csr    = {
 424                 .read           = rt2800_register_read,
 425                 .write          = rt2800_register_write,
 426                 .flags          = RT2X00DEBUGFS_OFFSET,
 427                 .word_base      = CSR_REG_BASE,
 428                 .word_size      = sizeof(u32),
 429                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 430         },
 431         .eeprom = {
 432                 .read           = rt2x00_eeprom_read,
 433                 .write          = rt2x00_eeprom_write,
 434                 .word_base      = EEPROM_BASE,
 435                 .word_size      = sizeof(u16),
 436                 .word_count     = EEPROM_SIZE / sizeof(u16),
 437         },
 438         .bbp    = {
 439                 .read           = rt2800_bbp_read,
 440                 .write          = rt2800_bbp_write,
 441                 .word_base      = BBP_BASE,
 442                 .word_size      = sizeof(u8),
 443                 .word_count     = BBP_SIZE / sizeof(u8),
 444         },
 445         .rf     = {
 446                 .read           = rt2x00_rf_read,
 447                 .write          = rt2800_rf_write,
 448                 .word_base      = RF_BASE,
 449                 .word_size      = sizeof(u32),
 450                 .word_count     = RF_SIZE / sizeof(u32),
 451         },
 452 };
 453 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 454
 455 static int rt2800pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 456 {
 457         u32 reg;
 458
 459         rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, &reg);
 460         return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
 461 }
 462
 463 #ifdef CONFIG_RT2X00_LIB_LEDS
 464 static void rt2800pci_brightness_set(struct led_classdev *led_cdev,
 465                                      enum led_brightness brightness)
 466 {
 467         struct rt2x00_led *led =
 468             container_of(led_cdev, struct rt2x00_led, led_dev);
 469         unsigned int enabled = brightness != LED_OFF;
 470         unsigned int bg_mode =
 471             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 472         unsigned int polarity =
 473                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 474                                    EEPROM_FREQ_LED_POLARITY);
 475         unsigned int ledmode =
 476                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
 477                                    EEPROM_FREQ_LED_MODE);
 478
 479         if (led->type == LED_TYPE_RADIO) {
 480                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 481                                       enabled ? 0x20 : 0);
 482         } else if (led->type == LED_TYPE_ASSOC) {
 483                 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
 484                                       enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
 485         } else if (led->type == LED_TYPE_QUALITY) {
 486                 /*
 487                  * The brightness is divided into 6 levels (0 - 5),
 488                  * The specs tell us the following levels:
 489                  *      0, 1 ,3, 7, 15, 31
 490                  * to determine the level in a simple way we can simply
 491                  * work with bitshifting:
 492                  *      (1 << level) - 1
 493                  */
 494                 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 495                                       (1 << brightness / (LED_FULL / 6)) - 1,
 496                                       polarity);
 497         }
 498 }
 499
 500 static int rt2800pci_blink_set(struct led_classdev *led_cdev,
 501                                unsigned long *delay_on,
 502                                unsigned long *delay_off)
 503 {
 504         struct rt2x00_led *led =
 505             container_of(led_cdev, struct rt2x00_led, led_dev);
 506         u32 reg;
 507
 508         rt2800_register_read(led->rt2x00dev, LED_CFG, &reg);
 509         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, *delay_on);
 510         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, *delay_off);
 511         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
 512         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
 513         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 12);
 514         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
 515         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
 516         rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
 517
 518         return 0;
 519 }
 520
 521 static void rt2800pci_init_led(struct rt2x00_dev *rt2x00dev,
 522                                struct rt2x00_led *led,
 523                                enum led_type type)
 524 {
 525         led->rt2x00dev = rt2x00dev;
 526         led->type = type;
 527         led->led_dev.brightness_set = rt2800pci_brightness_set;
 528         led->led_dev.blink_set = rt2800pci_blink_set;
 529         led->flags = LED_INITIALIZED;
 530 }
 531 #endif /* CONFIG_RT2X00_LIB_LEDS */
 532
 533 /*
 534  * Configuration handlers.
 535  */
 536 static void rt2800pci_config_wcid_attr(struct rt2x00_dev *rt2x00dev,
 537                                        struct rt2x00lib_crypto *crypto,
 538                                        struct ieee80211_key_conf *key)
 539 {
 540         struct mac_wcid_entry wcid_entry;
 541         struct mac_iveiv_entry iveiv_entry;
 542         u32 offset;
 543         u32 reg;
 544
 545         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
 546
 547         rt2800_register_read(rt2x00dev, offset, &reg);
 548         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
 549                            !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
 550         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
 551                            (crypto->cmd == SET_KEY) * crypto->cipher);
 552         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX,
 553                            (crypto->cmd == SET_KEY) * crypto->bssidx);
 554         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
 555         rt2800_register_write(rt2x00dev, offset, reg);
 556
 557         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
 558
 559         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
 560         if ((crypto->cipher == CIPHER_TKIP) ||
 561             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
 562             (crypto->cipher == CIPHER_AES))
 563                 iveiv_entry.iv[3] |= 0x20;
 564         iveiv_entry.iv[3] |= key->keyidx << 6;
 565         rt2800_register_multiwrite(rt2x00dev, offset,
 566                                       &iveiv_entry, sizeof(iveiv_entry));
 567
 568         offset = MAC_WCID_ENTRY(key->hw_key_idx);
 569
 570         memset(&wcid_entry, 0, sizeof(wcid_entry));
 571         if (crypto->cmd == SET_KEY)
 572                 memcpy(&wcid_entry, crypto->address, ETH_ALEN);
 573         rt2800_register_multiwrite(rt2x00dev, offset,
 574                                       &wcid_entry, sizeof(wcid_entry));
 575 }
 576
 577 static int rt2800pci_config_shared_key(struct rt2x00_dev *rt2x00dev,
 578                                        struct rt2x00lib_crypto *crypto,
 579                                        struct ieee80211_key_conf *key)
 580 {
 581         struct hw_key_entry key_entry;
 582         struct rt2x00_field32 field;
 583         u32 offset;
 584         u32 reg;
 585
 586         if (crypto->cmd == SET_KEY) {
 587                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
 588
 589                 memcpy(key_entry.key, crypto->key,
 590                        sizeof(key_entry.key));
 591                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 592                        sizeof(key_entry.tx_mic));
 593                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 594                        sizeof(key_entry.rx_mic));
 595
 596                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
 597                 rt2800_register_multiwrite(rt2x00dev, offset,
 598                                               &key_entry, sizeof(key_entry));
 599         }
 600
 601         /*
 602          * The cipher types are stored over multiple registers
 603          * starting with SHARED_KEY_MODE_BASE each word will have
 604          * 32 bits and contains the cipher types for 2 bssidx each.
 605          * Using the correct defines correctly will cause overhead,
 606          * so just calculate the correct offset.
 607          */
 608         field.bit_offset = 4 * (key->hw_key_idx % 8);
 609         field.bit_mask = 0x7 << field.bit_offset;
 610
 611         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
 612
 613         rt2800_register_read(rt2x00dev, offset, &reg);
 614         rt2x00_set_field32(&reg, field,
 615                            (crypto->cmd == SET_KEY) * crypto->cipher);
 616         rt2800_register_write(rt2x00dev, offset, reg);
 617
 618         /*
 619          * Update WCID information
 620          */
 621         rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
 622
 623         return 0;
 624 }
 625
 626 static int rt2800pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
 627                                          struct rt2x00lib_crypto *crypto,
 628                                          struct ieee80211_key_conf *key)
 629 {
 630         struct hw_key_entry key_entry;
 631         u32 offset;
 632
 633         if (crypto->cmd == SET_KEY) {
 634                 /*
 635                  * 1 pairwise key is possible per AID, this means that the AID
 636                  * equals our hw_key_idx. Make sure the WCID starts _after_ the
 637                  * last possible shared key entry.
 638                  */
 639                 if (crypto->aid > (256 - 32))
 640                         return -ENOSPC;
 641
 642                 key->hw_key_idx = 32 + crypto->aid;
 643
 644
 645                 memcpy(key_entry.key, crypto->key,
 646                        sizeof(key_entry.key));
 647                 memcpy(key_entry.tx_mic, crypto->tx_mic,
 648                        sizeof(key_entry.tx_mic));
 649                 memcpy(key_entry.rx_mic, crypto->rx_mic,
 650                        sizeof(key_entry.rx_mic));
 651
 652                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
 653                 rt2800_register_multiwrite(rt2x00dev, offset,
 654                                               &key_entry, sizeof(key_entry));
 655         }
 656
 657         /*
 658          * Update WCID information
 659          */
 660         rt2800pci_config_wcid_attr(rt2x00dev, crypto, key);
 661
 662         return 0;
 663 }
 664
 665 static void rt2800pci_config_filter(struct rt2x00_dev *rt2x00dev,
 666                                     const unsigned int filter_flags)
 667 {
 668         u32 reg;
 669
 670         /*
 671          * Start configuration steps.
 672          * Note that the version error will always be dropped
 673          * and broadcast frames will always be accepted since
 674          * there is no filter for it at this time.
 675          */
 676         rt2800_register_read(rt2x00dev, RX_FILTER_CFG, &reg);
 677         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
 678                            !(filter_flags & FIF_FCSFAIL));
 679         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
 680                            !(filter_flags & FIF_PLCPFAIL));
 681         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
 682                            !(filter_flags & FIF_PROMISC_IN_BSS));
 683         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
 684         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
 685         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
 686                            !(filter_flags & FIF_ALLMULTI));
 687         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
 688         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
 689         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
 690                            !(filter_flags & FIF_CONTROL));
 691         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
 692                            !(filter_flags & FIF_CONTROL));
 693         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
 694                            !(filter_flags & FIF_CONTROL));
 695         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
 696                            !(filter_flags & FIF_CONTROL));
 697         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
 698                            !(filter_flags & FIF_CONTROL));
 699         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
 700                            !(filter_flags & FIF_PSPOLL));
 701         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 1);
 702         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR, 0);
 703         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
 704                            !(filter_flags & FIF_CONTROL));
 705         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
 706 }
 707
 708 static void rt2800pci_config_intf(struct rt2x00_dev *rt2x00dev,
 709                                   struct rt2x00_intf *intf,
 710                                   struct rt2x00intf_conf *conf,
 711                                   const unsigned int flags)
 712 {
 713         unsigned int beacon_base;
 714         u32 reg;
 715
 716         if (flags & CONFIG_UPDATE_TYPE) {
 717                 /*
 718                  * Clear current synchronisation setup.
 719                  * For the Beacon base registers we only need to clear
 720                  * the first byte since that byte contains the VALID and OWNER
 721                  * bits which (when set to 0) will invalidate the entire beacon.
 722                  */
 723                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 724                 rt2800_register_write(rt2x00dev, beacon_base, 0);
 725
 726                 /*
 727                  * Enable synchronisation.
 728                  */
 729                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 730                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 731                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
 732                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 733                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 734         }
 735
 736         if (flags & CONFIG_UPDATE_MAC) {
 737                 reg = le32_to_cpu(conf->mac[1]);
 738                 rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
 739                 conf->mac[1] = cpu_to_le32(reg);
 740
 741                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
 742                                               conf->mac, sizeof(conf->mac));
 743         }
 744
 745         if (flags & CONFIG_UPDATE_BSSID) {
 746                 reg = le32_to_cpu(conf->bssid[1]);
 747                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 0);
 748                 rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
 749                 conf->bssid[1] = cpu_to_le32(reg);
 750
 751                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
 752                                               conf->bssid, sizeof(conf->bssid));
 753         }
 754 }
 755
 756 static void rt2800pci_config_erp(struct rt2x00_dev *rt2x00dev,
 757                                  struct rt2x00lib_erp *erp)
 758 {
 759         u32 reg;
 760
 761         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
 762         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 0x20);
 763         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
 764
 765         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
 766         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY,
 767                            !!erp->short_preamble);
 768         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
 769                            !!erp->short_preamble);
 770         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
 771
 772         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
 773         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
 774                            erp->cts_protection ? 2 : 0);
 775         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
 776
 777         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
 778                                  erp->basic_rates);
 779         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
 780
 781         rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, &reg);
 782         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, erp->slot_time);
 783         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
 784         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
 785
 786         rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, &reg);
 787         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, erp->sifs);
 788         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, erp->sifs);
 789         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
 790         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
 791         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
 792         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
 793
 794         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 795         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 796                            erp->beacon_int * 16);
 797         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 798 }
 799
 800 static void rt2800pci_config_ant(struct rt2x00_dev *rt2x00dev,
 801                                  struct antenna_setup *ant)
 802 {
 803         u8 r1;
 804         u8 r3;
 805
 806         rt2800_bbp_read(rt2x00dev, 1, &r1);
 807         rt2800_bbp_read(rt2x00dev, 3, &r3);
 808
 809         /*
 810          * Configure the TX antenna.
 811          */
 812         switch ((int)ant->tx) {
 813         case 1:
 814                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
 815                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 816                 break;
 817         case 2:
 818                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
 819                 break;
 820         case 3:
 821                 /* Do nothing */
 822                 break;
 823         }
 824
 825         /*
 826          * Configure the RX antenna.
 827          */
 828         switch ((int)ant->rx) {
 829         case 1:
 830                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
 831                 break;
 832         case 2:
 833                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
 834                 break;
 835         case 3:
 836                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
 837                 break;
 838         }
 839
 840         rt2800_bbp_write(rt2x00dev, 3, r3);
 841         rt2800_bbp_write(rt2x00dev, 1, r1);
 842 }
 843
 844 static void rt2800pci_config_lna_gain(struct rt2x00_dev *rt2x00dev,
 845                                       struct rt2x00lib_conf *libconf)
 846 {
 847         u16 eeprom;
 848         short lna_gain;
 849
 850         if (libconf->rf.channel <= 14) {
 851                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 852                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
 853         } else if (libconf->rf.channel <= 64) {
 854                 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
 855                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
 856         } else if (libconf->rf.channel <= 128) {
 857                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
 858                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
 859         } else {
 860                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
 861                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
 862         }
 863
 864         rt2x00dev->lna_gain = lna_gain;
 865 }
 866
 867 static void rt2800pci_config_channel_rt2x(struct rt2x00_dev *rt2x00dev,
 868                                           struct ieee80211_conf *conf,
 869                                           struct rf_channel *rf,
 870                                           struct channel_info *info)
 871 {
 872         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 873
 874         if (rt2x00dev->default_ant.tx == 1)
 875                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
 876
 877         if (rt2x00dev->default_ant.rx == 1) {
 878                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
 879                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 880         } else if (rt2x00dev->default_ant.rx == 2)
 881                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
 882
 883         if (rf->channel > 14) {
 884                 /*
 885                  * When TX power is below 0, we should increase it by 7 to
 886                  * make it a positive value (Minumum value is -7).
 887                  * However this means that values between 0 and 7 have
 888                  * double meaning, and we should set a 7DBm boost flag.
 889                  */
 890                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
 891                                    (info->tx_power1 >= 0));
 892
 893                 if (info->tx_power1 < 0)
 894                         info->tx_power1 += 7;
 895
 896                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A,
 897                                    TXPOWER_A_TO_DEV(info->tx_power1));
 898
 899                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
 900                                    (info->tx_power2 >= 0));
 901
 902                 if (info->tx_power2 < 0)
 903                         info->tx_power2 += 7;
 904
 905                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A,
 906                                    TXPOWER_A_TO_DEV(info->tx_power2));
 907         } else {
 908                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G,
 909                                    TXPOWER_G_TO_DEV(info->tx_power1));
 910                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G,
 911                                    TXPOWER_G_TO_DEV(info->tx_power2));
 912         }
 913
 914         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
 915
 916         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 917         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 918         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 919         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 920
 921         udelay(200);
 922
 923         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 924         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 925         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 926         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 927
 928         udelay(200);
 929
 930         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
 931         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
 932         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 933         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
 934 }
 935
 936 static void rt2800pci_config_channel_rt3x(struct rt2x00_dev *rt2x00dev,
 937                                           struct ieee80211_conf *conf,
 938                                           struct rf_channel *rf,
 939                                           struct channel_info *info)
 940 {
 941         u8 rfcsr;
 942
 943         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
 944         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf3);
 945
 946         rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
 947         rt2x00_set_field8(&rfcsr, RFCSR6_R, rf->rf2);
 948         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
 949
 950         rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
 951         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
 952                           TXPOWER_G_TO_DEV(info->tx_power1));
 953         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
 954
 955         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 956         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
 957         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 958
 959         rt2800_rfcsr_write(rt2x00dev, 24,
 960                               rt2x00dev->calibration[conf_is_ht40(conf)]);
 961
 962         rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
 963         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
 964         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
 965 }
 966
 967 static void rt2800pci_config_channel(struct rt2x00_dev *rt2x00dev,
 968                                      struct ieee80211_conf *conf,
 969                                      struct rf_channel *rf,
 970                                      struct channel_info *info)
 971 {
 972         u32 reg;
 973         unsigned int tx_pin;
 974         u8 bbp;
 975
 976         if (rt2x00_rev(&rt2x00dev->chip) != RT3070_VERSION)
 977                 rt2800pci_config_channel_rt2x(rt2x00dev, conf, rf, info);
 978         else
 979                 rt2800pci_config_channel_rt3x(rt2x00dev, conf, rf, info);
 980
 981         /*
 982          * Change BBP settings
 983          */
 984         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
 985         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
 986         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
 987         rt2800_bbp_write(rt2x00dev, 86, 0);
 988
 989         if (rf->channel <= 14) {
 990                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 991                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
 992                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
 993                 } else {
 994                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
 995                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
 996                 }
 997         } else {
 998                 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
 999
1000                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1001                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
1002                 else
1003                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
1004         }
1005
1006         rt2800_register_read(rt2x00dev, TX_BAND_CFG, &reg);
1007         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_PLUS, conf_is_ht40_plus(conf));
1008         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
1009         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
1010         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
1011
1012         tx_pin = 0;
1013
1014         /* Turn on unused PA or LNA when not using 1T or 1R */
1015         if (rt2x00dev->default_ant.tx != 1) {
1016                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
1017                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
1018         }
1019
1020         /* Turn on unused PA or LNA when not using 1T or 1R */
1021         if (rt2x00dev->default_ant.rx != 1) {
1022                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
1023                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
1024         }
1025
1026         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
1027         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
1028         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
1029         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
1030         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, rf->channel <= 14);
1031         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
1032
1033         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
1034
1035         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1036         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
1037         rt2800_bbp_write(rt2x00dev, 4, bbp);
1038
1039         rt2800_bbp_read(rt2x00dev, 3, &bbp);
1040         rt2x00_set_field8(&bbp, BBP3_HT40_PLUS, conf_is_ht40_plus(conf));
1041         rt2800_bbp_write(rt2x00dev, 3, bbp);
1042
1043         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1044                 if (conf_is_ht40(conf)) {
1045                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
1046                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1047                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
1048                 } else {
1049                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
1050                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
1051                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
1052                 }
1053         }
1054
1055         msleep(1);
1056 }
1057
1058 static void rt2800pci_config_txpower(struct rt2x00_dev *rt2x00dev,
1059                                      const int txpower)
1060 {
1061         u32 reg;
1062         u32 value = TXPOWER_G_TO_DEV(txpower);
1063         u8 r1;
1064
1065         rt2800_bbp_read(rt2x00dev, 1, &r1);
1066         rt2x00_set_field8(&reg, BBP1_TX_POWER, 0);
1067         rt2800_bbp_write(rt2x00dev, 1, r1);
1068
1069         rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, &reg);
1070         rt2x00_set_field32(&reg, TX_PWR_CFG_0_1MBS, value);
1071         rt2x00_set_field32(&reg, TX_PWR_CFG_0_2MBS, value);
1072         rt2x00_set_field32(&reg, TX_PWR_CFG_0_55MBS, value);
1073         rt2x00_set_field32(&reg, TX_PWR_CFG_0_11MBS, value);
1074         rt2x00_set_field32(&reg, TX_PWR_CFG_0_6MBS, value);
1075         rt2x00_set_field32(&reg, TX_PWR_CFG_0_9MBS, value);
1076         rt2x00_set_field32(&reg, TX_PWR_CFG_0_12MBS, value);
1077         rt2x00_set_field32(&reg, TX_PWR_CFG_0_18MBS, value);
1078         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, reg);
1079
1080         rt2800_register_read(rt2x00dev, TX_PWR_CFG_1, &reg);
1081         rt2x00_set_field32(&reg, TX_PWR_CFG_1_24MBS, value);
1082         rt2x00_set_field32(&reg, TX_PWR_CFG_1_36MBS, value);
1083         rt2x00_set_field32(&reg, TX_PWR_CFG_1_48MBS, value);
1084         rt2x00_set_field32(&reg, TX_PWR_CFG_1_54MBS, value);
1085         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS0, value);
1086         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS1, value);
1087         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS2, value);
1088         rt2x00_set_field32(&reg, TX_PWR_CFG_1_MCS3, value);
1089         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, reg);
1090
1091         rt2800_register_read(rt2x00dev, TX_PWR_CFG_2, &reg);
1092         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS4, value);
1093         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS5, value);
1094         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS6, value);
1095         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS7, value);
1096         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS8, value);
1097         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS9, value);
1098         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS10, value);
1099         rt2x00_set_field32(&reg, TX_PWR_CFG_2_MCS11, value);
1100         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, reg);
1101
1102         rt2800_register_read(rt2x00dev, TX_PWR_CFG_3, &reg);
1103         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS12, value);
1104         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS13, value);
1105         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS14, value);
1106         rt2x00_set_field32(&reg, TX_PWR_CFG_3_MCS15, value);
1107         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN1, value);
1108         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN2, value);
1109         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN3, value);
1110         rt2x00_set_field32(&reg, TX_PWR_CFG_3_UKNOWN4, value);
1111         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, reg);
1112
1113         rt2800_register_read(rt2x00dev, TX_PWR_CFG_4, &reg);
1114         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN5, value);
1115         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN6, value);
1116         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN7, value);
1117         rt2x00_set_field32(&reg, TX_PWR_CFG_4_UKNOWN8, value);
1118         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, reg);
1119 }
1120
1121 static void rt2800pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
1122                                          struct rt2x00lib_conf *libconf)
1123 {
1124         u32 reg;
1125
1126         rt2800_register_read(rt2x00dev, TX_RTY_CFG, &reg);
1127         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
1128                            libconf->conf->short_frame_max_tx_count);
1129         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
1130                            libconf->conf->long_frame_max_tx_count);
1131         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
1132         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
1133         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
1134         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
1135         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
1136 }
1137
1138 static void rt2800pci_config_ps(struct rt2x00_dev *rt2x00dev,
1139                                 struct rt2x00lib_conf *libconf)
1140 {
1141         enum dev_state state =
1142             (libconf->conf->flags & IEEE80211_CONF_PS) ?
1143                 STATE_SLEEP : STATE_AWAKE;
1144         u32 reg;
1145
1146         if (state == STATE_SLEEP) {
1147                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
1148
1149                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1150                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
1151                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
1152                                    libconf->conf->listen_interval - 1);
1153                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
1154                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1155
1156                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1157         } else {
1158                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
1159
1160                 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, &reg);
1161                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
1162                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
1163                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
1164                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
1165         }
1166 }
1167
1168 static void rt2800pci_config(struct rt2x00_dev *rt2x00dev,
1169                              struct rt2x00lib_conf *libconf,
1170                              const unsigned int flags)
1171 {
1172         /* Always recalculate LNA gain before changing configuration */
1173         rt2800pci_config_lna_gain(rt2x00dev, libconf);
1174
1175         if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
1176                 rt2800pci_config_channel(rt2x00dev, libconf->conf,
1177                                          &libconf->rf, &libconf->channel);
1178         if (flags & IEEE80211_CONF_CHANGE_POWER)
1179                 rt2800pci_config_txpower(rt2x00dev, libconf->conf->power_level);
1180         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
1181                 rt2800pci_config_retry_limit(rt2x00dev, libconf);
1182         if (flags & IEEE80211_CONF_CHANGE_PS)
1183                 rt2800pci_config_ps(rt2x00dev, libconf);
1184 }
1185
1186 /*
1187  * Link tuning
1188  */
1189 static void rt2800pci_link_stats(struct rt2x00_dev *rt2x00dev,
1190                                  struct link_qual *qual)
1191 {
1192         u32 reg;
1193
1194         /*
1195          * Update FCS error count from register.
1196          */
1197         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1198         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
1199 }
1200
1201 static u8 rt2800pci_get_default_vgc(struct rt2x00_dev *rt2x00dev)
1202 {
1203         if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ)
1204                 return 0x2e + rt2x00dev->lna_gain;
1205
1206         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
1207                 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
1208         else
1209                 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
1210 }
1211
1212 static inline void rt2800pci_set_vgc(struct rt2x00_dev *rt2x00dev,
1213                                      struct link_qual *qual, u8 vgc_level)
1214 {
1215         if (qual->vgc_level != vgc_level) {
1216                 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
1217                 qual->vgc_level = vgc_level;
1218                 qual->vgc_level_reg = vgc_level;
1219         }
1220 }
1221
1222 static void rt2800pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
1223                                   struct link_qual *qual)
1224 {
1225         rt2800pci_set_vgc(rt2x00dev, qual,
1226                           rt2800pci_get_default_vgc(rt2x00dev));
1227 }
1228
1229 static void rt2800pci_link_tuner(struct rt2x00_dev *rt2x00dev,
1230                                  struct link_qual *qual, const u32 count)
1231 {
1232         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION)
1233                 return;
1234
1235         /*
1236          * When RSSI is better then -80 increase VGC level with 0x10
1237          */
1238         rt2800pci_set_vgc(rt2x00dev, qual,
1239                           rt2800pci_get_default_vgc(rt2x00dev) +
1240                           ((qual->rssi > -80) * 0x10));
1241 }
1242
1243 /*
1244  * Firmware functions
1245  */
1246 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
1247 {
1248         return FIRMWARE_RT2860;
1249 }
1250
1251 static int rt2800pci_check_firmware(struct rt2x00_dev *rt2x00dev,
1252                                     const u8 *data, const size_t len)
1253 {
1254         u16 fw_crc;
1255         u16 crc;
1256
1257         /*
1258          * Only support 8kb firmware files.
1259          */
1260         if (len != 8192)
1261                 return FW_BAD_LENGTH;
1262
1263         /*
1264          * The last 2 bytes in the firmware array are the crc checksum itself,
1265          * this means that we should never pass those 2 bytes to the crc
1266          * algorithm.
1267          */
1268         fw_crc = (data[len - 2] << 8 | data[len - 1]);
1269
1270         /*
1271          * Use the crc ccitt algorithm.
1272          * This will return the same value as the legacy driver which
1273          * used bit ordering reversion on the both the firmware bytes
1274          * before input input as well as on the final output.
1275          * Obviously using crc ccitt directly is much more efficient.
1276          */
1277         crc = crc_ccitt(~0, data, len - 2);
1278
1279         /*
1280          * There is a small difference between the crc-itu-t + bitrev and
1281          * the crc-ccitt crc calculation. In the latter method the 2 bytes
1282          * will be swapped, use swab16 to convert the crc to the correct
1283          * value.
1284          */
1285         crc = swab16(crc);
1286
1287         return (fw_crc == crc) ? FW_OK : FW_BAD_CRC;
1288 }
1289
1290 static int rt2800pci_load_firmware(struct rt2x00_dev *rt2x00dev,
1291                                    const u8 *data, const size_t len)
1292 {
1293         unsigned int i;
1294         u32 reg;
1295
1296         /*
1297          * Wait for stable hardware.
1298          */
1299         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1300                 rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
1301                 if (reg && reg != ~0)
1302                         break;
1303                 msleep(1);
1304         }
1305
1306         if (i == REGISTER_BUSY_COUNT) {
1307                 ERROR(rt2x00dev, "Unstable hardware.\n");
1308                 return -EBUSY;
1309         }
1310
1311         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
1312         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
1313
1314         /*
1315          * Disable DMA, will be reenabled later when enabling
1316          * the radio.
1317          */
1318         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1319         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1320         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
1321         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1322         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
1323         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1324         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1325
1326         /*
1327          * enable Host program ram write selection
1328          */
1329         reg = 0;
1330         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
1331         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
1332
1333         /*
1334          * Write firmware to device.
1335          */
1336         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1337                                       data, len);
1338
1339         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
1340         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
1341
1342         /*
1343          * Wait for device to stabilize.
1344          */
1345         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1346                 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, &reg);
1347                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
1348                         break;
1349                 msleep(1);
1350         }
1351
1352         if (i == REGISTER_BUSY_COUNT) {
1353                 ERROR(rt2x00dev, "PBF system register not ready.\n");
1354                 return -EBUSY;
1355         }
1356
1357         /*
1358          * Disable interrupts
1359          */
1360         rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_RADIO_IRQ_OFF);
1361
1362         /*
1363          * Initialize BBP R/W access agent
1364          */
1365         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1366         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1367
1368         return 0;
1369 }
1370
1371 /*
1372  * Initialization functions.
1373  */
1374 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
1375 {
1376         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1377         u32 word;
1378
1379         if (entry->queue->qid == QID_RX) {
1380                 rt2x00_desc_read(entry_priv->desc, 1, &word);
1381
1382                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
1383         } else {
1384                 rt2x00_desc_read(entry_priv->desc, 1, &word);
1385
1386                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
1387         }
1388 }
1389
1390 static void rt2800pci_clear_entry(struct queue_entry *entry)
1391 {
1392         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1393         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1394         u32 word;
1395
1396         if (entry->queue->qid == QID_RX) {
1397                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1398                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
1399                 rt2x00_desc_write(entry_priv->desc, 0, word);
1400
1401                 rt2x00_desc_read(entry_priv->desc, 1, &word);
1402                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
1403                 rt2x00_desc_write(entry_priv->desc, 1, word);
1404         } else {
1405                 rt2x00_desc_read(entry_priv->desc, 1, &word);
1406                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
1407                 rt2x00_desc_write(entry_priv->desc, 1, word);
1408         }
1409 }
1410
1411 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
1412 {
1413         struct queue_entry_priv_pci *entry_priv;
1414         u32 reg;
1415
1416         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
1417         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
1418         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
1419         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
1420         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
1421         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
1422         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
1423         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
1424         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
1425
1426         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
1427         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
1428
1429         /*
1430          * Initialize registers.
1431          */
1432         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1433         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
1434         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
1435         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
1436         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
1437
1438         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1439         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
1440         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
1441         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
1442         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
1443
1444         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1445         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
1446         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
1447         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
1448         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
1449
1450         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1451         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
1452         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
1453         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
1454         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
1455
1456         entry_priv = rt2x00dev->rx->entries[0].priv_data;
1457         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
1458         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
1459         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
1460         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
1461
1462         /*
1463          * Enable global DMA configuration
1464          */
1465         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
1466         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
1467         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
1468         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
1469         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
1470
1471         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
1472
1473         return 0;
1474 }
1475
1476 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
1477 {
1478         u32 reg;
1479         unsigned int i;
1480
1481         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1482
1483         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1484         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
1485         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
1486         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1487
1488         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1489
1490         rt2800_register_read(rt2x00dev, BCN_OFFSET0, &reg);
1491         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
1492         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
1493         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
1494         rt2x00_set_field32(&reg, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
1495         rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
1496
1497         rt2800_register_read(rt2x00dev, BCN_OFFSET1, &reg);
1498         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
1499         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
1500         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
1501         rt2x00_set_field32(&reg, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
1502         rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
1503
1504         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
1505         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1506
1507         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
1508
1509         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
1510         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 0);
1511         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
1512         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
1513         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
1514         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1515         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
1516         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1517
1518         rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
1519         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
1520
1521         rt2800_register_read(rt2x00dev, TX_LINK_CFG, &reg);
1522         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
1523         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
1524         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
1525         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
1526         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
1527         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
1528         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
1529         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
1530         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
1531
1532         rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, &reg);
1533         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
1534         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
1535         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
1536
1537         rt2800_register_read(rt2x00dev, MAX_LEN_CFG, &reg);
1538         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
1539         if (rt2x00_rev(&rt2x00dev->chip) >= RT2880E_VERSION &&
1540             rt2x00_rev(&rt2x00dev->chip) < RT3070_VERSION)
1541                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 2);
1542         else
1543                 rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, 1);
1544         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 0);
1545         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 0);
1546         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1547
1548         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
1549
1550         rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, &reg);
1551         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
1552         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 0);
1553         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
1554         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
1555         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
1556         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1557
1558         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
1559         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 8);
1560         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
1561         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV, 1);
1562         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1563         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1564         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1565         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1566         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1567         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1568         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
1569
1570         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
1571         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 8);
1572         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
1573         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV, 1);
1574         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1575         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1576         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1577         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1578         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1579         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1580         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1581
1582         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
1583         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
1584         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 0);
1585         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV, 1);
1586         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1587         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1588         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1589         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1590         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1591         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1592         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1593
1594         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
1595         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
1596         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 0);
1597         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV, 1);
1598         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1599         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1600         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1601         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1602         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1603         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1604         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1605
1606         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
1607         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
1608         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 0);
1609         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV, 1);
1610         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1611         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1612         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1613         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
1614         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1615         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
1616         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1617
1618         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
1619         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
1620         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 0);
1621         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV, 1);
1622         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
1623         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
1624         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
1625         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
1626         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
1627         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
1628         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1629
1630         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, 0x0000583f);
1631         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
1632
1633         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
1634         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
1635         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
1636                            IEEE80211_MAX_RTS_THRESHOLD);
1637         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 0);
1638         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
1639
1640         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
1641         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
1642
1643         /*
1644          * ASIC will keep garbage value after boot, clear encryption keys.
1645          */
1646         for (i = 0; i < 4; i++)
1647                 rt2800_register_write(rt2x00dev,
1648                                          SHARED_KEY_MODE_ENTRY(i), 0);
1649
1650         for (i = 0; i < 256; i++) {
1651                 u32 wcid[2] = { 0xffffffff, 0x00ffffff };
1652                 rt2800_register_multiwrite(rt2x00dev, MAC_WCID_ENTRY(i),
1653                                               wcid, sizeof(wcid));
1654
1655                 rt2800_register_write(rt2x00dev, MAC_WCID_ATTR_ENTRY(i), 1);
1656                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
1657         }
1658
1659         /*
1660          * Clear all beacons
1661          * For the Beacon base registers we only need to clear
1662          * the first byte since that byte contains the VALID and OWNER
1663          * bits which (when set to 0) will invalidate the entire beacon.
1664          */
1665         rt2800_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1666         rt2800_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1667         rt2800_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1668         rt2800_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1669         rt2800_register_write(rt2x00dev, HW_BEACON_BASE4, 0);
1670         rt2800_register_write(rt2x00dev, HW_BEACON_BASE5, 0);
1671         rt2800_register_write(rt2x00dev, HW_BEACON_BASE6, 0);
1672         rt2800_register_write(rt2x00dev, HW_BEACON_BASE7, 0);
1673
1674         rt2800_register_read(rt2x00dev, HT_FBK_CFG0, &reg);
1675         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
1676         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
1677         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
1678         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
1679         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
1680         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
1681         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
1682         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
1683         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
1684
1685         rt2800_register_read(rt2x00dev, HT_FBK_CFG1, &reg);
1686         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
1687         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
1688         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
1689         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
1690         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
1691         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
1692         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
1693         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
1694         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
1695
1696         rt2800_register_read(rt2x00dev, LG_FBK_CFG0, &reg);
1697         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
1698         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
1699         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
1700         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
1701         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
1702         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
1703         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
1704         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
1705         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
1706
1707         rt2800_register_read(rt2x00dev, LG_FBK_CFG1, &reg);
1708         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
1709         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
1710         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
1711         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
1712         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
1713
1714         /*
1715          * We must clear the error counters.
1716          * These registers are cleared on read,
1717          * so we may pass a useless variable to store the value.
1718          */
1719         rt2800_register_read(rt2x00dev, RX_STA_CNT0, &reg);
1720         rt2800_register_read(rt2x00dev, RX_STA_CNT1, &reg);
1721         rt2800_register_read(rt2x00dev, RX_STA_CNT2, &reg);
1722         rt2800_register_read(rt2x00dev, TX_STA_CNT0, &reg);
1723         rt2800_register_read(rt2x00dev, TX_STA_CNT1, &reg);
1724         rt2800_register_read(rt2x00dev, TX_STA_CNT2, &reg);
1725
1726         return 0;
1727 }
1728
1729 static int rt2800pci_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
1730 {
1731         unsigned int i;
1732         u32 reg;
1733
1734         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1735                 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, &reg);
1736                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
1737                         return 0;
1738
1739                 udelay(REGISTER_BUSY_DELAY);
1740         }
1741
1742         ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
1743         return -EACCES;
1744 }
1745
1746 static int rt2800pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1747 {
1748         unsigned int i;
1749         u8 value;
1750
1751         /*
1752          * BBP was enabled after firmware was loaded,
1753          * but we need to reactivate it now.
1754          */
1755         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
1756         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1757         msleep(1);
1758
1759         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1760                 rt2800_bbp_read(rt2x00dev, 0, &value);
1761                 if ((value != 0xff) && (value != 0x00))
1762                         return 0;
1763                 udelay(REGISTER_BUSY_DELAY);
1764         }
1765
1766         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1767         return -EACCES;
1768 }
1769
1770 static int rt2800pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1771 {
1772         unsigned int i;
1773         u16 eeprom;
1774         u8 reg_id;
1775         u8 value;
1776
1777         if (unlikely(rt2800pci_wait_bbp_rf_ready(rt2x00dev) ||
1778                      rt2800pci_wait_bbp_ready(rt2x00dev)))
1779                 return -EACCES;
1780
1781         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
1782         rt2800_bbp_write(rt2x00dev, 66, 0x38);
1783         rt2800_bbp_write(rt2x00dev, 69, 0x12);
1784         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
1785         rt2800_bbp_write(rt2x00dev, 73, 0x10);
1786         rt2800_bbp_write(rt2x00dev, 81, 0x37);
1787         rt2800_bbp_write(rt2x00dev, 82, 0x62);
1788         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
1789         rt2800_bbp_write(rt2x00dev, 84, 0x99);
1790         rt2800_bbp_write(rt2x00dev, 86, 0x00);
1791         rt2800_bbp_write(rt2x00dev, 91, 0x04);
1792         rt2800_bbp_write(rt2x00dev, 92, 0x00);
1793         rt2800_bbp_write(rt2x00dev, 103, 0x00);
1794         rt2800_bbp_write(rt2x00dev, 105, 0x05);
1795
1796         if (rt2x00_rev(&rt2x00dev->chip) == RT2860C_VERSION) {
1797                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
1798                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
1799         }
1800
1801         if (rt2x00_rev(&rt2x00dev->chip) > RT2860D_VERSION)
1802                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
1803
1804         if (rt2x00_rt(&rt2x00dev->chip, RT3052)) {
1805                 rt2800_bbp_write(rt2x00dev, 31, 0x08);
1806                 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
1807                 rt2800_bbp_write(rt2x00dev, 80, 0x08);
1808         }
1809
1810         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1811                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1812
1813                 if (eeprom != 0xffff && eeprom != 0x0000) {
1814                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1815                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1816                         rt2800_bbp_write(rt2x00dev, reg_id, value);
1817                 }
1818         }
1819
1820         return 0;
1821 }
1822
1823 static u8 rt2800pci_init_rx_filter(struct rt2x00_dev *rt2x00dev,
1824                                    bool bw40, u8 rfcsr24, u8 filter_target)
1825 {
1826         unsigned int i;
1827         u8 bbp;
1828         u8 rfcsr;
1829         u8 passband;
1830         u8 stopband;
1831         u8 overtuned = 0;
1832
1833         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1834
1835         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1836         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
1837         rt2800_bbp_write(rt2x00dev, 4, bbp);
1838
1839         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1840         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
1841         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1842
1843         /*
1844          * Set power & frequency of passband test tone
1845          */
1846         rt2800_bbp_write(rt2x00dev, 24, 0);
1847
1848         for (i = 0; i < 100; i++) {
1849                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1850                 msleep(1);
1851
1852                 rt2800_bbp_read(rt2x00dev, 55, &passband);
1853                 if (passband)
1854                         break;
1855         }
1856
1857         /*
1858          * Set power & frequency of stopband test tone
1859          */
1860         rt2800_bbp_write(rt2x00dev, 24, 0x06);
1861
1862         for (i = 0; i < 100; i++) {
1863                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
1864                 msleep(1);
1865
1866                 rt2800_bbp_read(rt2x00dev, 55, &stopband);
1867
1868                 if ((passband - stopband) <= filter_target) {
1869                         rfcsr24++;
1870                         overtuned += ((passband - stopband) == filter_target);
1871                 } else
1872                         break;
1873
1874                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1875         }
1876
1877         rfcsr24 -= !!overtuned;
1878
1879         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
1880         return rfcsr24;
1881 }
1882
1883 static int rt2800pci_init_rfcsr(struct rt2x00_dev *rt2x00dev)
1884 {
1885         u8 rfcsr;
1886         u8 bbp;
1887
1888         if (!rt2x00_rf(&rt2x00dev->chip, RF3020) &&
1889             !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
1890             !rt2x00_rf(&rt2x00dev->chip, RF3022))
1891                 return 0;
1892
1893         /*
1894          * Init RF calibration.
1895          */
1896         rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1897         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1898         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1899         msleep(1);
1900         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1901         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1902
1903         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
1904         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
1905         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
1906         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
1907         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
1908         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
1909         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
1910         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
1911         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
1912         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
1913         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
1914         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
1915         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
1916         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
1917         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
1918         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
1919         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
1920         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
1921         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
1922         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
1923         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
1924         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
1925         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
1926         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
1927         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
1928         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1929         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
1930         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
1931         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
1932         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
1933
1934         /*
1935          * Set RX Filter calibration for 20MHz and 40MHz
1936          */
1937         rt2x00dev->calibration[0] =
1938             rt2800pci_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
1939         rt2x00dev->calibration[1] =
1940             rt2800pci_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
1941
1942         /*
1943          * Set back to initial state
1944          */
1945         rt2800_bbp_write(rt2x00dev, 24, 0);
1946
1947         rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
1948         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
1949         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
1950
1951         /*
1952          * set BBP back to BW20
1953          */
1954         rt2800_bbp_read(rt2x00dev, 4, &bbp);
1955         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
1956         rt2800_bbp_write(rt2x00dev, 4, bbp);
1957
1958         return 0;
1959 }
1960
1961 /*
1962  * Device state switch handlers.
1963  */
1964 static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1965                                 enum dev_state state)
1966 {
1967         u32 reg;
1968
1969         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
1970         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
1971                            (state == STATE_RADIO_RX_ON) ||
1972                            (state == STATE_RADIO_RX_ON_LINK));
1973         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
1974 }
1975
1976 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1977                                  enum dev_state state)
1978 {
1979         int mask = (state == STATE_RADIO_IRQ_ON);
1980         u32 reg;
1981
1982         /*
1983          * When interrupts are being enabled, the interrupt registers
1984          * should clear the register to assure a clean state.
1985          */
1986         if (state == STATE_RADIO_IRQ_ON) {
1987                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1988                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1989         }
1990
1991         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1992         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, mask);
1993         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, mask);
1994         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
1995         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, mask);
1996         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, mask);
1997         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, mask);
1998         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, mask);
1999         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, mask);
2000         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, mask);
2001         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, mask);
2002         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, mask);
2003         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
2004         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
2005         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
2006         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
2007         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, mask);
2008         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, mask);
2009         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, mask);
2010         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
2011 }
2012
2013 static int rt2800pci_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
2014 {
2015         unsigned int i;
2016         u32 reg;
2017
2018         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
2019                 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2020                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
2021                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
2022                         return 0;
2023
2024                 msleep(1);
2025         }
2026
2027         ERROR(rt2x00dev, "WPDMA TX/RX busy, aborting.\n");
2028         return -EACCES;
2029 }
2030
2031 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
2032 {
2033         u32 reg;
2034         u16 word;
2035
2036         /*
2037          * Initialize all registers.
2038          */
2039         if (unlikely(rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2040                      rt2800pci_init_queues(rt2x00dev) ||
2041                      rt2800pci_init_registers(rt2x00dev) ||
2042                      rt2800pci_wait_wpdma_ready(rt2x00dev) ||
2043                      rt2800pci_init_bbp(rt2x00dev) ||
2044                      rt2800pci_init_rfcsr(rt2x00dev)))
2045                 return -EIO;
2046
2047         /*
2048          * Send signal to firmware during boot time.
2049          */
2050         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0xff, 0, 0);
2051
2052         /*
2053          * Enable RX.
2054          */
2055         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2056         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2057         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
2058         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2059
2060         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2061         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
2062         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
2063         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
2064         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2065         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2066
2067         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
2068         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
2069         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
2070         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
2071
2072         /*
2073          * Initialize LED control
2074          */
2075         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED1, &word);
2076         rt2800_mcu_request(rt2x00dev, MCU_LED_1, 0xff,
2077                               word & 0xff, (word >> 8) & 0xff);
2078
2079         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED2, &word);
2080         rt2800_mcu_request(rt2x00dev, MCU_LED_2, 0xff,
2081                               word & 0xff, (word >> 8) & 0xff);
2082
2083         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED3, &word);
2084         rt2800_mcu_request(rt2x00dev, MCU_LED_3, 0xff,
2085                               word & 0xff, (word >> 8) & 0xff);
2086
2087         return 0;
2088 }
2089
2090 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
2091 {
2092         u32 reg;
2093
2094         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
2095         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
2096         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
2097         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
2098         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
2099         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
2100         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
2101
2102         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
2103         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0);
2104         rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0);
2105
2106         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
2107
2108         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2109         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
2110         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
2111         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
2112         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
2113         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
2114         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
2115         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
2116         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2117
2118         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
2119         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
2120
2121         /* Wait for DMA, ignore error */
2122         rt2800pci_wait_wpdma_ready(rt2x00dev);
2123 }
2124
2125 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
2126                                enum dev_state state)
2127 {
2128         /*
2129          * Always put the device to sleep (even when we intend to wakeup!)
2130          * if the device is booting and wasn't asleep it will return
2131          * failure when attempting to wakeup.
2132          */
2133         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
2134
2135         if (state == STATE_AWAKE) {
2136                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
2137                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
2138         }
2139
2140         return 0;
2141 }
2142
2143 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
2144                                       enum dev_state state)
2145 {
2146         int retval = 0;
2147
2148         switch (state) {
2149         case STATE_RADIO_ON:
2150                 /*
2151                  * Before the radio can be enabled, the device first has
2152                  * to be woken up. After that it needs a bit of time
2153                  * to be fully awake and then the radio can be enabled.
2154                  */
2155                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
2156                 msleep(1);
2157                 retval = rt2800pci_enable_radio(rt2x00dev);
2158                 break;
2159         case STATE_RADIO_OFF:
2160                 /*
2161                  * After the radio has been disabled, the device should
2162                  * be put to sleep for powersaving.
2163                  */
2164                 rt2800pci_disable_radio(rt2x00dev);
2165                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
2166                 break;
2167         case STATE_RADIO_RX_ON:
2168         case STATE_RADIO_RX_ON_LINK:
2169         case STATE_RADIO_RX_OFF:
2170         case STATE_RADIO_RX_OFF_LINK:
2171                 rt2800pci_toggle_rx(rt2x00dev, state);
2172                 break;
2173         case STATE_RADIO_IRQ_ON:
2174         case STATE_RADIO_IRQ_OFF:
2175                 rt2800pci_toggle_irq(rt2x00dev, state);
2176                 break;
2177         case STATE_DEEP_SLEEP:
2178         case STATE_SLEEP:
2179         case STATE_STANDBY:
2180         case STATE_AWAKE:
2181                 retval = rt2800pci_set_state(rt2x00dev, state);
2182                 break;
2183         default:
2184                 retval = -ENOTSUPP;
2185                 break;
2186         }
2187
2188         if (unlikely(retval))
2189                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
2190                       state, retval);
2191
2192         return retval;
2193 }
2194
2195 /*
2196  * TX descriptor initialization
2197  */
2198 static void rt2800pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
2199                                     struct sk_buff *skb,
2200                                     struct txentry_desc *txdesc)
2201 {
2202         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
2203         __le32 *txd = skbdesc->desc;
2204         __le32 *txwi = (__le32 *)(skb->data - rt2x00dev->hw->extra_tx_headroom);
2205         u32 word;
2206
2207         /*
2208          * Initialize TX Info descriptor
2209          */
2210         rt2x00_desc_read(txwi, 0, &word);
2211         rt2x00_set_field32(&word, TXWI_W0_FRAG,
2212                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2213         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS, 0);
2214         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
2215         rt2x00_set_field32(&word, TXWI_W0_TS,
2216                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
2217         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
2218                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
2219         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY, txdesc->mpdu_density);
2220         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->ifs);
2221         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->mcs);
2222         rt2x00_set_field32(&word, TXWI_W0_BW,
2223                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
2224         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
2225                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
2226         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->stbc);
2227         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
2228         rt2x00_desc_write(txwi, 0, word);
2229
2230         rt2x00_desc_read(txwi, 1, &word);
2231         rt2x00_set_field32(&word, TXWI_W1_ACK,
2232                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
2233         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
2234                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
2235         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->ba_size);
2236         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
2237                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
2238                            txdesc->key_idx : 0xff);
2239         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
2240                            skb->len - txdesc->l2pad);
2241         rt2x00_set_field32(&word, TXWI_W1_PACKETID,
2242                            skbdesc->entry->queue->qid + 1);
2243         rt2x00_desc_write(txwi, 1, word);
2244
2245         /*
2246          * Always write 0 to IV/EIV fields, hardware will insert the IV
2247          * from the IVEIV register when TXD_W3_WIV is set to 0.
2248          * When TXD_W3_WIV is set to 1 it will use the IV data
2249          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
2250          * crypto entry in the registers should be used to encrypt the frame.
2251          */
2252         _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
2253         _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
2254
2255         /*
2256          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
2257          * must contains a TXWI structure + 802.11 header + padding + 802.11
2258          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
2259          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
2260          * data. It means that LAST_SEC0 is always 0.
2261          */
2262
2263         /*
2264          * Initialize TX descriptor
2265          */
2266         rt2x00_desc_read(txd, 0, &word);
2267         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
2268         rt2x00_desc_write(txd, 0, word);
2269
2270         rt2x00_desc_read(txd, 1, &word);
2271         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, skb->len);
2272         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
2273                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
2274         rt2x00_set_field32(&word, TXD_W1_BURST,
2275                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
2276         rt2x00_set_field32(&word, TXD_W1_SD_LEN0,
2277                            rt2x00dev->hw->extra_tx_headroom);
2278         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
2279         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
2280         rt2x00_desc_write(txd, 1, word);
2281
2282         rt2x00_desc_read(txd, 2, &word);
2283         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
2284                            skbdesc->skb_dma + rt2x00dev->hw->extra_tx_headroom);
2285         rt2x00_desc_write(txd, 2, word);
2286
2287         rt2x00_desc_read(txd, 3, &word);
2288         rt2x00_set_field32(&word, TXD_W3_WIV,
2289                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
2290         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
2291         rt2x00_desc_write(txd, 3, word);
2292 }
2293
2294 /*
2295  * TX data initialization
2296  */
2297 static void rt2800pci_write_beacon(struct queue_entry *entry)
2298 {
2299         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2300         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2301         unsigned int beacon_base;
2302         u32 reg;
2303
2304         /*
2305          * Disable beaconing while we are reloading the beacon data,
2306          * otherwise we might be sending out invalid data.
2307          */
2308         rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2309         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
2310         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2311
2312         /*
2313          * Write entire beacon with descriptor to register.
2314          */
2315         beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
2316         rt2800_register_multiwrite(rt2x00dev,
2317                                       beacon_base,
2318                                       skbdesc->desc, skbdesc->desc_len);
2319         rt2800_register_multiwrite(rt2x00dev,
2320                                       beacon_base + skbdesc->desc_len,
2321                                       entry->skb->data, entry->skb->len);
2322
2323         /*
2324          * Clean up beacon skb.
2325          */
2326         dev_kfree_skb_any(entry->skb);
2327         entry->skb = NULL;
2328 }
2329
2330 static void rt2800pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
2331                                     const enum data_queue_qid queue_idx)
2332 {
2333         struct data_queue *queue;
2334         unsigned int idx, qidx = 0;
2335         u32 reg;
2336
2337         if (queue_idx == QID_BEACON) {
2338                 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
2339                 if (!rt2x00_get_field32(reg, BCN_TIME_CFG_BEACON_GEN)) {
2340                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
2341                         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
2342                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
2343                         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2344                 }
2345                 return;
2346         }
2347
2348         if (queue_idx > QID_HCCA && queue_idx != QID_MGMT)
2349                 return;
2350
2351         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
2352         idx = queue->index[Q_INDEX];
2353
2354         if (queue_idx == QID_MGMT)
2355                 qidx = 5;
2356         else
2357                 qidx = queue_idx;
2358
2359         rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), idx);
2360 }
2361
2362 static void rt2800pci_kill_tx_queue(struct rt2x00_dev *rt2x00dev,
2363                                     const enum data_queue_qid qid)
2364 {
2365         u32 reg;
2366
2367         if (qid == QID_BEACON) {
2368                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
2369                 return;
2370         }
2371
2372         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
2373         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (qid == QID_AC_BE));
2374         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (qid == QID_AC_BK));
2375         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (qid == QID_AC_VI));
2376         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (qid == QID_AC_VO));
2377         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
2378 }
2379
2380 /*
2381  * RX control handlers
2382  */
2383 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
2384                                   struct rxdone_entry_desc *rxdesc)
2385 {
2386         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
2387         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
2388         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
2389         __le32 *rxd = entry_priv->desc;
2390         __le32 *rxwi = (__le32 *)entry->skb->data;
2391         u32 rxd3;
2392         u32 rxwi0;
2393         u32 rxwi1;
2394         u32 rxwi2;
2395         u32 rxwi3;
2396
2397         rt2x00_desc_read(rxd, 3, &rxd3);
2398         rt2x00_desc_read(rxwi, 0, &rxwi0);
2399         rt2x00_desc_read(rxwi, 1, &rxwi1);
2400         rt2x00_desc_read(rxwi, 2, &rxwi2);
2401         rt2x00_desc_read(rxwi, 3, &rxwi3);
2402
2403         if (rt2x00_get_field32(rxd3, RXD_W3_CRC_ERROR))
2404                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
2405
2406         if (test_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags)) {
2407                 /*
2408                  * Unfortunately we don't know the cipher type used during
2409                  * decryption. This prevents us from correct providing
2410                  * correct statistics through debugfs.
2411                  */
2412                 rxdesc->cipher = rt2x00_get_field32(rxwi0, RXWI_W0_UDF);
2413                 rxdesc->cipher_status =
2414                     rt2x00_get_field32(rxd3, RXD_W3_CIPHER_ERROR);
2415         }
2416
2417         if (rt2x00_get_field32(rxd3, RXD_W3_DECRYPTED)) {
2418                 /*
2419                  * Hardware has stripped IV/EIV data from 802.11 frame during
2420                  * decryption. Unfortunately the descriptor doesn't contain
2421                  * any fields with the EIV/IV data either, so they can't
2422                  * be restored by rt2x00lib.
2423                  */
2424                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
2425
2426                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
2427                         rxdesc->flags |= RX_FLAG_DECRYPTED;
2428                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
2429                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
2430         }
2431
2432         if (rt2x00_get_field32(rxd3, RXD_W3_MY_BSS))
2433                 rxdesc->dev_flags |= RXDONE_MY_BSS;
2434
2435         if (rt2x00_get_field32(rxd3, RXD_W3_L2PAD)) {
2436                 rxdesc->dev_flags |= RXDONE_L2PAD;
2437                 skbdesc->flags |= SKBDESC_L2_PADDED;
2438         }
2439
2440         if (rt2x00_get_field32(rxwi1, RXWI_W1_SHORT_GI))
2441                 rxdesc->flags |= RX_FLAG_SHORT_GI;
2442
2443         if (rt2x00_get_field32(rxwi1, RXWI_W1_BW))
2444                 rxdesc->flags |= RX_FLAG_40MHZ;
2445
2446         /*
2447          * Detect RX rate, always use MCS as signal type.
2448          */
2449         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
2450         rxdesc->rate_mode = rt2x00_get_field32(rxwi1, RXWI_W1_PHYMODE);
2451         rxdesc->signal = rt2x00_get_field32(rxwi1, RXWI_W1_MCS);
2452
2453         /*
2454          * Mask of 0x8 bit to remove the short preamble flag.
2455          */
2456         if (rxdesc->rate_mode == RATE_MODE_CCK)
2457                 rxdesc->signal &= ~0x8;
2458
2459         rxdesc->rssi =
2460             (rt2x00_get_field32(rxwi2, RXWI_W2_RSSI0) +
2461              rt2x00_get_field32(rxwi2, RXWI_W2_RSSI1)) / 2;
2462
2463         rxdesc->noise =
2464             (rt2x00_get_field32(rxwi3, RXWI_W3_SNR0) +
2465              rt2x00_get_field32(rxwi3, RXWI_W3_SNR1)) / 2;
2466
2467         rxdesc->size = rt2x00_get_field32(rxwi0, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
2468
2469         /*
2470          * Set RX IDX in register to inform hardware that we have handled
2471          * this entry and it is available for reuse again.
2472          */
2473         rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
2474
2475         /*
2476          * Remove TXWI descriptor from start of buffer.
2477          */
2478         skb_pull(entry->skb, RXWI_DESC_SIZE);
2479         skb_trim(entry->skb, rxdesc->size);
2480 }
2481
2482 /*
2483  * Interrupt functions.
2484  */
2485 static void rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
2486 {
2487         struct data_queue *queue;
2488         struct queue_entry *entry;
2489         struct queue_entry *entry_done;
2490         struct queue_entry_priv_pci *entry_priv;
2491         struct txdone_entry_desc txdesc;
2492         u32 word;
2493         u32 reg;
2494         u32 old_reg;
2495         unsigned int type;
2496         unsigned int index;
2497         u16 mcs, real_mcs;
2498
2499         /*
2500          * During each loop we will compare the freshly read
2501          * TX_STA_FIFO register value with the value read from
2502          * the previous loop. If the 2 values are equal then
2503          * we should stop processing because the chance it
2504          * quite big that the device has been unplugged and
2505          * we risk going into an endless loop.
2506          */
2507         old_reg = 0;
2508
2509         while (1) {
2510                 rt2800_register_read(rt2x00dev, TX_STA_FIFO, &reg);
2511                 if (!rt2x00_get_field32(reg, TX_STA_FIFO_VALID))
2512                         break;
2513
2514                 if (old_reg == reg)
2515                         break;
2516                 old_reg = reg;
2517
2518                 /*
2519                  * Skip this entry when it contains an invalid
2520                  * queue identication number.
2521                  */
2522                 type = rt2x00_get_field32(reg, TX_STA_FIFO_PID_TYPE) - 1;
2523                 if (type >= QID_RX)
2524                         continue;
2525
2526                 queue = rt2x00queue_get_queue(rt2x00dev, type);
2527                 if (unlikely(!queue))
2528                         continue;
2529
2530                 /*
2531                  * Skip this entry when it contains an invalid
2532                  * index number.
2533                  */
2534                 index = rt2x00_get_field32(reg, TX_STA_FIFO_WCID) - 1;
2535                 if (unlikely(index >= queue->limit))
2536                         continue;
2537
2538                 entry = &queue->entries[index];
2539                 entry_priv = entry->priv_data;
2540                 rt2x00_desc_read((__le32 *)entry->skb->data, 0, &word);
2541
2542                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2543                 while (entry != entry_done) {
2544                         /*
2545                          * Catch up.
2546                          * Just report any entries we missed as failed.
2547                          */
2548                         WARNING(rt2x00dev,
2549                                 "TX status report missed for entry %d\n",
2550                                 entry_done->entry_idx);
2551
2552                         txdesc.flags = 0;
2553                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
2554                         txdesc.retry = 0;
2555
2556                         rt2x00lib_txdone(entry_done, &txdesc);
2557                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
2558                 }
2559
2560                 /*
2561                  * Obtain the status about this packet.
2562                  */
2563                 txdesc.flags = 0;
2564                 if (rt2x00_get_field32(reg, TX_STA_FIFO_TX_SUCCESS))
2565                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
2566                 else
2567                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
2568
2569                 /*
2570                  * Ralink has a retry mechanism using a global fallback
2571                  * table. We setup this fallback table to try immediate
2572                  * lower rate for all rates. In the TX_STA_FIFO,
2573                  * the MCS field contains the MCS used for the successfull
2574                  * transmission. If the first transmission succeed,
2575                  * we have mcs == tx_mcs. On the second transmission,
2576                  * we have mcs = tx_mcs - 1. So the number of
2577                  * retry is (tx_mcs - mcs).
2578                  */
2579                 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
2580                 real_mcs = rt2x00_get_field32(reg, TX_STA_FIFO_MCS);
2581                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
2582                 txdesc.retry = mcs - min(mcs, real_mcs);
2583
2584                 rt2x00lib_txdone(entry, &txdesc);
2585         }
2586 }
2587
2588 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
2589 {
2590         struct rt2x00_dev *rt2x00dev = dev_instance;
2591         u32 reg;
2592
2593         /* Read status and ACK all interrupts */
2594         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
2595         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
2596
2597         if (!reg)
2598                 return IRQ_NONE;
2599
2600         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
2601                 return IRQ_HANDLED;
2602
2603         /*
2604          * 1 - Rx ring done interrupt.
2605          */
2606         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
2607                 rt2x00pci_rxdone(rt2x00dev);
2608
2609         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
2610                 rt2800pci_txdone(rt2x00dev);
2611
2612         return IRQ_HANDLED;
2613 }
2614
2615 /*
2616  * Device probe functions.
2617  */
2618 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
2619 {
2620         u16 word;
2621         u8 *mac;
2622         u8 default_lna_gain;
2623
2624         /*
2625          * Read EEPROM into buffer
2626          */
2627         switch(rt2x00dev->chip.rt) {
2628         case RT2880:
2629         case RT3052:
2630                 rt2800pci_read_eeprom_soc(rt2x00dev);
2631                 break;
2632         case RT3090:
2633                 rt2800pci_read_eeprom_efuse(rt2x00dev);
2634                 break;
2635         default:
2636                 rt2800pci_read_eeprom_pci(rt2x00dev);
2637                 break;
2638         }
2639
2640         /*
2641          * Start validation of the data that has been read.
2642          */
2643         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
2644         if (!is_valid_ether_addr(mac)) {
2645                 random_ether_addr(mac);
2646                 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
2647         }
2648
2649         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
2650         if (word == 0xffff) {
2651                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2652                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TXPATH, 1);
2653                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2820);
2654                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2655                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
2656         } else if (rt2x00_rev(&rt2x00dev->chip) < RT2883_VERSION) {
2657                 /*
2658                  * There is a max of 2 RX streams for RT2860 series
2659                  */
2660                 if (rt2x00_get_field16(word, EEPROM_ANTENNA_RXPATH) > 2)
2661                         rt2x00_set_field16(&word, EEPROM_ANTENNA_RXPATH, 2);
2662                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
2663         }
2664
2665         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
2666         if (word == 0xffff) {
2667                 rt2x00_set_field16(&word, EEPROM_NIC_HW_RADIO, 0);
2668                 rt2x00_set_field16(&word, EEPROM_NIC_DYNAMIC_TX_AGC, 0);
2669                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
2670                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
2671                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
2672                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_BG, 0);
2673                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_SB_A, 0);
2674                 rt2x00_set_field16(&word, EEPROM_NIC_WPS_PBC, 0);
2675                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_BG, 0);
2676                 rt2x00_set_field16(&word, EEPROM_NIC_BW40M_A, 0);
2677                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
2678                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2679         }
2680
2681         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2682         if ((word & 0x00ff) == 0x00ff) {
2683                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2684                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
2685                                    LED_MODE_TXRX_ACTIVITY);
2686                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
2687                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2688                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED1, 0x5555);
2689                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED2, 0x2221);
2690                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED3, 0xa9f8);
2691                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2692         }
2693
2694         /*
2695          * During the LNA validation we are going to use
2696          * lna0 as correct value. Note that EEPROM_LNA
2697          * is never validated.
2698          */
2699         rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
2700         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
2701
2702         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
2703         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
2704                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
2705         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
2706                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
2707         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
2708
2709         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
2710         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
2711                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
2712         if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
2713             rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
2714                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
2715                                    default_lna_gain);
2716         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
2717
2718         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
2719         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
2720                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
2721         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
2722                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
2723         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
2724
2725         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
2726         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
2727                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
2728         if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
2729             rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
2730                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
2731                                    default_lna_gain);
2732         rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
2733
2734         return 0;
2735 }
2736
2737 static int rt2800pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2738 {
2739         u32 reg;
2740         u16 value;
2741         u16 eeprom;
2742
2743         /*
2744          * Read EEPROM word for configuration.
2745          */
2746         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2747
2748         /*
2749          * Identify RF chipset.
2750          */
2751         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2752         rt2800_register_read(rt2x00dev, MAC_CSR0, &reg);
2753         rt2x00_set_chip_rf(rt2x00dev, value, reg);
2754
2755         if (!rt2x00_rf(&rt2x00dev->chip, RF2820) &&
2756             !rt2x00_rf(&rt2x00dev->chip, RF2850) &&
2757             !rt2x00_rf(&rt2x00dev->chip, RF2720) &&
2758             !rt2x00_rf(&rt2x00dev->chip, RF2750) &&
2759             !rt2x00_rf(&rt2x00dev->chip, RF3020) &&
2760             !rt2x00_rf(&rt2x00dev->chip, RF2020) &&
2761             !rt2x00_rf(&rt2x00dev->chip, RF3021) &&
2762             !rt2x00_rf(&rt2x00dev->chip, RF3022)) {
2763                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2764                 return -ENODEV;
2765         }
2766
2767         /*
2768          * Identify default antenna configuration.
2769          */
2770         rt2x00dev->default_ant.tx =
2771             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH);
2772         rt2x00dev->default_ant.rx =
2773             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH);
2774
2775         /*
2776          * Read frequency offset and RF programming sequence.
2777          */
2778         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2779         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2780
2781         /*
2782          * Read external LNA informations.
2783          */
2784         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2785
2786         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2787                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2788         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2789                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2790
2791         /*
2792          * Detect if this device has an hardware controlled radio.
2793          */
2794         if (rt2x00_get_field16(eeprom, EEPROM_NIC_HW_RADIO))
2795                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2796
2797         /*
2798          * Store led settings, for correct led behaviour.
2799          */
2800 #ifdef CONFIG_RT2X00_LIB_LEDS
2801         rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
2802         rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
2803         rt2800pci_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
2804
2805         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &rt2x00dev->led_mcu_reg);
2806 #endif /* CONFIG_RT2X00_LIB_LEDS */
2807
2808         return 0;
2809 }
2810
2811 /*
2812  * RF value list for rt2860
2813  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
2814  */
2815 static const struct rf_channel rf_vals[] = {
2816         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
2817         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
2818         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
2819         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
2820         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
2821         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
2822         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
2823         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
2824         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
2825         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
2826         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
2827         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
2828         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
2829         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
2830
2831         /* 802.11 UNI / HyperLan 2 */
2832         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
2833         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
2834         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
2835         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
2836         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
2837         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
2838         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
2839         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
2840         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
2841         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
2842         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
2843         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
2844
2845         /* 802.11 HyperLan 2 */
2846         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
2847         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
2848         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
2849         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
2850         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
2851         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
2852         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
2853         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
2854         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
2855         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
2856         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
2857         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
2858         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
2859         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
2860         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
2861         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
2862
2863         /* 802.11 UNII */
2864         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
2865         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
2866         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
2867         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
2868         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
2869         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
2870         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
2871
2872         /* 802.11 Japan */
2873         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
2874         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
2875         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
2876         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
2877         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
2878         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
2879         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
2880 };
2881
2882 static int rt2800pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2883 {
2884         struct hw_mode_spec *spec = &rt2x00dev->spec;
2885         struct channel_info *info;
2886         char *tx_power1;
2887         char *tx_power2;
2888         unsigned int i;
2889         u16 eeprom;
2890
2891         /*
2892          * Initialize all hw fields.
2893          */
2894         rt2x00dev->hw->flags =
2895             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2896             IEEE80211_HW_SIGNAL_DBM |
2897             IEEE80211_HW_SUPPORTS_PS |
2898             IEEE80211_HW_PS_NULLFUNC_STACK;
2899         rt2x00dev->hw->extra_tx_headroom = TXWI_DESC_SIZE;
2900
2901         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
2902         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2903                                 rt2x00_eeprom_addr(rt2x00dev,
2904                                                    EEPROM_MAC_ADDR_0));
2905
2906         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2907
2908         /*
2909          * Initialize hw_mode information.
2910          */
2911         spec->supported_bands = SUPPORT_BAND_2GHZ;
2912         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2913
2914         if (rt2x00_rf(&rt2x00dev->chip, RF2820) ||
2915             rt2x00_rf(&rt2x00dev->chip, RF2720) ||
2916             rt2x00_rf(&rt2x00dev->chip, RF3020) ||
2917             rt2x00_rf(&rt2x00dev->chip, RF3021) ||
2918             rt2x00_rf(&rt2x00dev->chip, RF3022) ||
2919             rt2x00_rf(&rt2x00dev->chip, RF2020) ||
2920             rt2x00_rf(&rt2x00dev->chip, RF3052)) {
2921                 spec->num_channels = 14;
2922                 spec->channels = rf_vals;
2923         } else if (rt2x00_rf(&rt2x00dev->chip, RF2850) ||
2924                    rt2x00_rf(&rt2x00dev->chip, RF2750)) {
2925                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2926                 spec->num_channels = ARRAY_SIZE(rf_vals);
2927                 spec->channels = rf_vals;
2928         }
2929
2930         /*
2931          * Initialize HT information.
2932          */
2933         spec->ht.ht_supported = true;
2934         spec->ht.cap =
2935             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
2936             IEEE80211_HT_CAP_GRN_FLD |
2937             IEEE80211_HT_CAP_SGI_20 |
2938             IEEE80211_HT_CAP_SGI_40 |
2939             IEEE80211_HT_CAP_TX_STBC |
2940             IEEE80211_HT_CAP_RX_STBC |
2941             IEEE80211_HT_CAP_PSMP_SUPPORT;
2942         spec->ht.ampdu_factor = 3;
2943         spec->ht.ampdu_density = 4;
2944         spec->ht.mcs.tx_params =
2945             IEEE80211_HT_MCS_TX_DEFINED |
2946             IEEE80211_HT_MCS_TX_RX_DIFF |
2947             ((rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TXPATH) - 1) <<
2948                 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
2949
2950         switch (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RXPATH)) {
2951         case 3:
2952                 spec->ht.mcs.rx_mask[2] = 0xff;
2953         case 2:
2954                 spec->ht.mcs.rx_mask[1] = 0xff;
2955         case 1:
2956                 spec->ht.mcs.rx_mask[0] = 0xff;
2957                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
2958                 break;
2959         }
2960
2961         /*
2962          * Create channel information array
2963          */
2964         info = kzalloc(spec->num_channels * sizeof(*info), GFP_KERNEL);
2965         if (!info)
2966                 return -ENOMEM;
2967
2968         spec->channels_info = info;
2969
2970         tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
2971         tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
2972
2973         for (i = 0; i < 14; i++) {
2974                 info[i].tx_power1 = TXPOWER_G_FROM_DEV(tx_power1[i]);
2975                 info[i].tx_power2 = TXPOWER_G_FROM_DEV(tx_power2[i]);
2976         }
2977
2978         if (spec->num_channels > 14) {
2979                 tx_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
2980                 tx_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
2981
2982                 for (i = 14; i < spec->num_channels; i++) {
2983                         info[i].tx_power1 = TXPOWER_A_FROM_DEV(tx_power1[i]);
2984                         info[i].tx_power2 = TXPOWER_A_FROM_DEV(tx_power2[i]);
2985                 }
2986         }
2987
2988         return 0;
2989 }
2990
2991 static const struct rt2800_ops rt2800pci_rt2800_ops = {
2992         .register_read          = rt2x00pci_register_read,
2993         .register_write         = rt2x00pci_register_write,
2994         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
2995
2996         .register_multiread     = rt2x00pci_register_multiread,
2997         .register_multiwrite    = rt2x00pci_register_multiwrite,
2998
2999         .regbusy_read           = rt2x00pci_regbusy_read,
3000 };
3001
3002 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
3003 {
3004         int retval;
3005
3006         rt2x00dev->priv = (void *)&rt2800pci_rt2800_ops;
3007
3008         /*
3009          * Allocate eeprom data.
3010          */
3011         retval = rt2800pci_validate_eeprom(rt2x00dev);
3012         if (retval)
3013                 return retval;
3014
3015         retval = rt2800pci_init_eeprom(rt2x00dev);
3016         if (retval)
3017                 return retval;
3018
3019         /*
3020          * Initialize hw specifications.
3021          */
3022         retval = rt2800pci_probe_hw_mode(rt2x00dev);
3023         if (retval)
3024                 return retval;
3025
3026         /*
3027          * This device has multiple filters for control frames
3028          * and has a separate filter for PS Poll frames.
3029          */
3030         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
3031         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
3032
3033         /*
3034          * This device requires firmware.
3035          */
3036         if (!rt2x00_rt(&rt2x00dev->chip, RT2880) &&
3037             !rt2x00_rt(&rt2x00dev->chip, RT3052))
3038                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
3039         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
3040         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
3041         if (!modparam_nohwcrypt)
3042                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
3043
3044         /*
3045          * Set the rssi offset.
3046          */
3047         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
3048
3049         return 0;
3050 }
3051
3052 /*
3053  * IEEE80211 stack callback functions.
3054  */
3055 static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
3056                                    u32 *iv32, u16 *iv16)
3057 {
3058         struct rt2x00_dev *rt2x00dev = hw->priv;
3059         struct mac_iveiv_entry iveiv_entry;
3060         u32 offset;
3061
3062         offset = MAC_IVEIV_ENTRY(hw_key_idx);
3063         rt2800_register_multiread(rt2x00dev, offset,
3064                                       &iveiv_entry, sizeof(iveiv_entry));
3065
3066         memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
3067         memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
3068 }
3069
3070 static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
3071 {
3072         struct rt2x00_dev *rt2x00dev = hw->priv;
3073         u32 reg;
3074         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
3075
3076         rt2800_register_read(rt2x00dev, TX_RTS_CFG, &reg);
3077         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
3078         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3079
3080         rt2800_register_read(rt2x00dev, CCK_PROT_CFG, &reg);
3081         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
3082         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3083
3084         rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, &reg);
3085         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
3086         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3087
3088         rt2800_register_read(rt2x00dev, MM20_PROT_CFG, &reg);
3089         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
3090         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3091
3092         rt2800_register_read(rt2x00dev, MM40_PROT_CFG, &reg);
3093         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
3094         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3095
3096         rt2800_register_read(rt2x00dev, GF20_PROT_CFG, &reg);
3097         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
3098         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3099
3100         rt2800_register_read(rt2x00dev, GF40_PROT_CFG, &reg);
3101         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
3102         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3103
3104         return 0;
3105 }
3106
3107 static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
3108                              const struct ieee80211_tx_queue_params *params)
3109 {
3110         struct rt2x00_dev *rt2x00dev = hw->priv;
3111         struct data_queue *queue;
3112         struct rt2x00_field32 field;
3113         int retval;
3114         u32 reg;
3115         u32 offset;
3116
3117         /*
3118          * First pass the configuration through rt2x00lib, that will
3119          * update the queue settings and validate the input. After that
3120          * we are free to update the registers based on the value
3121          * in the queue parameter.
3122          */
3123         retval = rt2x00mac_conf_tx(hw, queue_idx, params);
3124         if (retval)
3125                 return retval;
3126
3127         /*
3128          * We only need to perform additional register initialization
3129          * for WMM queues/
3130          */
3131         if (queue_idx >= 4)
3132                 return 0;
3133
3134         queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
3135
3136         /* Update WMM TXOP register */
3137         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
3138         field.bit_offset = (queue_idx & 1) * 16;
3139         field.bit_mask = 0xffff << field.bit_offset;
3140
3141         rt2800_register_read(rt2x00dev, offset, &reg);
3142         rt2x00_set_field32(&reg, field, queue->txop);
3143         rt2800_register_write(rt2x00dev, offset, reg);
3144
3145         /* Update WMM registers */
3146         field.bit_offset = queue_idx * 4;
3147         field.bit_mask = 0xf << field.bit_offset;
3148
3149         rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, &reg);
3150         rt2x00_set_field32(&reg, field, queue->aifs);
3151         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
3152
3153         rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, &reg);
3154         rt2x00_set_field32(&reg, field, queue->cw_min);
3155         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
3156
3157         rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, &reg);
3158         rt2x00_set_field32(&reg, field, queue->cw_max);
3159         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
3160
3161         /* Update EDCA registers */
3162         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
3163
3164         rt2800_register_read(rt2x00dev, offset, &reg);
3165         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
3166         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
3167         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
3168         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
3169         rt2800_register_write(rt2x00dev, offset, reg);
3170
3171         return 0;
3172 }
3173
3174 static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
3175 {
3176         struct rt2x00_dev *rt2x00dev = hw->priv;
3177         u64 tsf;
3178         u32 reg;
3179
3180         rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, &reg);
3181         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
3182         rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, &reg);
3183         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
3184
3185         return tsf;
3186 }
3187
3188 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
3189         .tx                     = rt2x00mac_tx,
3190         .start                  = rt2x00mac_start,
3191         .stop                   = rt2x00mac_stop,
3192         .add_interface          = rt2x00mac_add_interface,
3193         .remove_interface       = rt2x00mac_remove_interface,
3194         .config                 = rt2x00mac_config,
3195         .configure_filter       = rt2x00mac_configure_filter,
3196         .set_key                = rt2x00mac_set_key,
3197         .get_stats              = rt2x00mac_get_stats,
3198         .get_tkip_seq           = rt2800pci_get_tkip_seq,
3199         .set_rts_threshold      = rt2800pci_set_rts_threshold,
3200         .bss_info_changed       = rt2x00mac_bss_info_changed,
3201         .conf_tx                = rt2800pci_conf_tx,
3202         .get_tx_stats           = rt2x00mac_get_tx_stats,
3203         .get_tsf                = rt2800pci_get_tsf,
3204         .rfkill_poll            = rt2x00mac_rfkill_poll,
3205 };
3206
3207 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
3208         .irq_handler            = rt2800pci_interrupt,
3209         .probe_hw               = rt2800pci_probe_hw,
3210         .get_firmware_name      = rt2800pci_get_firmware_name,
3211         .check_firmware         = rt2800pci_check_firmware,
3212         .load_firmware          = rt2800pci_load_firmware,
3213         .initialize             = rt2x00pci_initialize,
3214         .uninitialize           = rt2x00pci_uninitialize,
3215         .get_entry_state        = rt2800pci_get_entry_state,
3216         .clear_entry            = rt2800pci_clear_entry,
3217         .set_device_state       = rt2800pci_set_device_state,
3218         .rfkill_poll            = rt2800pci_rfkill_poll,
3219         .link_stats             = rt2800pci_link_stats,
3220         .reset_tuner            = rt2800pci_reset_tuner,
3221         .link_tuner             = rt2800pci_link_tuner,
3222         .write_tx_desc          = rt2800pci_write_tx_desc,
3223         .write_tx_data          = rt2x00pci_write_tx_data,
3224         .write_beacon           = rt2800pci_write_beacon,
3225         .kick_tx_queue          = rt2800pci_kick_tx_queue,
3226         .kill_tx_queue          = rt2800pci_kill_tx_queue,
3227         .fill_rxdone            = rt2800pci_fill_rxdone,
3228         .config_shared_key      = rt2800pci_config_shared_key,
3229         .config_pairwise_key    = rt2800pci_config_pairwise_key,
3230         .config_filter          = rt2800pci_config_filter,
3231         .config_intf            = rt2800pci_config_intf,
3232         .config_erp             = rt2800pci_config_erp,
3233         .config_ant             = rt2800pci_config_ant,
3234         .config                 = rt2800pci_config,
3235 };
3236
3237 static const struct data_queue_desc rt2800pci_queue_rx = {
3238         .entry_num              = RX_ENTRIES,
3239         .data_size              = AGGREGATION_SIZE,
3240         .desc_size              = RXD_DESC_SIZE,
3241         .priv_size              = sizeof(struct queue_entry_priv_pci),
3242 };
3243
3244 static const struct data_queue_desc rt2800pci_queue_tx = {
3245         .entry_num              = TX_ENTRIES,
3246         .data_size              = AGGREGATION_SIZE,
3247         .desc_size              = TXD_DESC_SIZE,
3248         .priv_size              = sizeof(struct queue_entry_priv_pci),
3249 };
3250
3251 static const struct data_queue_desc rt2800pci_queue_bcn = {
3252         .entry_num              = 8 * BEACON_ENTRIES,
3253         .data_size              = 0, /* No DMA required for beacons */
3254         .desc_size              = TXWI_DESC_SIZE,
3255         .priv_size              = sizeof(struct queue_entry_priv_pci),
3256 };
3257
3258 static const struct rt2x00_ops rt2800pci_ops = {
3259         .name           = KBUILD_MODNAME,
3260         .max_sta_intf   = 1,
3261         .max_ap_intf    = 8,
3262         .eeprom_size    = EEPROM_SIZE,
3263         .rf_size        = RF_SIZE,
3264         .tx_queues      = NUM_TX_QUEUES,
3265         .rx             = &rt2800pci_queue_rx,
3266         .tx             = &rt2800pci_queue_tx,
3267         .bcn            = &rt2800pci_queue_bcn,
3268         .lib            = &rt2800pci_rt2x00_ops,
3269         .hw             = &rt2800pci_mac80211_ops,
3270 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
3271         .debugfs        = &rt2800pci_rt2x00debug,
3272 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
3273 };
3274
3275 /*
3276  * RT2800pci module information.
3277  */
3278 static struct pci_device_id rt2800pci_device_table[] = {
3279         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
3280         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
3281         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
3282         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
3283         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
3284         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
3285         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
3286         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
3287         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
3288         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
3289         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
3290         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
3291         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
3292         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
3293         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
3294         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
3295         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
3296         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
3297         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
3298         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
3299         { 0, }
3300 };
3301
3302 MODULE_AUTHOR(DRV_PROJECT);
3303 MODULE_VERSION(DRV_VERSION);
3304 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
3305 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
3306 #ifdef CONFIG_RT2800PCI_PCI
3307 MODULE_FIRMWARE(FIRMWARE_RT2860);
3308 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
3309 #endif /* CONFIG_RT2800PCI_PCI */
3310 MODULE_LICENSE("GPL");
3311
3312 #ifdef CONFIG_RT2800PCI_WISOC
3313 #if defined(CONFIG_RALINK_RT288X)
3314 __rt2x00soc_probe(RT2880, &rt2800pci_ops);
3315 #elif defined(CONFIG_RALINK_RT305X)
3316 __rt2x00soc_probe(RT3052, &rt2800pci_ops);
3317 #endif
3318
3319 static struct platform_driver rt2800soc_driver = {
3320         .driver         = {
3321                 .name           = "rt2800_wmac",
3322                 .owner          = THIS_MODULE,
3323                 .mod_name       = KBUILD_MODNAME,
3324         },
3325         .probe          = __rt2x00soc_probe,
3326         .remove         = __devexit_p(rt2x00soc_remove),
3327         .suspend        = rt2x00soc_suspend,
3328         .resume         = rt2x00soc_resume,
3329 };
3330 #endif /* CONFIG_RT2800PCI_WISOC */
3331
3332 #ifdef CONFIG_RT2800PCI_PCI
3333 static struct pci_driver rt2800pci_driver = {
3334         .name           = KBUILD_MODNAME,
3335         .id_table       = rt2800pci_device_table,
3336         .probe          = rt2x00pci_probe,
3337         .remove         = __devexit_p(rt2x00pci_remove),
3338         .suspend        = rt2x00pci_suspend,
3339         .resume         = rt2x00pci_resume,
3340 };
3341 #endif /* CONFIG_RT2800PCI_PCI */
3342
3343 static int __init rt2800pci_init(void)
3344 {
3345         int ret = 0;
3346
3347 #ifdef CONFIG_RT2800PCI_WISOC
3348         ret = platform_driver_register(&rt2800soc_driver);
3349         if (ret)
3350                 return ret;
3351 #endif
3352 #ifdef CONFIG_RT2800PCI_PCI
3353         ret = pci_register_driver(&rt2800pci_driver);
3354         if (ret) {
3355 #ifdef CONFIG_RT2800PCI_WISOC
3356                 platform_driver_unregister(&rt2800soc_driver);
3357 #endif
3358                 return ret;
3359         }
3360 #endif
3361
3362         return ret;
3363 }
3364
3365 static void __exit rt2800pci_exit(void)
3366 {
3367 #ifdef CONFIG_RT2800PCI_PCI
3368         pci_unregister_driver(&rt2800pci_driver);
3369 #endif
3370 #ifdef CONFIG_RT2800PCI_WISOC
3371         platform_driver_unregister(&rt2800soc_driver);
3372 #endif
3373 }
3374
3375 module_init(rt2800pci_init);
3376 module_exit(rt2800pci_exit);