drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10         <http://rt2x00.serialmonkey.com>
  11
  12         This program is free software; you can redistribute it and/or modify
  13         it under the terms of the GNU General Public License as published by
  14         the Free Software Foundation; either version 2 of the License, or
  15         (at your option) any later version.
  16
  17         This program is distributed in the hope that it will be useful,
  18         but WITHOUT ANY WARRANTY; without even the implied warranty of
  19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20         GNU General Public License for more details.
  21
  22         You should have received a copy of the GNU General Public License
  23         along with this program; if not, write to the
  24         Free Software Foundation, Inc.,
  25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  */
  27
  28 /*
  29         Module: rt2800pci
  30         Abstract: rt2800pci device specific routines.
  31         Supported chipsets: RT2800E & RT2800ED.
  32  */
  33
  34 #include <linux/delay.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/init.h>
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/pci.h>
  40 #include <linux/platform_device.h>
  41 #include <linux/eeprom_93cx6.h>
  42
  43 #include "rt2x00.h"
  44 #include "rt2x00pci.h"
  45 #include "rt2x00soc.h"
  46 #include "rt2800lib.h"
  47 #include "rt2800.h"
  48 #include "rt2800pci.h"
  49
  50 /*
  51  * Allow hardware encryption to be disabled.
  52  */
  53 static bool modparam_nohwcrypt = false;
  54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  56
  57 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  58 {
  59         unsigned int i;
  60         u32 reg;
  61
  62         /*
  63          * SOC devices don't support MCU requests.
  64          */
  65         if (rt2x00_is_soc(rt2x00dev))
  66                 return;
  67
  68         for (i = 0; i < 200; i++) {
  69                 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  70
  71                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  72                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  73                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  74                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  75                         break;
  76
  77                 udelay(REGISTER_BUSY_DELAY);
  78         }
  79
  80         if (i == 200)
  81                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  82
  83         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  84         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  85 }
  86
  87 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
  88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  89 {
  90         void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
  91
  92         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  93
  94         iounmap(base_addr);
  95 }
  96 #else
  97 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  98 {
  99 }
 100 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
 101
 102 #ifdef CONFIG_PCI
 103 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 104 {
 105         struct rt2x00_dev *rt2x00dev = eeprom->data;
 106         u32 reg;
 107
 108         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 109
 110         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 111         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 112         eeprom->reg_data_clock =
 113             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 114         eeprom->reg_chip_select =
 115             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 116 }
 117
 118 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 119 {
 120         struct rt2x00_dev *rt2x00dev = eeprom->data;
 121         u32 reg = 0;
 122
 123         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 124         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 125         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 126                            !!eeprom->reg_data_clock);
 127         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 128                            !!eeprom->reg_chip_select);
 129
 130         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 131 }
 132
 133 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 134 {
 135         struct eeprom_93cx6 eeprom;
 136         u32 reg;
 137
 138         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 139
 140         eeprom.data = rt2x00dev;
 141         eeprom.register_read = rt2800pci_eepromregister_read;
 142         eeprom.register_write = rt2800pci_eepromregister_write;
 143         switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
 144         {
 145         case 0:
 146                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
 147                 break;
 148         case 1:
 149                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
 150                 break;
 151         default:
 152                 eeprom.width = PCI_EEPROM_WIDTH_93C86;
 153                 break;
 154         }
 155         eeprom.reg_data_in = 0;
 156         eeprom.reg_data_out = 0;
 157         eeprom.reg_data_clock = 0;
 158         eeprom.reg_chip_select = 0;
 159
 160         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 161                                EEPROM_SIZE / sizeof(u16));
 162 }
 163
 164 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 165 {
 166         return rt2800_efuse_detect(rt2x00dev);
 167 }
 168
 169 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 170 {
 171         rt2800_read_eeprom_efuse(rt2x00dev);
 172 }
 173 #else
 174 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 175 {
 176 }
 177
 178 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 179 {
 180         return 0;
 181 }
 182
 183 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 184 {
 185 }
 186 #endif /* CONFIG_PCI */
 187
 188 /*
 189  * Queue handlers.
 190  */
 191 static void rt2800pci_start_queue(struct data_queue *queue)
 192 {
 193         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 194         u32 reg;
 195
 196         switch (queue->qid) {
 197         case QID_RX:
 198                 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 199                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
 200                 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 201                 break;
 202         case QID_BEACON:
 203                 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 204                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 1);
 205                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 1);
 206                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 1);
 207                 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 208
 209                 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
 210                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
 211                 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
 212                 break;
 213         default:
 214                 break;
 215         }
 216 }
 217
 218 static void rt2800pci_kick_queue(struct data_queue *queue)
 219 {
 220         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 221         struct queue_entry *entry;
 222
 223         switch (queue->qid) {
 224         case QID_AC_VO:
 225         case QID_AC_VI:
 226         case QID_AC_BE:
 227         case QID_AC_BK:
 228                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
 229                 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
 230                                          entry->entry_idx);
 231                 break;
 232         case QID_MGMT:
 233                 entry = rt2x00queue_get_entry(queue, Q_INDEX);
 234                 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
 235                                          entry->entry_idx);
 236                 break;
 237         default:
 238                 break;
 239         }
 240 }
 241
 242 static void rt2800pci_stop_queue(struct data_queue *queue)
 243 {
 244         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 245         u32 reg;
 246
 247         switch (queue->qid) {
 248         case QID_RX:
 249                 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 250                 rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
 251                 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 252                 break;
 253         case QID_BEACON:
 254                 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 255                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
 256                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
 257                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
 258                 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 259
 260                 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, &reg);
 261                 rt2x00_set_field32(&reg, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
 262                 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
 263
 264                 /*
 265                  * Wait for current invocation to finish. The tasklet
 266                  * won't be scheduled anymore afterwards since we disabled
 267                  * the TBTT and PRE TBTT timer.
 268                  */
 269                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
 270                 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
 271
 272                 break;
 273         default:
 274                 break;
 275         }
 276 }
 277
 278 /*
 279  * Firmware functions
 280  */
 281 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 282 {
 283         return FIRMWARE_RT2860;
 284 }
 285
 286 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
 287                                     const u8 *data, const size_t len)
 288 {
 289         u32 reg;
 290
 291         /*
 292          * enable Host program ram write selection
 293          */
 294         reg = 0;
 295         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
 296         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
 297
 298         /*
 299          * Write firmware to device.
 300          */
 301         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 302                                       data, len);
 303
 304         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
 305         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
 306
 307         rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 308         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 309
 310         return 0;
 311 }
 312
 313 /*
 314  * Initialization functions.
 315  */
 316 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
 317 {
 318         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 319         u32 word;
 320
 321         if (entry->queue->qid == QID_RX) {
 322                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 323
 324                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 325         } else {
 326                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 327
 328                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 329         }
 330 }
 331
 332 static void rt2800pci_clear_entry(struct queue_entry *entry)
 333 {
 334         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 335         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 336         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 337         u32 word;
 338
 339         if (entry->queue->qid == QID_RX) {
 340                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 341                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 342                 rt2x00_desc_write(entry_priv->desc, 0, word);
 343
 344                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 345                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 346                 rt2x00_desc_write(entry_priv->desc, 1, word);
 347
 348                 /*
 349                  * Set RX IDX in register to inform hardware that we have
 350                  * handled this entry and it is available for reuse again.
 351                  */
 352                 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
 353                                       entry->entry_idx);
 354         } else {
 355                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 356                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 357                 rt2x00_desc_write(entry_priv->desc, 1, word);
 358         }
 359 }
 360
 361 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 362 {
 363         struct queue_entry_priv_pci *entry_priv;
 364
 365         /*
 366          * Initialize registers.
 367          */
 368         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 369         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
 370         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
 371                                  rt2x00dev->tx[0].limit);
 372         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 373         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 374
 375         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 376         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
 377         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
 378                                  rt2x00dev->tx[1].limit);
 379         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 380         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 381
 382         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 383         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
 384         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
 385                                  rt2x00dev->tx[2].limit);
 386         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 387         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 388
 389         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 390         rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
 391         rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
 392                                  rt2x00dev->tx[3].limit);
 393         rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 394         rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 395
 396         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 397         rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 398         rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
 399                                  rt2x00dev->rx[0].limit);
 400         rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
 401                                  rt2x00dev->rx[0].limit - 1);
 402         rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
 403
 404         rt2800_disable_wpdma(rt2x00dev);
 405
 406         rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 407
 408         return 0;
 409 }
 410
 411 /*
 412  * Device state switch handlers.
 413  */
 414 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 415                                  enum dev_state state)
 416 {
 417         u32 reg;
 418         unsigned long flags;
 419
 420         /*
 421          * When interrupts are being enabled, the interrupt registers
 422          * should clear the register to assure a clean state.
 423          */
 424         if (state == STATE_RADIO_IRQ_ON) {
 425                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 426                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 427         }
 428
 429         spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
 430         reg = 0;
 431         if (state == STATE_RADIO_IRQ_ON) {
 432                 rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, 1);
 433                 rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, 1);
 434                 rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, 1);
 435                 rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, 1);
 436                 rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, 1);
 437         }
 438         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
 439         spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
 440
 441         if (state == STATE_RADIO_IRQ_OFF) {
 442                 /*
 443                  * Wait for possibly running tasklets to finish.
 444                  */
 445                 tasklet_kill(&rt2x00dev->txstatus_tasklet);
 446                 tasklet_kill(&rt2x00dev->rxdone_tasklet);
 447                 tasklet_kill(&rt2x00dev->autowake_tasklet);
 448                 tasklet_kill(&rt2x00dev->tbtt_tasklet);
 449                 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
 450         }
 451 }
 452
 453 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
 454 {
 455         u32 reg;
 456
 457         /*
 458          * Reset DMA indexes
 459          */
 460         rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 461         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 462         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 463         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 464         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 465         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 466         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 467         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 468         rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 469
 470         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 471         rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 472
 473         if (rt2x00_is_pcie(rt2x00dev) &&
 474             (rt2x00_rt(rt2x00dev, RT3572) ||
 475              rt2x00_rt(rt2x00dev, RT5390) ||
 476              rt2x00_rt(rt2x00dev, RT5392))) {
 477                 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, &reg);
 478                 rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 479                 rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 480                 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
 481         }
 482
 483         rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
 484
 485         reg = 0;
 486         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
 487         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
 488         rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 489
 490         rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
 491
 492         return 0;
 493 }
 494
 495 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 496 {
 497         int retval;
 498
 499         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
 500                      rt2800pci_init_queues(rt2x00dev)))
 501                 return -EIO;
 502
 503         retval = rt2800_enable_radio(rt2x00dev);
 504         if (retval)
 505                 return retval;
 506
 507         /* After resume MCU_BOOT_SIGNAL will trash these. */
 508         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
 509         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
 510
 511         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
 512         rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
 513
 514         rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
 515         rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
 516
 517         return retval;
 518 }
 519
 520 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 521 {
 522         if (rt2x00_is_soc(rt2x00dev)) {
 523                 rt2800_disable_radio(rt2x00dev);
 524                 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
 525                 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
 526         }
 527 }
 528
 529 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
 530                                enum dev_state state)
 531 {
 532         if (state == STATE_AWAKE) {
 533                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
 534                                    0, 0x02);
 535                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
 536         } else if (state == STATE_SLEEP) {
 537                 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
 538                                          0xffffffff);
 539                 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
 540                                          0xffffffff);
 541                 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
 542                                    0xff, 0x01);
 543         }
 544
 545         return 0;
 546 }
 547
 548 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 549                                       enum dev_state state)
 550 {
 551         int retval = 0;
 552
 553         switch (state) {
 554         case STATE_RADIO_ON:
 555                 retval = rt2800pci_enable_radio(rt2x00dev);
 556                 break;
 557         case STATE_RADIO_OFF:
 558                 /*
 559                  * After the radio has been disabled, the device should
 560                  * be put to sleep for powersaving.
 561                  */
 562                 rt2800pci_disable_radio(rt2x00dev);
 563                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
 564                 break;
 565         case STATE_RADIO_IRQ_ON:
 566         case STATE_RADIO_IRQ_OFF:
 567                 rt2800pci_toggle_irq(rt2x00dev, state);
 568                 break;
 569         case STATE_DEEP_SLEEP:
 570         case STATE_SLEEP:
 571         case STATE_STANDBY:
 572         case STATE_AWAKE:
 573                 retval = rt2800pci_set_state(rt2x00dev, state);
 574                 break;
 575         default:
 576                 retval = -ENOTSUPP;
 577                 break;
 578         }
 579
 580         if (unlikely(retval))
 581                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 582                       state, retval);
 583
 584         return retval;
 585 }
 586
 587 /*
 588  * TX descriptor initialization
 589  */
 590 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
 591 {
 592         return (__le32 *) entry->skb->data;
 593 }
 594
 595 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
 596                                     struct txentry_desc *txdesc)
 597 {
 598         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 599         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 600         __le32 *txd = entry_priv->desc;
 601         u32 word;
 602
 603         /*
 604          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
 605          * must contains a TXWI structure + 802.11 header + padding + 802.11
 606          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
 607          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
 608          * data. It means that LAST_SEC0 is always 0.
 609          */
 610
 611         /*
 612          * Initialize TX descriptor
 613          */
 614         word = 0;
 615         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
 616         rt2x00_desc_write(txd, 0, word);
 617
 618         word = 0;
 619         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
 620         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
 621                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 622         rt2x00_set_field32(&word, TXD_W1_BURST,
 623                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
 624         rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
 625         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
 626         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
 627         rt2x00_desc_write(txd, 1, word);
 628
 629         word = 0;
 630         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
 631                            skbdesc->skb_dma + TXWI_DESC_SIZE);
 632         rt2x00_desc_write(txd, 2, word);
 633
 634         word = 0;
 635         rt2x00_set_field32(&word, TXD_W3_WIV,
 636                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
 637         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
 638         rt2x00_desc_write(txd, 3, word);
 639
 640         /*
 641          * Register descriptor details in skb frame descriptor.
 642          */
 643         skbdesc->desc = txd;
 644         skbdesc->desc_len = TXD_DESC_SIZE;
 645 }
 646
 647 /*
 648  * RX control handlers
 649  */
 650 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
 651                                   struct rxdone_entry_desc *rxdesc)
 652 {
 653         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 654         __le32 *rxd = entry_priv->desc;
 655         u32 word;
 656
 657         rt2x00_desc_read(rxd, 3, &word);
 658
 659         if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
 660                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 661
 662         /*
 663          * Unfortunately we don't know the cipher type used during
 664          * decryption. This prevents us from correct providing
 665          * correct statistics through debugfs.
 666          */
 667         rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
 668
 669         if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
 670                 /*
 671                  * Hardware has stripped IV/EIV data from 802.11 frame during
 672                  * decryption. Unfortunately the descriptor doesn't contain
 673                  * any fields with the EIV/IV data either, so they can't
 674                  * be restored by rt2x00lib.
 675                  */
 676                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 677
 678                 /*
 679                  * The hardware has already checked the Michael Mic and has
 680                  * stripped it from the frame. Signal this to mac80211.
 681                  */
 682                 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
 683
 684                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 685                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 686                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 687                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 688         }
 689
 690         if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
 691                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 692
 693         if (rt2x00_get_field32(word, RXD_W3_L2PAD))
 694                 rxdesc->dev_flags |= RXDONE_L2PAD;
 695
 696         /*
 697          * Process the RXWI structure that is at the start of the buffer.
 698          */
 699         rt2800_process_rxwi(entry, rxdesc);
 700 }
 701
 702 /*
 703  * Interrupt functions.
 704  */
 705 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
 706 {
 707         struct ieee80211_conf conf = { .flags = 0 };
 708         struct rt2x00lib_conf libconf = { .conf = &conf };
 709
 710         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
 711 }
 712
 713 static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
 714 {
 715         struct data_queue *queue;
 716         struct queue_entry *entry;
 717         u32 status;
 718         u8 qid;
 719         int max_tx_done = 16;
 720
 721         while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
 722                 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
 723                 if (unlikely(qid >= QID_RX)) {
 724                         /*
 725                          * Unknown queue, this shouldn't happen. Just drop
 726                          * this tx status.
 727                          */
 728                         WARNING(rt2x00dev, "Got TX status report with "
 729                                            "unexpected pid %u, dropping\n", qid);
 730                         break;
 731                 }
 732
 733                 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
 734                 if (unlikely(queue == NULL)) {
 735                         /*
 736                          * The queue is NULL, this shouldn't happen. Stop
 737                          * processing here and drop the tx status
 738                          */
 739                         WARNING(rt2x00dev, "Got TX status for an unavailable "
 740                                            "queue %u, dropping\n", qid);
 741                         break;
 742                 }
 743
 744                 if (unlikely(rt2x00queue_empty(queue))) {
 745                         /*
 746                          * The queue is empty. Stop processing here
 747                          * and drop the tx status.
 748                          */
 749                         WARNING(rt2x00dev, "Got TX status for an empty "
 750                                            "queue %u, dropping\n", qid);
 751                         break;
 752                 }
 753
 754                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
 755                 rt2800_txdone_entry(entry, status, rt2800pci_get_txwi(entry));
 756
 757                 if (--max_tx_done == 0)
 758                         break;
 759         }
 760
 761         return !max_tx_done;
 762 }
 763
 764 static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
 765                                               struct rt2x00_field32 irq_field)
 766 {
 767         u32 reg;
 768
 769         /*
 770          * Enable a single interrupt. The interrupt mask register
 771          * access needs locking.
 772          */
 773         spin_lock_irq(&rt2x00dev->irqmask_lock);
 774         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 775         rt2x00_set_field32(&reg, irq_field, 1);
 776         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
 777         spin_unlock_irq(&rt2x00dev->irqmask_lock);
 778 }
 779
 780 static void rt2800pci_txstatus_tasklet(unsigned long data)
 781 {
 782         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 783         if (rt2800pci_txdone(rt2x00dev))
 784                 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
 785
 786         /*
 787          * No need to enable the tx status interrupt here as we always
 788          * leave it enabled to minimize the possibility of a tx status
 789          * register overflow. See comment in interrupt handler.
 790          */
 791 }
 792
 793 static void rt2800pci_pretbtt_tasklet(unsigned long data)
 794 {
 795         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 796         rt2x00lib_pretbtt(rt2x00dev);
 797         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 798                 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
 799 }
 800
 801 static void rt2800pci_tbtt_tasklet(unsigned long data)
 802 {
 803         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 804         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 805         u32 reg;
 806
 807         rt2x00lib_beacondone(rt2x00dev);
 808
 809         if (rt2x00dev->intf_ap_count) {
 810                 /*
 811                  * The rt2800pci hardware tbtt timer is off by 1us per tbtt
 812                  * causing beacon skew and as a result causing problems with
 813                  * some powersaving clients over time. Shorten the beacon
 814                  * interval every 64 beacons by 64us to mitigate this effect.
 815                  */
 816                 if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 2)) {
 817                         rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 818                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 819                                            (rt2x00dev->beacon_int * 16) - 1);
 820                         rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 821                 } else if (drv_data->tbtt_tick == (BCN_TBTT_OFFSET - 1)) {
 822                         rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, &reg);
 823                         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
 824                                            (rt2x00dev->beacon_int * 16));
 825                         rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
 826                 }
 827                 drv_data->tbtt_tick++;
 828                 drv_data->tbtt_tick %= BCN_TBTT_OFFSET;
 829         }
 830
 831         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 832                 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
 833 }
 834
 835 static void rt2800pci_rxdone_tasklet(unsigned long data)
 836 {
 837         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 838         if (rt2x00pci_rxdone(rt2x00dev))
 839                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
 840         else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 841                 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
 842 }
 843
 844 static void rt2800pci_autowake_tasklet(unsigned long data)
 845 {
 846         struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
 847         rt2800pci_wakeup(rt2x00dev);
 848         if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 849                 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
 850 }
 851
 852 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
 853 {
 854         u32 status;
 855         int i;
 856
 857         /*
 858          * The TX_FIFO_STATUS interrupt needs special care. We should
 859          * read TX_STA_FIFO but we should do it immediately as otherwise
 860          * the register can overflow and we would lose status reports.
 861          *
 862          * Hence, read the TX_STA_FIFO register and copy all tx status
 863          * reports into a kernel FIFO which is handled in the txstatus
 864          * tasklet. We use a tasklet to process the tx status reports
 865          * because we can schedule the tasklet multiple times (when the
 866          * interrupt fires again during tx status processing).
 867          *
 868          * Furthermore we don't disable the TX_FIFO_STATUS
 869          * interrupt here but leave it enabled so that the TX_STA_FIFO
 870          * can also be read while the tx status tasklet gets executed.
 871          *
 872          * Since we have only one producer and one consumer we don't
 873          * need to lock the kfifo.
 874          */
 875         for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
 876                 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
 877
 878                 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
 879                         break;
 880
 881                 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
 882                         WARNING(rt2x00dev, "TX status FIFO overrun,"
 883                                 "drop tx status report.\n");
 884                         break;
 885                 }
 886         }
 887
 888         /* Schedule the tasklet for processing the tx status. */
 889         tasklet_schedule(&rt2x00dev->txstatus_tasklet);
 890 }
 891
 892 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
 893 {
 894         struct rt2x00_dev *rt2x00dev = dev_instance;
 895         u32 reg, mask;
 896
 897         /* Read status and ACK all interrupts */
 898         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 899         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 900
 901         if (!reg)
 902                 return IRQ_NONE;
 903
 904         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 905                 return IRQ_HANDLED;
 906
 907         /*
 908          * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
 909          * for interrupts and interrupt masks we can just use the value of
 910          * INT_SOURCE_CSR to create the interrupt mask.
 911          */
 912         mask = ~reg;
 913
 914         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
 915                 rt2800pci_txstatus_interrupt(rt2x00dev);
 916                 /*
 917                  * Never disable the TX_FIFO_STATUS interrupt.
 918                  */
 919                 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
 920         }
 921
 922         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
 923                 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
 924
 925         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
 926                 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
 927
 928         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
 929                 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
 930
 931         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
 932                 tasklet_schedule(&rt2x00dev->autowake_tasklet);
 933
 934         /*
 935          * Disable all interrupts for which a tasklet was scheduled right now,
 936          * the tasklet will reenable the appropriate interrupts.
 937          */
 938         spin_lock(&rt2x00dev->irqmask_lock);
 939         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 940         reg &= mask;
 941         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
 942         spin_unlock(&rt2x00dev->irqmask_lock);
 943
 944         return IRQ_HANDLED;
 945 }
 946
 947 /*
 948  * Device probe functions.
 949  */
 950 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
 951 {
 952         /*
 953          * Read EEPROM into buffer
 954          */
 955         if (rt2x00_is_soc(rt2x00dev))
 956                 rt2800pci_read_eeprom_soc(rt2x00dev);
 957         else if (rt2800pci_efuse_detect(rt2x00dev))
 958                 rt2800pci_read_eeprom_efuse(rt2x00dev);
 959         else
 960                 rt2800pci_read_eeprom_pci(rt2x00dev);
 961
 962         return rt2800_validate_eeprom(rt2x00dev);
 963 }
 964
 965 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
 966 {
 967         int retval;
 968
 969         /*
 970          * Allocate eeprom data.
 971          */
 972         retval = rt2800pci_validate_eeprom(rt2x00dev);
 973         if (retval)
 974                 return retval;
 975
 976         retval = rt2800_init_eeprom(rt2x00dev);
 977         if (retval)
 978                 return retval;
 979
 980         /*
 981          * Initialize hw specifications.
 982          */
 983         retval = rt2800_probe_hw_mode(rt2x00dev);
 984         if (retval)
 985                 return retval;
 986
 987         /*
 988          * This device has multiple filters for control frames
 989          * and has a separate filter for PS Poll frames.
 990          */
 991         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
 992         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
 993
 994         /*
 995          * This device has a pre tbtt interrupt and thus fetches
 996          * a new beacon directly prior to transmission.
 997          */
 998         __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
 999
1000         /*
1001          * This device requires firmware.
1002          */
1003         if (!rt2x00_is_soc(rt2x00dev))
1004                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
1005         __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
1006         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
1007         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
1008         __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
1009         if (!modparam_nohwcrypt)
1010                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
1011         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1012         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
1013
1014         /*
1015          * Set the rssi offset.
1016          */
1017         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1018
1019         return 0;
1020 }
1021
1022 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
1023         .tx                     = rt2x00mac_tx,
1024         .start                  = rt2x00mac_start,
1025         .stop                   = rt2x00mac_stop,
1026         .add_interface          = rt2x00mac_add_interface,
1027         .remove_interface       = rt2x00mac_remove_interface,
1028         .config                 = rt2x00mac_config,
1029         .configure_filter       = rt2x00mac_configure_filter,
1030         .set_key                = rt2x00mac_set_key,
1031         .sw_scan_start          = rt2x00mac_sw_scan_start,
1032         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
1033         .get_stats              = rt2x00mac_get_stats,
1034         .get_tkip_seq           = rt2800_get_tkip_seq,
1035         .set_rts_threshold      = rt2800_set_rts_threshold,
1036         .sta_add                = rt2x00mac_sta_add,
1037         .sta_remove             = rt2x00mac_sta_remove,
1038         .bss_info_changed       = rt2x00mac_bss_info_changed,
1039         .conf_tx                = rt2800_conf_tx,
1040         .get_tsf                = rt2800_get_tsf,
1041         .rfkill_poll            = rt2x00mac_rfkill_poll,
1042         .ampdu_action           = rt2800_ampdu_action,
1043         .flush                  = rt2x00mac_flush,
1044         .get_survey             = rt2800_get_survey,
1045         .get_ringparam          = rt2x00mac_get_ringparam,
1046         .tx_frames_pending      = rt2x00mac_tx_frames_pending,
1047 };
1048
1049 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1050         .register_read          = rt2x00pci_register_read,
1051         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
1052         .register_write         = rt2x00pci_register_write,
1053         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
1054         .register_multiread     = rt2x00pci_register_multiread,
1055         .register_multiwrite    = rt2x00pci_register_multiwrite,
1056         .regbusy_read           = rt2x00pci_regbusy_read,
1057         .drv_write_firmware     = rt2800pci_write_firmware,
1058         .drv_init_registers     = rt2800pci_init_registers,
1059         .drv_get_txwi           = rt2800pci_get_txwi,
1060 };
1061
1062 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1063         .irq_handler            = rt2800pci_interrupt,
1064         .txstatus_tasklet       = rt2800pci_txstatus_tasklet,
1065         .pretbtt_tasklet        = rt2800pci_pretbtt_tasklet,
1066         .tbtt_tasklet           = rt2800pci_tbtt_tasklet,
1067         .rxdone_tasklet         = rt2800pci_rxdone_tasklet,
1068         .autowake_tasklet       = rt2800pci_autowake_tasklet,
1069         .probe_hw               = rt2800pci_probe_hw,
1070         .get_firmware_name      = rt2800pci_get_firmware_name,
1071         .check_firmware         = rt2800_check_firmware,
1072         .load_firmware          = rt2800_load_firmware,
1073         .initialize             = rt2x00pci_initialize,
1074         .uninitialize           = rt2x00pci_uninitialize,
1075         .get_entry_state        = rt2800pci_get_entry_state,
1076         .clear_entry            = rt2800pci_clear_entry,
1077         .set_device_state       = rt2800pci_set_device_state,
1078         .rfkill_poll            = rt2800_rfkill_poll,
1079         .link_stats             = rt2800_link_stats,
1080         .reset_tuner            = rt2800_reset_tuner,
1081         .link_tuner             = rt2800_link_tuner,
1082         .gain_calibration       = rt2800_gain_calibration,
1083         .vco_calibration        = rt2800_vco_calibration,
1084         .start_queue            = rt2800pci_start_queue,
1085         .kick_queue             = rt2800pci_kick_queue,
1086         .stop_queue             = rt2800pci_stop_queue,
1087         .flush_queue            = rt2x00pci_flush_queue,
1088         .write_tx_desc          = rt2800pci_write_tx_desc,
1089         .write_tx_data          = rt2800_write_tx_data,
1090         .write_beacon           = rt2800_write_beacon,
1091         .clear_beacon           = rt2800_clear_beacon,
1092         .fill_rxdone            = rt2800pci_fill_rxdone,
1093         .config_shared_key      = rt2800_config_shared_key,
1094         .config_pairwise_key    = rt2800_config_pairwise_key,
1095         .config_filter          = rt2800_config_filter,
1096         .config_intf            = rt2800_config_intf,
1097         .config_erp             = rt2800_config_erp,
1098         .config_ant             = rt2800_config_ant,
1099         .config                 = rt2800_config,
1100         .sta_add                = rt2800_sta_add,
1101         .sta_remove             = rt2800_sta_remove,
1102 };
1103
1104 static const struct data_queue_desc rt2800pci_queue_rx = {
1105         .entry_num              = 128,
1106         .data_size              = AGGREGATION_SIZE,
1107         .desc_size              = RXD_DESC_SIZE,
1108         .priv_size              = sizeof(struct queue_entry_priv_pci),
1109 };
1110
1111 static const struct data_queue_desc rt2800pci_queue_tx = {
1112         .entry_num              = 64,
1113         .data_size              = AGGREGATION_SIZE,
1114         .desc_size              = TXD_DESC_SIZE,
1115         .priv_size              = sizeof(struct queue_entry_priv_pci),
1116 };
1117
1118 static const struct data_queue_desc rt2800pci_queue_bcn = {
1119         .entry_num              = 8,
1120         .data_size              = 0, /* No DMA required for beacons */
1121         .desc_size              = TXWI_DESC_SIZE,
1122         .priv_size              = sizeof(struct queue_entry_priv_pci),
1123 };
1124
1125 static const struct rt2x00_ops rt2800pci_ops = {
1126         .name                   = KBUILD_MODNAME,
1127         .drv_data_size          = sizeof(struct rt2800_drv_data),
1128         .max_sta_intf           = 1,
1129         .max_ap_intf            = 8,
1130         .eeprom_size            = EEPROM_SIZE,
1131         .rf_size                = RF_SIZE,
1132         .tx_queues              = NUM_TX_QUEUES,
1133         .extra_tx_headroom      = TXWI_DESC_SIZE,
1134         .rx                     = &rt2800pci_queue_rx,
1135         .tx                     = &rt2800pci_queue_tx,
1136         .bcn                    = &rt2800pci_queue_bcn,
1137         .lib                    = &rt2800pci_rt2x00_ops,
1138         .drv                    = &rt2800pci_rt2800_ops,
1139         .hw                     = &rt2800pci_mac80211_ops,
1140 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1141         .debugfs                = &rt2800_rt2x00debug,
1142 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1143 };
1144
1145 /*
1146  * RT2800pci module information.
1147  */
1148 #ifdef CONFIG_PCI
1149 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1150         { PCI_DEVICE(0x1814, 0x0601) },
1151         { PCI_DEVICE(0x1814, 0x0681) },
1152         { PCI_DEVICE(0x1814, 0x0701) },
1153         { PCI_DEVICE(0x1814, 0x0781) },
1154         { PCI_DEVICE(0x1814, 0x3090) },
1155         { PCI_DEVICE(0x1814, 0x3091) },
1156         { PCI_DEVICE(0x1814, 0x3092) },
1157         { PCI_DEVICE(0x1432, 0x7708) },
1158         { PCI_DEVICE(0x1432, 0x7727) },
1159         { PCI_DEVICE(0x1432, 0x7728) },
1160         { PCI_DEVICE(0x1432, 0x7738) },
1161         { PCI_DEVICE(0x1432, 0x7748) },
1162         { PCI_DEVICE(0x1432, 0x7758) },
1163         { PCI_DEVICE(0x1432, 0x7768) },
1164         { PCI_DEVICE(0x1462, 0x891a) },
1165         { PCI_DEVICE(0x1a3b, 0x1059) },
1166 #ifdef CONFIG_RT2800PCI_RT33XX
1167         { PCI_DEVICE(0x1814, 0x3390) },
1168 #endif
1169 #ifdef CONFIG_RT2800PCI_RT35XX
1170         { PCI_DEVICE(0x1432, 0x7711) },
1171         { PCI_DEVICE(0x1432, 0x7722) },
1172         { PCI_DEVICE(0x1814, 0x3060) },
1173         { PCI_DEVICE(0x1814, 0x3062) },
1174         { PCI_DEVICE(0x1814, 0x3562) },
1175         { PCI_DEVICE(0x1814, 0x3592) },
1176         { PCI_DEVICE(0x1814, 0x3593) },
1177 #endif
1178 #ifdef CONFIG_RT2800PCI_RT53XX
1179         { PCI_DEVICE(0x1814, 0x5390) },
1180         { PCI_DEVICE(0x1814, 0x539a) },
1181         { PCI_DEVICE(0x1814, 0x539f) },
1182 #endif
1183         { 0, }
1184 };
1185 #endif /* CONFIG_PCI */
1186
1187 MODULE_AUTHOR(DRV_PROJECT);
1188 MODULE_VERSION(DRV_VERSION);
1189 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1190 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1191 #ifdef CONFIG_PCI
1192 MODULE_FIRMWARE(FIRMWARE_RT2860);
1193 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1194 #endif /* CONFIG_PCI */
1195 MODULE_LICENSE("GPL");
1196
1197 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1198 static int rt2800soc_probe(struct platform_device *pdev)
1199 {
1200         return rt2x00soc_probe(pdev, &rt2800pci_ops);
1201 }
1202
1203 static struct platform_driver rt2800soc_driver = {
1204         .driver         = {
1205                 .name           = "rt2800_wmac",
1206                 .owner          = THIS_MODULE,
1207                 .mod_name       = KBUILD_MODNAME,
1208         },
1209         .probe          = rt2800soc_probe,
1210         .remove         = __devexit_p(rt2x00soc_remove),
1211         .suspend        = rt2x00soc_suspend,
1212         .resume         = rt2x00soc_resume,
1213 };
1214 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1215
1216 #ifdef CONFIG_PCI
1217 static int rt2800pci_probe(struct pci_dev *pci_dev,
1218                            const struct pci_device_id *id)
1219 {
1220         return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1221 }
1222
1223 static struct pci_driver rt2800pci_driver = {
1224         .name           = KBUILD_MODNAME,
1225         .id_table       = rt2800pci_device_table,
1226         .probe          = rt2800pci_probe,
1227         .remove         = __devexit_p(rt2x00pci_remove),
1228         .suspend        = rt2x00pci_suspend,
1229         .resume         = rt2x00pci_resume,
1230 };
1231 #endif /* CONFIG_PCI */
1232
1233 static int __init rt2800pci_init(void)
1234 {
1235         int ret = 0;
1236
1237 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1238         ret = platform_driver_register(&rt2800soc_driver);
1239         if (ret)
1240                 return ret;
1241 #endif
1242 #ifdef CONFIG_PCI
1243         ret = pci_register_driver(&rt2800pci_driver);
1244         if (ret) {
1245 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1246                 platform_driver_unregister(&rt2800soc_driver);
1247 #endif
1248                 return ret;
1249         }
1250 #endif
1251
1252         return ret;
1253 }
1254
1255 static void __exit rt2800pci_exit(void)
1256 {
1257 #ifdef CONFIG_PCI
1258         pci_unregister_driver(&rt2800pci_driver);
1259 #endif
1260 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1261         platform_driver_unregister(&rt2800soc_driver);
1262 #endif
1263 }
1264
1265 module_init(rt2800pci_init);
1266 module_exit(rt2800pci_exit);