drivers/net/wireless/rt2x00/rt2800pci.c

   1 /*
   2         Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
   3         Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   4         Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
   5         Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
   6         Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
   7         Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
   8         Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
   9         Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
  10         <http://rt2x00.serialmonkey.com>
  11
  12         This program is free software; you can redistribute it and/or modify
  13         it under the terms of the GNU General Public License as published by
  14         the Free Software Foundation; either version 2 of the License, or
  15         (at your option) any later version.
  16
  17         This program is distributed in the hope that it will be useful,
  18         but WITHOUT ANY WARRANTY; without even the implied warranty of
  19         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20         GNU General Public License for more details.
  21
  22         You should have received a copy of the GNU General Public License
  23         along with this program; if not, write to the
  24         Free Software Foundation, Inc.,
  25         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26  */
  27
  28 /*
  29         Module: rt2800pci
  30         Abstract: rt2800pci device specific routines.
  31         Supported chipsets: RT2800E & RT2800ED.
  32  */
  33
  34 #include <linux/delay.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/init.h>
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/pci.h>
  40 #include <linux/platform_device.h>
  41 #include <linux/eeprom_93cx6.h>
  42
  43 #include "rt2x00.h"
  44 #include "rt2x00pci.h"
  45 #include "rt2x00soc.h"
  46 #include "rt2800lib.h"
  47 #include "rt2800.h"
  48 #include "rt2800pci.h"
  49
  50 /*
  51  * Allow hardware encryption to be disabled.
  52  */
  53 static int modparam_nohwcrypt = 0;
  54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
  55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  56
  57 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
  58 {
  59         unsigned int i;
  60         u32 reg;
  61
  62         /*
  63          * SOC devices don't support MCU requests.
  64          */
  65         if (rt2x00_is_soc(rt2x00dev))
  66                 return;
  67
  68         for (i = 0; i < 200; i++) {
  69                 rt2800_register_read(rt2x00dev, H2M_MAILBOX_CID, &reg);
  70
  71                 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
  72                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
  73                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
  74                     (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
  75                         break;
  76
  77                 udelay(REGISTER_BUSY_DELAY);
  78         }
  79
  80         if (i == 200)
  81                 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
  82
  83         rt2800_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
  84         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
  85 }
  86
  87 #ifdef CONFIG_RT2800PCI_SOC
  88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  89 {
  90         u32 *base_addr = (u32 *) KSEG1ADDR(0x1F040000); /* XXX for RT3052 */
  91
  92         memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
  93 }
  94 #else
  95 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
  96 {
  97 }
  98 #endif /* CONFIG_RT2800PCI_SOC */
  99
 100 #ifdef CONFIG_RT2800PCI_PCI
 101 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 102 {
 103         struct rt2x00_dev *rt2x00dev = eeprom->data;
 104         u32 reg;
 105
 106         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 107
 108         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 109         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 110         eeprom->reg_data_clock =
 111             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 112         eeprom->reg_chip_select =
 113             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 114 }
 115
 116 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 117 {
 118         struct rt2x00_dev *rt2x00dev = eeprom->data;
 119         u32 reg = 0;
 120
 121         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 122         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 123         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 124                            !!eeprom->reg_data_clock);
 125         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 126                            !!eeprom->reg_chip_select);
 127
 128         rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
 129 }
 130
 131 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 132 {
 133         struct eeprom_93cx6 eeprom;
 134         u32 reg;
 135
 136         rt2800_register_read(rt2x00dev, E2PROM_CSR, &reg);
 137
 138         eeprom.data = rt2x00dev;
 139         eeprom.register_read = rt2800pci_eepromregister_read;
 140         eeprom.register_write = rt2800pci_eepromregister_write;
 141         switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
 142         {
 143         case 0:
 144                 eeprom.width = PCI_EEPROM_WIDTH_93C46;
 145                 break;
 146         case 1:
 147                 eeprom.width = PCI_EEPROM_WIDTH_93C66;
 148                 break;
 149         default:
 150                 eeprom.width = PCI_EEPROM_WIDTH_93C86;
 151                 break;
 152         }
 153         eeprom.reg_data_in = 0;
 154         eeprom.reg_data_out = 0;
 155         eeprom.reg_data_clock = 0;
 156         eeprom.reg_chip_select = 0;
 157
 158         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
 159                                EEPROM_SIZE / sizeof(u16));
 160 }
 161
 162 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 163 {
 164         return rt2800_efuse_detect(rt2x00dev);
 165 }
 166
 167 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 168 {
 169         rt2800_read_eeprom_efuse(rt2x00dev);
 170 }
 171 #else
 172 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
 173 {
 174 }
 175
 176 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
 177 {
 178         return 0;
 179 }
 180
 181 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
 182 {
 183 }
 184 #endif /* CONFIG_RT2800PCI_PCI */
 185
 186 /*
 187  * Firmware functions
 188  */
 189 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 190 {
 191         return FIRMWARE_RT2860;
 192 }
 193
 194 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
 195                                     const u8 *data, const size_t len)
 196 {
 197         u32 reg;
 198
 199         /*
 200          * enable Host program ram write selection
 201          */
 202         reg = 0;
 203         rt2x00_set_field32(&reg, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
 204         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
 205
 206         /*
 207          * Write firmware to device.
 208          */
 209         rt2800_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 210                                    data, len);
 211
 212         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
 213         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
 214
 215         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 216         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 217
 218         return 0;
 219 }
 220
 221 /*
 222  * Initialization functions.
 223  */
 224 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
 225 {
 226         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 227         u32 word;
 228
 229         if (entry->queue->qid == QID_RX) {
 230                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 231
 232                 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
 233         } else {
 234                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 235
 236                 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
 237         }
 238 }
 239
 240 static void rt2800pci_clear_entry(struct queue_entry *entry)
 241 {
 242         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 243         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 244         u32 word;
 245
 246         if (entry->queue->qid == QID_RX) {
 247                 rt2x00_desc_read(entry_priv->desc, 0, &word);
 248                 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
 249                 rt2x00_desc_write(entry_priv->desc, 0, word);
 250
 251                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 252                 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
 253                 rt2x00_desc_write(entry_priv->desc, 1, word);
 254         } else {
 255                 rt2x00_desc_read(entry_priv->desc, 1, &word);
 256                 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
 257                 rt2x00_desc_write(entry_priv->desc, 1, word);
 258         }
 259 }
 260
 261 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
 262 {
 263         struct queue_entry_priv_pci *entry_priv;
 264         u32 reg;
 265
 266         /*
 267          * Initialize registers.
 268          */
 269         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 270         rt2800_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
 271         rt2800_register_write(rt2x00dev, TX_MAX_CNT0, rt2x00dev->tx[0].limit);
 272         rt2800_register_write(rt2x00dev, TX_CTX_IDX0, 0);
 273         rt2800_register_write(rt2x00dev, TX_DTX_IDX0, 0);
 274
 275         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 276         rt2800_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
 277         rt2800_register_write(rt2x00dev, TX_MAX_CNT1, rt2x00dev->tx[1].limit);
 278         rt2800_register_write(rt2x00dev, TX_CTX_IDX1, 0);
 279         rt2800_register_write(rt2x00dev, TX_DTX_IDX1, 0);
 280
 281         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
 282         rt2800_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
 283         rt2800_register_write(rt2x00dev, TX_MAX_CNT2, rt2x00dev->tx[2].limit);
 284         rt2800_register_write(rt2x00dev, TX_CTX_IDX2, 0);
 285         rt2800_register_write(rt2x00dev, TX_DTX_IDX2, 0);
 286
 287         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
 288         rt2800_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
 289         rt2800_register_write(rt2x00dev, TX_MAX_CNT3, rt2x00dev->tx[3].limit);
 290         rt2800_register_write(rt2x00dev, TX_CTX_IDX3, 0);
 291         rt2800_register_write(rt2x00dev, TX_DTX_IDX3, 0);
 292
 293         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 294         rt2800_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
 295         rt2800_register_write(rt2x00dev, RX_MAX_CNT, rt2x00dev->rx[0].limit);
 296         rt2800_register_write(rt2x00dev, RX_CRX_IDX, rt2x00dev->rx[0].limit - 1);
 297         rt2800_register_write(rt2x00dev, RX_DRX_IDX, 0);
 298
 299         /*
 300          * Enable global DMA configuration
 301          */
 302         rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, &reg);
 303         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 304         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 305         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 306         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 307
 308         rt2800_register_write(rt2x00dev, DELAY_INT_CFG, 0);
 309
 310         return 0;
 311 }
 312
 313 /*
 314  * Device state switch handlers.
 315  */
 316 static void rt2800pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 317                                 enum dev_state state)
 318 {
 319         u32 reg;
 320
 321         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 322         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX,
 323                            (state == STATE_RADIO_RX_ON) ||
 324                            (state == STATE_RADIO_RX_ON_LINK));
 325         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 326 }
 327
 328 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 329                                  enum dev_state state)
 330 {
 331         int mask = (state == STATE_RADIO_IRQ_ON) ||
 332                    (state == STATE_RADIO_IRQ_ON_ISR);
 333         u32 reg;
 334
 335         /*
 336          * When interrupts are being enabled, the interrupt registers
 337          * should clear the register to assure a clean state.
 338          */
 339         if (state == STATE_RADIO_IRQ_ON) {
 340                 rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 341                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 342         }
 343
 344         rt2800_register_read(rt2x00dev, INT_MASK_CSR, &reg);
 345         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDELAYINT, 0);
 346         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDELAYINT, 0);
 347         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_DONE, mask);
 348         rt2x00_set_field32(&reg, INT_MASK_CSR_AC0_DMA_DONE, 0);
 349         rt2x00_set_field32(&reg, INT_MASK_CSR_AC1_DMA_DONE, 0);
 350         rt2x00_set_field32(&reg, INT_MASK_CSR_AC2_DMA_DONE, 0);
 351         rt2x00_set_field32(&reg, INT_MASK_CSR_AC3_DMA_DONE, 0);
 352         rt2x00_set_field32(&reg, INT_MASK_CSR_HCCA_DMA_DONE, 0);
 353         rt2x00_set_field32(&reg, INT_MASK_CSR_MGMT_DMA_DONE, 0);
 354         rt2x00_set_field32(&reg, INT_MASK_CSR_MCU_COMMAND, 0);
 355         rt2x00_set_field32(&reg, INT_MASK_CSR_RXTX_COHERENT, 0);
 356         rt2x00_set_field32(&reg, INT_MASK_CSR_TBTT, mask);
 357         rt2x00_set_field32(&reg, INT_MASK_CSR_PRE_TBTT, mask);
 358         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_FIFO_STATUS, mask);
 359         rt2x00_set_field32(&reg, INT_MASK_CSR_AUTO_WAKEUP, mask);
 360         rt2x00_set_field32(&reg, INT_MASK_CSR_GPTIMER, 0);
 361         rt2x00_set_field32(&reg, INT_MASK_CSR_RX_COHERENT, 0);
 362         rt2x00_set_field32(&reg, INT_MASK_CSR_TX_COHERENT, 0);
 363         rt2800_register_write(rt2x00dev, INT_MASK_CSR, reg);
 364 }
 365
 366 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
 367 {
 368         u32 reg;
 369
 370         /*
 371          * Reset DMA indexes
 372          */
 373         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 374         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 375         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 376         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 377         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 378         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 379         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 380         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 381         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 382
 383         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 384         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 385
 386         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
 387
 388         rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, &reg);
 389         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_CSR, 1);
 390         rt2x00_set_field32(&reg, MAC_SYS_CTRL_RESET_BBP, 1);
 391         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
 392
 393         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
 394
 395         return 0;
 396 }
 397
 398 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 399 {
 400         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
 401                      rt2800pci_init_queues(rt2x00dev)))
 402                 return -EIO;
 403
 404         return rt2800_enable_radio(rt2x00dev);
 405 }
 406
 407 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 408 {
 409         u32 reg;
 410
 411         rt2800_disable_radio(rt2x00dev);
 412
 413         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001280);
 414
 415         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 416         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, 1);
 417         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, 1);
 418         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, 1);
 419         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, 1);
 420         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX4, 1);
 421         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX5, 1);
 422         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DRX_IDX0, 1);
 423         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 424
 425         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
 426         rt2800_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
 427 }
 428
 429 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
 430                                enum dev_state state)
 431 {
 432         /*
 433          * Always put the device to sleep (even when we intend to wakeup!)
 434          * if the device is booting and wasn't asleep it will return
 435          * failure when attempting to wakeup.
 436          */
 437         rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 2);
 438
 439         if (state == STATE_AWAKE) {
 440                 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0);
 441                 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
 442         }
 443
 444         return 0;
 445 }
 446
 447 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 448                                       enum dev_state state)
 449 {
 450         int retval = 0;
 451
 452         switch (state) {
 453         case STATE_RADIO_ON:
 454                 /*
 455                  * Before the radio can be enabled, the device first has
 456                  * to be woken up. After that it needs a bit of time
 457                  * to be fully awake and then the radio can be enabled.
 458                  */
 459                 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
 460                 msleep(1);
 461                 retval = rt2800pci_enable_radio(rt2x00dev);
 462                 break;
 463         case STATE_RADIO_OFF:
 464                 /*
 465                  * After the radio has been disabled, the device should
 466                  * be put to sleep for powersaving.
 467                  */
 468                 rt2800pci_disable_radio(rt2x00dev);
 469                 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
 470                 break;
 471         case STATE_RADIO_RX_ON:
 472         case STATE_RADIO_RX_ON_LINK:
 473         case STATE_RADIO_RX_OFF:
 474         case STATE_RADIO_RX_OFF_LINK:
 475                 rt2800pci_toggle_rx(rt2x00dev, state);
 476                 break;
 477         case STATE_RADIO_IRQ_ON:
 478         case STATE_RADIO_IRQ_ON_ISR:
 479         case STATE_RADIO_IRQ_OFF:
 480         case STATE_RADIO_IRQ_OFF_ISR:
 481                 rt2800pci_toggle_irq(rt2x00dev, state);
 482                 break;
 483         case STATE_DEEP_SLEEP:
 484         case STATE_SLEEP:
 485         case STATE_STANDBY:
 486         case STATE_AWAKE:
 487                 retval = rt2800pci_set_state(rt2x00dev, state);
 488                 break;
 489         default:
 490                 retval = -ENOTSUPP;
 491                 break;
 492         }
 493
 494         if (unlikely(retval))
 495                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 496                       state, retval);
 497
 498         return retval;
 499 }
 500
 501 /*
 502  * TX descriptor initialization
 503  */
 504 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
 505 {
 506         return (__le32 *) entry->skb->data;
 507 }
 508
 509 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
 510                                     struct txentry_desc *txdesc)
 511 {
 512         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 513         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 514         __le32 *txd = entry_priv->desc;
 515         u32 word;
 516
 517         /*
 518          * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
 519          * must contains a TXWI structure + 802.11 header + padding + 802.11
 520          * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
 521          * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
 522          * data. It means that LAST_SEC0 is always 0.
 523          */
 524
 525         /*
 526          * Initialize TX descriptor
 527          */
 528         rt2x00_desc_read(txd, 0, &word);
 529         rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
 530         rt2x00_desc_write(txd, 0, word);
 531
 532         rt2x00_desc_read(txd, 1, &word);
 533         rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
 534         rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
 535                            !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 536         rt2x00_set_field32(&word, TXD_W1_BURST,
 537                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
 538         rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
 539         rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
 540         rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
 541         rt2x00_desc_write(txd, 1, word);
 542
 543         rt2x00_desc_read(txd, 2, &word);
 544         rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
 545                            skbdesc->skb_dma + TXWI_DESC_SIZE);
 546         rt2x00_desc_write(txd, 2, word);
 547
 548         rt2x00_desc_read(txd, 3, &word);
 549         rt2x00_set_field32(&word, TXD_W3_WIV,
 550                            !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
 551         rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
 552         rt2x00_desc_write(txd, 3, word);
 553
 554         /*
 555          * Register descriptor details in skb frame descriptor.
 556          */
 557         skbdesc->desc = txd;
 558         skbdesc->desc_len = TXD_DESC_SIZE;
 559 }
 560
 561 /*
 562  * TX data initialization
 563  */
 564 static void rt2800pci_kick_tx_queue(struct data_queue *queue)
 565 {
 566         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 567         struct queue_entry *entry = rt2x00queue_get_entry(queue, Q_INDEX);
 568         unsigned int qidx = 0;
 569
 570         if (queue->qid == QID_MGMT)
 571                 qidx = 5;
 572         else
 573                 qidx = queue->qid;
 574
 575         rt2800_register_write(rt2x00dev, TX_CTX_IDX(qidx), entry->entry_idx);
 576 }
 577
 578 static void rt2800pci_kill_tx_queue(struct data_queue *queue)
 579 {
 580         struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
 581         u32 reg;
 582
 583         if (queue->qid == QID_BEACON) {
 584                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, 0);
 585                 return;
 586         }
 587
 588         rt2800_register_read(rt2x00dev, WPDMA_RST_IDX, &reg);
 589         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX0, (queue->qid == QID_AC_BE));
 590         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX1, (queue->qid == QID_AC_BK));
 591         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX2, (queue->qid == QID_AC_VI));
 592         rt2x00_set_field32(&reg, WPDMA_RST_IDX_DTX_IDX3, (queue->qid == QID_AC_VO));
 593         rt2800_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
 594 }
 595
 596 /*
 597  * RX control handlers
 598  */
 599 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
 600                                   struct rxdone_entry_desc *rxdesc)
 601 {
 602         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 603         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 604         __le32 *rxd = entry_priv->desc;
 605         u32 word;
 606
 607         rt2x00_desc_read(rxd, 3, &word);
 608
 609         if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
 610                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
 611
 612         /*
 613          * Unfortunately we don't know the cipher type used during
 614          * decryption. This prevents us from correct providing
 615          * correct statistics through debugfs.
 616          */
 617         rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
 618
 619         if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
 620                 /*
 621                  * Hardware has stripped IV/EIV data from 802.11 frame during
 622                  * decryption. Unfortunately the descriptor doesn't contain
 623                  * any fields with the EIV/IV data either, so they can't
 624                  * be restored by rt2x00lib.
 625                  */
 626                 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
 627
 628                 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
 629                         rxdesc->flags |= RX_FLAG_DECRYPTED;
 630                 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
 631                         rxdesc->flags |= RX_FLAG_MMIC_ERROR;
 632         }
 633
 634         if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
 635                 rxdesc->dev_flags |= RXDONE_MY_BSS;
 636
 637         if (rt2x00_get_field32(word, RXD_W3_L2PAD))
 638                 rxdesc->dev_flags |= RXDONE_L2PAD;
 639
 640         /*
 641          * Process the RXWI structure that is at the start of the buffer.
 642          */
 643         rt2800_process_rxwi(entry, rxdesc);
 644
 645         /*
 646          * Set RX IDX in register to inform hardware that we have handled
 647          * this entry and it is available for reuse again.
 648          */
 649         rt2800_register_write(rt2x00dev, RX_CRX_IDX, entry->entry_idx);
 650 }
 651
 652 /*
 653  * Interrupt functions.
 654  */
 655 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
 656 {
 657         struct ieee80211_conf conf = { .flags = 0 };
 658         struct rt2x00lib_conf libconf = { .conf = &conf };
 659
 660         rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
 661 }
 662
 663 static irqreturn_t rt2800pci_interrupt_thread(int irq, void *dev_instance)
 664 {
 665         struct rt2x00_dev *rt2x00dev = dev_instance;
 666         u32 reg = rt2x00dev->irqvalue[0];
 667
 668         /*
 669          * 1 - Pre TBTT interrupt.
 670          */
 671         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
 672                 rt2x00lib_pretbtt(rt2x00dev);
 673
 674         /*
 675          * 2 - Beacondone interrupt.
 676          */
 677         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
 678                 rt2x00lib_beacondone(rt2x00dev);
 679
 680         /*
 681          * 3 - Rx ring done interrupt.
 682          */
 683         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
 684                 rt2x00pci_rxdone(rt2x00dev);
 685
 686         /*
 687          * 4 - Tx done interrupt.
 688          */
 689         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS))
 690                 rt2800_txdone(rt2x00dev);
 691
 692         /*
 693          * 5 - Auto wakeup interrupt.
 694          */
 695         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
 696                 rt2800pci_wakeup(rt2x00dev);
 697
 698         /* Enable interrupts again. */
 699         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
 700                                               STATE_RADIO_IRQ_ON_ISR);
 701
 702         return IRQ_HANDLED;
 703 }
 704
 705 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
 706 {
 707         struct rt2x00_dev *rt2x00dev = dev_instance;
 708         u32 reg;
 709
 710         /* Read status and ACK all interrupts */
 711         rt2800_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
 712         rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
 713
 714         if (!reg)
 715                 return IRQ_NONE;
 716
 717         if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
 718                 return IRQ_HANDLED;
 719
 720         /* Store irqvalue for use in the interrupt thread. */
 721         rt2x00dev->irqvalue[0] = reg;
 722
 723         /* Disable interrupts, will be enabled again in the interrupt thread. */
 724         rt2x00dev->ops->lib->set_device_state(rt2x00dev,
 725                                               STATE_RADIO_IRQ_OFF_ISR);
 726
 727
 728         return IRQ_WAKE_THREAD;
 729 }
 730
 731 /*
 732  * Device probe functions.
 733  */
 734 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
 735 {
 736         /*
 737          * Read EEPROM into buffer
 738          */
 739         if (rt2x00_is_soc(rt2x00dev))
 740                 rt2800pci_read_eeprom_soc(rt2x00dev);
 741         else if (rt2800pci_efuse_detect(rt2x00dev))
 742                 rt2800pci_read_eeprom_efuse(rt2x00dev);
 743         else
 744                 rt2800pci_read_eeprom_pci(rt2x00dev);
 745
 746         return rt2800_validate_eeprom(rt2x00dev);
 747 }
 748
 749 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
 750 {
 751         int retval;
 752
 753         /*
 754          * Allocate eeprom data.
 755          */
 756         retval = rt2800pci_validate_eeprom(rt2x00dev);
 757         if (retval)
 758                 return retval;
 759
 760         retval = rt2800_init_eeprom(rt2x00dev);
 761         if (retval)
 762                 return retval;
 763
 764         /*
 765          * Initialize hw specifications.
 766          */
 767         retval = rt2800_probe_hw_mode(rt2x00dev);
 768         if (retval)
 769                 return retval;
 770
 771         /*
 772          * This device has multiple filters for control frames
 773          * and has a separate filter for PS Poll frames.
 774          */
 775         __set_bit(DRIVER_SUPPORT_CONTROL_FILTERS, &rt2x00dev->flags);
 776         __set_bit(DRIVER_SUPPORT_CONTROL_FILTER_PSPOLL, &rt2x00dev->flags);
 777
 778         /*
 779          * This device has a pre tbtt interrupt and thus fetches
 780          * a new beacon directly prior to transmission.
 781          */
 782         __set_bit(DRIVER_SUPPORT_PRE_TBTT_INTERRUPT, &rt2x00dev->flags);
 783
 784         /*
 785          * This device requires firmware.
 786          */
 787         if (!rt2x00_is_soc(rt2x00dev))
 788                 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
 789         __set_bit(DRIVER_REQUIRE_DMA, &rt2x00dev->flags);
 790         __set_bit(DRIVER_REQUIRE_L2PAD, &rt2x00dev->flags);
 791         if (!modparam_nohwcrypt)
 792                 __set_bit(CONFIG_SUPPORT_HW_CRYPTO, &rt2x00dev->flags);
 793         __set_bit(DRIVER_SUPPORT_LINK_TUNING, &rt2x00dev->flags);
 794
 795         /*
 796          * Set the rssi offset.
 797          */
 798         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
 799
 800         return 0;
 801 }
 802
 803 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
 804         .tx                     = rt2x00mac_tx,
 805         .start                  = rt2x00mac_start,
 806         .stop                   = rt2x00mac_stop,
 807         .add_interface          = rt2x00mac_add_interface,
 808         .remove_interface       = rt2x00mac_remove_interface,
 809         .config                 = rt2x00mac_config,
 810         .configure_filter       = rt2x00mac_configure_filter,
 811         .set_key                = rt2x00mac_set_key,
 812         .sw_scan_start          = rt2x00mac_sw_scan_start,
 813         .sw_scan_complete       = rt2x00mac_sw_scan_complete,
 814         .get_stats              = rt2x00mac_get_stats,
 815         .get_tkip_seq           = rt2800_get_tkip_seq,
 816         .set_rts_threshold      = rt2800_set_rts_threshold,
 817         .bss_info_changed       = rt2x00mac_bss_info_changed,
 818         .conf_tx                = rt2800_conf_tx,
 819         .get_tsf                = rt2800_get_tsf,
 820         .rfkill_poll            = rt2x00mac_rfkill_poll,
 821         .ampdu_action           = rt2800_ampdu_action,
 822 };
 823
 824 static const struct rt2800_ops rt2800pci_rt2800_ops = {
 825         .register_read          = rt2x00pci_register_read,
 826         .register_read_lock     = rt2x00pci_register_read, /* same for PCI */
 827         .register_write         = rt2x00pci_register_write,
 828         .register_write_lock    = rt2x00pci_register_write, /* same for PCI */
 829         .register_multiread     = rt2x00pci_register_multiread,
 830         .register_multiwrite    = rt2x00pci_register_multiwrite,
 831         .regbusy_read           = rt2x00pci_regbusy_read,
 832         .drv_write_firmware     = rt2800pci_write_firmware,
 833         .drv_init_registers     = rt2800pci_init_registers,
 834         .drv_get_txwi           = rt2800pci_get_txwi,
 835 };
 836
 837 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
 838         .irq_handler            = rt2800pci_interrupt,
 839         .irq_handler_thread     = rt2800pci_interrupt_thread,
 840         .probe_hw               = rt2800pci_probe_hw,
 841         .get_firmware_name      = rt2800pci_get_firmware_name,
 842         .check_firmware         = rt2800_check_firmware,
 843         .load_firmware          = rt2800_load_firmware,
 844         .initialize             = rt2x00pci_initialize,
 845         .uninitialize           = rt2x00pci_uninitialize,
 846         .get_entry_state        = rt2800pci_get_entry_state,
 847         .clear_entry            = rt2800pci_clear_entry,
 848         .set_device_state       = rt2800pci_set_device_state,
 849         .rfkill_poll            = rt2800_rfkill_poll,
 850         .link_stats             = rt2800_link_stats,
 851         .reset_tuner            = rt2800_reset_tuner,
 852         .link_tuner             = rt2800_link_tuner,
 853         .write_tx_desc          = rt2800pci_write_tx_desc,
 854         .write_tx_data          = rt2800_write_tx_data,
 855         .write_beacon           = rt2800_write_beacon,
 856         .kick_tx_queue          = rt2800pci_kick_tx_queue,
 857         .kill_tx_queue          = rt2800pci_kill_tx_queue,
 858         .fill_rxdone            = rt2800pci_fill_rxdone,
 859         .config_shared_key      = rt2800_config_shared_key,
 860         .config_pairwise_key    = rt2800_config_pairwise_key,
 861         .config_filter          = rt2800_config_filter,
 862         .config_intf            = rt2800_config_intf,
 863         .config_erp             = rt2800_config_erp,
 864         .config_ant             = rt2800_config_ant,
 865         .config                 = rt2800_config,
 866 };
 867
 868 static const struct data_queue_desc rt2800pci_queue_rx = {
 869         .entry_num              = RX_ENTRIES,
 870         .data_size              = AGGREGATION_SIZE,
 871         .desc_size              = RXD_DESC_SIZE,
 872         .priv_size              = sizeof(struct queue_entry_priv_pci),
 873 };
 874
 875 static const struct data_queue_desc rt2800pci_queue_tx = {
 876         .entry_num              = TX_ENTRIES,
 877         .data_size              = AGGREGATION_SIZE,
 878         .desc_size              = TXD_DESC_SIZE,
 879         .priv_size              = sizeof(struct queue_entry_priv_pci),
 880 };
 881
 882 static const struct data_queue_desc rt2800pci_queue_bcn = {
 883         .entry_num              = 8 * BEACON_ENTRIES,
 884         .data_size              = 0, /* No DMA required for beacons */
 885         .desc_size              = TXWI_DESC_SIZE,
 886         .priv_size              = sizeof(struct queue_entry_priv_pci),
 887 };
 888
 889 static const struct rt2x00_ops rt2800pci_ops = {
 890         .name                   = KBUILD_MODNAME,
 891         .max_sta_intf           = 1,
 892         .max_ap_intf            = 8,
 893         .eeprom_size            = EEPROM_SIZE,
 894         .rf_size                = RF_SIZE,
 895         .tx_queues              = NUM_TX_QUEUES,
 896         .extra_tx_headroom      = TXWI_DESC_SIZE,
 897         .rx                     = &rt2800pci_queue_rx,
 898         .tx                     = &rt2800pci_queue_tx,
 899         .bcn                    = &rt2800pci_queue_bcn,
 900         .lib                    = &rt2800pci_rt2x00_ops,
 901         .drv                    = &rt2800pci_rt2800_ops,
 902         .hw                     = &rt2800pci_mac80211_ops,
 903 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 904         .debugfs                = &rt2800_rt2x00debug,
 905 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 906 };
 907
 908 /*
 909  * RT2800pci module information.
 910  */
 911 #ifdef CONFIG_RT2800PCI_PCI
 912 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
 913         { PCI_DEVICE(0x1814, 0x0601), PCI_DEVICE_DATA(&rt2800pci_ops) },
 914         { PCI_DEVICE(0x1814, 0x0681), PCI_DEVICE_DATA(&rt2800pci_ops) },
 915         { PCI_DEVICE(0x1814, 0x0701), PCI_DEVICE_DATA(&rt2800pci_ops) },
 916         { PCI_DEVICE(0x1814, 0x0781), PCI_DEVICE_DATA(&rt2800pci_ops) },
 917         { PCI_DEVICE(0x1432, 0x7708), PCI_DEVICE_DATA(&rt2800pci_ops) },
 918         { PCI_DEVICE(0x1432, 0x7727), PCI_DEVICE_DATA(&rt2800pci_ops) },
 919         { PCI_DEVICE(0x1432, 0x7728), PCI_DEVICE_DATA(&rt2800pci_ops) },
 920         { PCI_DEVICE(0x1432, 0x7738), PCI_DEVICE_DATA(&rt2800pci_ops) },
 921         { PCI_DEVICE(0x1432, 0x7748), PCI_DEVICE_DATA(&rt2800pci_ops) },
 922         { PCI_DEVICE(0x1432, 0x7758), PCI_DEVICE_DATA(&rt2800pci_ops) },
 923         { PCI_DEVICE(0x1432, 0x7768), PCI_DEVICE_DATA(&rt2800pci_ops) },
 924         { PCI_DEVICE(0x1a3b, 0x1059), PCI_DEVICE_DATA(&rt2800pci_ops) },
 925 #ifdef CONFIG_RT2800PCI_RT30XX
 926         { PCI_DEVICE(0x1814, 0x3090), PCI_DEVICE_DATA(&rt2800pci_ops) },
 927         { PCI_DEVICE(0x1814, 0x3091), PCI_DEVICE_DATA(&rt2800pci_ops) },
 928         { PCI_DEVICE(0x1814, 0x3092), PCI_DEVICE_DATA(&rt2800pci_ops) },
 929         { PCI_DEVICE(0x1462, 0x891a), PCI_DEVICE_DATA(&rt2800pci_ops) },
 930 #endif
 931 #ifdef CONFIG_RT2800PCI_RT35XX
 932         { PCI_DEVICE(0x1814, 0x3060), PCI_DEVICE_DATA(&rt2800pci_ops) },
 933         { PCI_DEVICE(0x1814, 0x3062), PCI_DEVICE_DATA(&rt2800pci_ops) },
 934         { PCI_DEVICE(0x1814, 0x3562), PCI_DEVICE_DATA(&rt2800pci_ops) },
 935         { PCI_DEVICE(0x1814, 0x3592), PCI_DEVICE_DATA(&rt2800pci_ops) },
 936         { PCI_DEVICE(0x1814, 0x3593), PCI_DEVICE_DATA(&rt2800pci_ops) },
 937 #endif
 938         { 0, }
 939 };
 940 #endif /* CONFIG_RT2800PCI_PCI */
 941
 942 MODULE_AUTHOR(DRV_PROJECT);
 943 MODULE_VERSION(DRV_VERSION);
 944 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
 945 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
 946 #ifdef CONFIG_RT2800PCI_PCI
 947 MODULE_FIRMWARE(FIRMWARE_RT2860);
 948 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
 949 #endif /* CONFIG_RT2800PCI_PCI */
 950 MODULE_LICENSE("GPL");
 951
 952 #ifdef CONFIG_RT2800PCI_SOC
 953 static int rt2800soc_probe(struct platform_device *pdev)
 954 {
 955         return rt2x00soc_probe(pdev, &rt2800pci_ops);
 956 }
 957
 958 static struct platform_driver rt2800soc_driver = {
 959         .driver         = {
 960                 .name           = "rt2800_wmac",
 961                 .owner          = THIS_MODULE,
 962                 .mod_name       = KBUILD_MODNAME,
 963         },
 964         .probe          = rt2800soc_probe,
 965         .remove         = __devexit_p(rt2x00soc_remove),
 966         .suspend        = rt2x00soc_suspend,
 967         .resume         = rt2x00soc_resume,
 968 };
 969 #endif /* CONFIG_RT2800PCI_SOC */
 970
 971 #ifdef CONFIG_RT2800PCI_PCI
 972 static struct pci_driver rt2800pci_driver = {
 973         .name           = KBUILD_MODNAME,
 974         .id_table       = rt2800pci_device_table,
 975         .probe          = rt2x00pci_probe,
 976         .remove         = __devexit_p(rt2x00pci_remove),
 977         .suspend        = rt2x00pci_suspend,
 978         .resume         = rt2x00pci_resume,
 979 };
 980 #endif /* CONFIG_RT2800PCI_PCI */
 981
 982 static int __init rt2800pci_init(void)
 983 {
 984         int ret = 0;
 985
 986 #ifdef CONFIG_RT2800PCI_SOC
 987         ret = platform_driver_register(&rt2800soc_driver);
 988         if (ret)
 989                 return ret;
 990 #endif
 991 #ifdef CONFIG_RT2800PCI_PCI
 992         ret = pci_register_driver(&rt2800pci_driver);
 993         if (ret) {
 994 #ifdef CONFIG_RT2800PCI_SOC
 995                 platform_driver_unregister(&rt2800soc_driver);
 996 #endif
 997                 return ret;
 998         }
 999 #endif
1000
1001         return ret;
1002 }
1003
1004 static void __exit rt2800pci_exit(void)
1005 {
1006 #ifdef CONFIG_RT2800PCI_PCI
1007         pci_unregister_driver(&rt2800pci_driver);
1008 #endif
1009 #ifdef CONFIG_RT2800PCI_SOC
1010         platform_driver_unregister(&rt2800soc_driver);
1011 #endif
1012 }
1013
1014 module_init(rt2800pci_init);
1015 module_exit(rt2800pci_exit);