drivers/net/wireless/iwlwifi/iwl-trans-pcie-rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
   4  *
   5  * Portions of this file are derived from the ipw3945 project, as well
   6  * as portions of the ieee80211 subsystem header files.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of version 2 of the GNU General Public License as
  10  * published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope that it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc.,
  19  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20  *
  21  * The full GNU General Public License is included in this distribution in the
  22  * file called LICENSE.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29 #include <linux/sched.h>
  30 #include <linux/wait.h>
  31 #include <linux/gfp.h>
  32
  33 #include "iwl-prph.h"
  34 #include "iwl-io.h"
  35 #include "iwl-trans-pcie-int.h"
  36 #include "iwl-op-mode.h"
  37
  38 #ifdef CONFIG_IWLWIFI_IDI
  39 #include "iwl-amfh.h"
  40 #endif
  41
  42 /******************************************************************************
  43  *
  44  * RX path functions
  45  *
  46  ******************************************************************************/
  47
  48 /*
  49  * Rx theory of operation
  50  *
  51  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  52  * each of which point to Receive Buffers to be filled by the NIC.  These get
  53  * used not only for Rx frames, but for any command response or notification
  54  * from the NIC.  The driver and NIC manage the Rx buffers by means
  55  * of indexes into the circular buffer.
  56  *
  57  * Rx Queue Indexes
  58  * The host/firmware share two index registers for managing the Rx buffers.
  59  *
  60  * The READ index maps to the first position that the firmware may be writing
  61  * to -- the driver can read up to (but not including) this position and get
  62  * good data.
  63  * The READ index is managed by the firmware once the card is enabled.
  64  *
  65  * The WRITE index maps to the last position the driver has read from -- the
  66  * position preceding WRITE is the last slot the firmware can place a packet.
  67  *
  68  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  69  * WRITE = READ.
  70  *
  71  * During initialization, the host sets up the READ queue position to the first
  72  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  73  *
  74  * When the firmware places a packet in a buffer, it will advance the READ index
  75  * and fire the RX interrupt.  The driver can then query the READ index and
  76  * process as many packets as possible, moving the WRITE index forward as it
  77  * resets the Rx queue buffers with new memory.
  78  *
  79  * The management in the driver is as follows:
  80  * + A list of pre-allocated SKBs is stored in iwl->rxq->rx_free.  When
  81  *   iwl->rxq->free_count drops to or below RX_LOW_WATERMARK, work is scheduled
  82  *   to replenish the iwl->rxq->rx_free.
  83  * + In iwl_rx_replenish (scheduled) if 'processed' != 'read' then the
  84  *   iwl->rxq is replenished and the READ INDEX is updated (updating the
  85  *   'processed' and 'read' driver indexes as well)
  86  * + A received packet is processed and handed to the kernel network stack,
  87  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
  88  * + The Host/Firmware iwl->rxq is replenished at tasklet time from the rx_free
  89  *   list. If there are no allocated buffers in iwl->rxq->rx_free, the READ
  90  *   INDEX is not incremented and iwl->status(RX_STALLED) is set.  If there
  91  *   were enough free buffers and RX_STALLED is set it is cleared.
  92  *
  93  *
  94  * Driver sequence:
  95  *
  96  * iwl_rx_queue_alloc()   Allocates rx_free
  97  * iwl_rx_replenish()     Replenishes rx_free list from rx_used, and calls
  98  *                            iwl_rx_queue_restock
  99  * iwl_rx_queue_restock() Moves available buffers from rx_free into Rx
 100  *                            queue, updates firmware pointers, and updates
 101  *                            the WRITE index.  If insufficient rx_free buffers
 102  *                            are available, schedules iwl_rx_replenish
 103  *
 104  * -- enable interrupts --
 105  * ISR - iwl_rx()         Detach iwl_rx_mem_buffers from pool up to the
 106  *                            READ INDEX, detaching the SKB from the pool.
 107  *                            Moves the packet buffer from queue to rx_used.
 108  *                            Calls iwl_rx_queue_restock to refill any empty
 109  *                            slots.
 110  * ...
 111  *
 112  */
 113
 114 /**
 115  * iwl_rx_queue_space - Return number of free slots available in queue.
 116  */
 117 static int iwl_rx_queue_space(const struct iwl_rx_queue *q)
 118 {
 119         int s = q->read - q->write;
 120         if (s <= 0)
 121                 s += RX_QUEUE_SIZE;
 122         /* keep some buffer to not confuse full and empty queue */
 123         s -= 2;
 124         if (s < 0)
 125                 s = 0;
 126         return s;
 127 }
 128
 129 /**
 130  * iwl_rx_queue_update_write_ptr - Update the write pointer for the RX queue
 131  */
 132 void iwl_rx_queue_update_write_ptr(struct iwl_trans *trans,
 133                         struct iwl_rx_queue *q)
 134 {
 135         unsigned long flags;
 136         u32 reg;
 137
 138         spin_lock_irqsave(&q->lock, flags);
 139
 140         if (q->need_update == 0)
 141                 goto exit_unlock;
 142
 143         if (cfg(trans)->base_params->shadow_reg_enable) {
 144                 /* shadow register enabled */
 145                 /* Device expects a multiple of 8 */
 146                 q->write_actual = (q->write & ~0x7);
 147                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, q->write_actual);
 148         } else {
 149                 struct iwl_trans_pcie *trans_pcie =
 150                         IWL_TRANS_GET_PCIE_TRANS(trans);
 151
 152                 /* If power-saving is in use, make sure device is awake */
 153                 if (test_bit(STATUS_POWER_PMI, &trans_pcie->status)) {
 154                         reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 155
 156                         if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 157                                 IWL_DEBUG_INFO(trans,
 158                                         "Rx queue requesting wakeup,"
 159                                         " GP1 = 0x%x\n", reg);
 160                                 iwl_set_bit(trans, CSR_GP_CNTRL,
 161                                         CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 162                                 goto exit_unlock;
 163                         }
 164
 165                         q->write_actual = (q->write & ~0x7);
 166                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 167                                         q->write_actual);
 168
 169                 /* Else device is assumed to be awake */
 170                 } else {
 171                         /* Device expects a multiple of 8 */
 172                         q->write_actual = (q->write & ~0x7);
 173                         iwl_write_direct32(trans, FH_RSCSR_CHNL0_WPTR,
 174                                 q->write_actual);
 175                 }
 176         }
 177         q->need_update = 0;
 178
 179  exit_unlock:
 180         spin_unlock_irqrestore(&q->lock, flags);
 181 }
 182
 183 /**
 184  * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 185  */
 186 static inline __le32 iwlagn_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 187 {
 188         return cpu_to_le32((u32)(dma_addr >> 8));
 189 }
 190
 191 /**
 192  * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
 193  *
 194  * If there are slots in the RX queue that need to be restocked,
 195  * and we have free pre-allocated buffers, fill the ranks as much
 196  * as we can, pulling from rx_free.
 197  *
 198  * This moves the 'write' index forward to catch up with 'processed', and
 199  * also updates the memory address in the firmware to reference the new
 200  * target buffer.
 201  */
 202 static void iwlagn_rx_queue_restock(struct iwl_trans *trans)
 203 {
 204         struct iwl_trans_pcie *trans_pcie =
 205                 IWL_TRANS_GET_PCIE_TRANS(trans);
 206
 207         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 208         struct list_head *element;
 209         struct iwl_rx_mem_buffer *rxb;
 210         unsigned long flags;
 211
 212         spin_lock_irqsave(&rxq->lock, flags);
 213         while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
 214                 /* The overwritten rxb must be a used one */
 215                 rxb = rxq->queue[rxq->write];
 216                 BUG_ON(rxb && rxb->page);
 217
 218                 /* Get next free Rx buffer, remove from free list */
 219                 element = rxq->rx_free.next;
 220                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 221                 list_del(element);
 222
 223                 /* Point to Rx buffer via next RBD in circular buffer */
 224                 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(rxb->page_dma);
 225                 rxq->queue[rxq->write] = rxb;
 226                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 227                 rxq->free_count--;
 228         }
 229         spin_unlock_irqrestore(&rxq->lock, flags);
 230         /* If the pre-allocated buffer pool is dropping low, schedule to
 231          * refill it */
 232         if (rxq->free_count <= RX_LOW_WATERMARK)
 233                 schedule_work(&trans_pcie->rx_replenish);
 234
 235
 236         /* If we've added more space for the firmware to place data, tell it.
 237          * Increment device's write pointer in multiples of 8. */
 238         if (rxq->write_actual != (rxq->write & ~0x7)) {
 239                 spin_lock_irqsave(&rxq->lock, flags);
 240                 rxq->need_update = 1;
 241                 spin_unlock_irqrestore(&rxq->lock, flags);
 242                 iwl_rx_queue_update_write_ptr(trans, rxq);
 243         }
 244 }
 245
 246 /**
 247  * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
 248  *
 249  * When moving to rx_free an SKB is allocated for the slot.
 250  *
 251  * Also restock the Rx queue via iwl_rx_queue_restock.
 252  * This is called as a scheduled work item (except for during initialization)
 253  */
 254 static void iwlagn_rx_allocate(struct iwl_trans *trans, gfp_t priority)
 255 {
 256         struct iwl_trans_pcie *trans_pcie =
 257                 IWL_TRANS_GET_PCIE_TRANS(trans);
 258
 259         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 260         struct list_head *element;
 261         struct iwl_rx_mem_buffer *rxb;
 262         struct page *page;
 263         unsigned long flags;
 264         gfp_t gfp_mask = priority;
 265
 266         while (1) {
 267                 spin_lock_irqsave(&rxq->lock, flags);
 268                 if (list_empty(&rxq->rx_used)) {
 269                         spin_unlock_irqrestore(&rxq->lock, flags);
 270                         return;
 271                 }
 272                 spin_unlock_irqrestore(&rxq->lock, flags);
 273
 274                 if (rxq->free_count > RX_LOW_WATERMARK)
 275                         gfp_mask |= __GFP_NOWARN;
 276
 277                 if (trans_pcie->rx_page_order > 0)
 278                         gfp_mask |= __GFP_COMP;
 279
 280                 /* Alloc a new receive buffer */
 281                 page = alloc_pages(gfp_mask,
 282                                   trans_pcie->rx_page_order);
 283                 if (!page) {
 284                         if (net_ratelimit())
 285                                 IWL_DEBUG_INFO(trans, "alloc_pages failed, "
 286                                            "order: %d\n",
 287                                            trans_pcie->rx_page_order);
 288
 289                         if ((rxq->free_count <= RX_LOW_WATERMARK) &&
 290                             net_ratelimit())
 291                                 IWL_CRIT(trans, "Failed to alloc_pages with %s."
 292                                          "Only %u free buffers remaining.\n",
 293                                          priority == GFP_ATOMIC ?
 294                                          "GFP_ATOMIC" : "GFP_KERNEL",
 295                                          rxq->free_count);
 296                         /* We don't reschedule replenish work here -- we will
 297                          * call the restock method and if it still needs
 298                          * more buffers it will schedule replenish */
 299                         return;
 300                 }
 301
 302                 spin_lock_irqsave(&rxq->lock, flags);
 303
 304                 if (list_empty(&rxq->rx_used)) {
 305                         spin_unlock_irqrestore(&rxq->lock, flags);
 306                         __free_pages(page, trans_pcie->rx_page_order);
 307                         return;
 308                 }
 309                 element = rxq->rx_used.next;
 310                 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
 311                 list_del(element);
 312
 313                 spin_unlock_irqrestore(&rxq->lock, flags);
 314
 315                 BUG_ON(rxb->page);
 316                 rxb->page = page;
 317                 /* Get physical address of the RB */
 318                 rxb->page_dma = dma_map_page(trans->dev, page, 0,
 319                                 PAGE_SIZE << trans_pcie->rx_page_order,
 320                                 DMA_FROM_DEVICE);
 321                 /* dma address must be no more than 36 bits */
 322                 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
 323                 /* and also 256 byte aligned! */
 324                 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
 325
 326                 spin_lock_irqsave(&rxq->lock, flags);
 327
 328                 list_add_tail(&rxb->list, &rxq->rx_free);
 329                 rxq->free_count++;
 330
 331                 spin_unlock_irqrestore(&rxq->lock, flags);
 332         }
 333 }
 334
 335 void iwlagn_rx_replenish(struct iwl_trans *trans)
 336 {
 337         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 338         unsigned long flags;
 339
 340         iwlagn_rx_allocate(trans, GFP_KERNEL);
 341
 342         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 343         iwlagn_rx_queue_restock(trans);
 344         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 345 }
 346
 347 static void iwlagn_rx_replenish_now(struct iwl_trans *trans)
 348 {
 349         iwlagn_rx_allocate(trans, GFP_ATOMIC);
 350
 351         iwlagn_rx_queue_restock(trans);
 352 }
 353
 354 void iwl_bg_rx_replenish(struct work_struct *data)
 355 {
 356         struct iwl_trans_pcie *trans_pcie =
 357             container_of(data, struct iwl_trans_pcie, rx_replenish);
 358
 359         iwlagn_rx_replenish(trans_pcie->trans);
 360 }
 361
 362 static void iwl_rx_handle_rxbuf(struct iwl_trans *trans,
 363                                 struct iwl_rx_mem_buffer *rxb)
 364 {
 365         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 366         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 367         struct iwl_tx_queue *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
 368         unsigned long flags;
 369         bool page_stolen = false;
 370         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
 371         u32 offset = 0;
 372
 373         if (WARN_ON(!rxb))
 374                 return;
 375
 376         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
 377
 378         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
 379                 struct iwl_rx_packet *pkt;
 380                 struct iwl_device_cmd *cmd;
 381                 u16 sequence;
 382                 bool reclaim;
 383                 int index, cmd_index, err, len;
 384                 struct iwl_rx_cmd_buffer rxcb = {
 385                         ._offset = offset,
 386                         ._page = rxb->page,
 387                         ._page_stolen = false,
 388                 };
 389
 390                 pkt = rxb_addr(&rxcb);
 391
 392                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
 393                         break;
 394
 395                 IWL_DEBUG_RX(trans, "cmd at offset %d: %s (0x%.2x)\n",
 396                              rxcb._offset, get_cmd_string(pkt->hdr.cmd),
 397                              pkt->hdr.cmd);
 398
 399                 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 400                 len += sizeof(u32); /* account for status word */
 401                 trace_iwlwifi_dev_rx(trans->dev, pkt, len);
 402
 403                 /* Reclaim a command buffer only if this packet is a response
 404                  *   to a (driver-originated) command.
 405                  * If the packet (e.g. Rx frame) originated from uCode,
 406                  *   there is no command buffer to reclaim.
 407                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
 408                  *   but apparently a few don't get set; catch them here. */
 409                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
 410                 if (reclaim) {
 411                         int i;
 412
 413                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
 414                                 if (trans_pcie->no_reclaim_cmds[i] ==
 415                                                         pkt->hdr.cmd) {
 416                                         reclaim = false;
 417                                         break;
 418                                 }
 419                         }
 420                 }
 421
 422                 sequence = le16_to_cpu(pkt->hdr.sequence);
 423                 index = SEQ_TO_INDEX(sequence);
 424                 cmd_index = get_cmd_index(&txq->q, index);
 425
 426                 if (reclaim)
 427                         cmd = txq->cmd[cmd_index];
 428                 else
 429                         cmd = NULL;
 430
 431                 err = iwl_op_mode_rx(trans->op_mode, &rxcb, cmd);
 432
 433                 /*
 434                  * After here, we should always check rxcb._page_stolen,
 435                  * if it is true then one of the handlers took the page.
 436                  */
 437
 438                 if (reclaim) {
 439                         /* Invoke any callbacks, transfer the buffer to caller,
 440                          * and fire off the (possibly) blocking
 441                          * iwl_trans_send_cmd()
 442                          * as we reclaim the driver command queue */
 443                         if (!rxcb._page_stolen)
 444                                 iwl_tx_cmd_complete(trans, &rxcb, err);
 445                         else
 446                                 IWL_WARN(trans, "Claim null rxb?\n");
 447                 }
 448
 449                 page_stolen |= rxcb._page_stolen;
 450                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
 451         }
 452
 453         /* page was stolen from us -- free our reference */
 454         if (page_stolen) {
 455                 __free_pages(rxb->page, trans_pcie->rx_page_order);
 456                 rxb->page = NULL;
 457         }
 458
 459         /* Reuse the page if possible. For notification packets and
 460          * SKBs that fail to Rx correctly, add them back into the
 461          * rx_free list for reuse later. */
 462         spin_lock_irqsave(&rxq->lock, flags);
 463         if (rxb->page != NULL) {
 464                 rxb->page_dma =
 465                         dma_map_page(trans->dev, rxb->page, 0,
 466                                 PAGE_SIZE << trans_pcie->rx_page_order,
 467                                 DMA_FROM_DEVICE);
 468                 list_add_tail(&rxb->list, &rxq->rx_free);
 469                 rxq->free_count++;
 470         } else
 471                 list_add_tail(&rxb->list, &rxq->rx_used);
 472         spin_unlock_irqrestore(&rxq->lock, flags);
 473 }
 474
 475 /**
 476  * iwl_rx_handle - Main entry function for receiving responses from uCode
 477  *
 478  * Uses the priv->rx_handlers callback function array to invoke
 479  * the appropriate handlers, including command responses,
 480  * frame-received notifications, and other notifications.
 481  */
 482 static void iwl_rx_handle(struct iwl_trans *trans)
 483 {
 484         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 485         struct iwl_rx_queue *rxq = &trans_pcie->rxq;
 486         u32 r, i;
 487         u8 fill_rx = 0;
 488         u32 count = 8;
 489         int total_empty;
 490
 491         /* uCode's read index (stored in shared DRAM) indicates the last Rx
 492          * buffer that the driver may process (last buffer filled by ucode). */
 493         r = le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF;
 494         i = rxq->read;
 495
 496         /* Rx interrupt, but nothing sent from uCode */
 497         if (i == r)
 498                 IWL_DEBUG_RX(trans, "r = %d, i = %d\n", r, i);
 499
 500         /* calculate total frames need to be restock after handling RX */
 501         total_empty = r - rxq->write_actual;
 502         if (total_empty < 0)
 503                 total_empty += RX_QUEUE_SIZE;
 504
 505         if (total_empty > (RX_QUEUE_SIZE / 2))
 506                 fill_rx = 1;
 507
 508         while (i != r) {
 509                 struct iwl_rx_mem_buffer *rxb;
 510
 511                 rxb = rxq->queue[i];
 512                 rxq->queue[i] = NULL;
 513
 514                 IWL_DEBUG_RX(trans, "rxbuf: r = %d, i = %d (%p)\n", rxb);
 515
 516                 iwl_rx_handle_rxbuf(trans, rxb);
 517
 518                 i = (i + 1) & RX_QUEUE_MASK;
 519                 /* If there are a lot of unused frames,
 520                  * restock the Rx queue so ucode wont assert. */
 521                 if (fill_rx) {
 522                         count++;
 523                         if (count >= 8) {
 524                                 rxq->read = i;
 525                                 iwlagn_rx_replenish_now(trans);
 526                                 count = 0;
 527                         }
 528                 }
 529         }
 530
 531         /* Backtrack one entry */
 532         rxq->read = i;
 533         if (fill_rx)
 534                 iwlagn_rx_replenish_now(trans);
 535         else
 536                 iwlagn_rx_queue_restock(trans);
 537 }
 538
 539 /**
 540  * iwl_irq_handle_error - called for HW or SW error interrupt from card
 541  */
 542 static void iwl_irq_handle_error(struct iwl_trans *trans)
 543 {
 544         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
 545         if (cfg(trans)->internal_wimax_coex &&
 546             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
 547                         APMS_CLK_VAL_MRB_FUNC_MODE) ||
 548              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
 549                         APMG_PS_CTRL_VAL_RESET_REQ))) {
 550                 /*
 551                  * Keep the restart process from trying to send host
 552                  * commands by clearing the ready bit.
 553                  */
 554                 clear_bit(STATUS_READY, &trans->shrd->status);
 555                 clear_bit(STATUS_HCMD_ACTIVE, &trans->shrd->status);
 556                 wake_up(&trans->wait_command_queue);
 557                 IWL_ERR(trans, "RF is used by WiMAX\n");
 558                 return;
 559         }
 560
 561         iwl_dump_csr(trans);
 562         iwl_dump_fh(trans, NULL, false);
 563
 564         iwl_op_mode_nic_error(trans->op_mode);
 565 }
 566
 567 /* tasklet for iwlagn interrupt */
 568 void iwl_irq_tasklet(struct iwl_trans *trans)
 569 {
 570         u32 inta = 0;
 571         u32 handled = 0;
 572         unsigned long flags;
 573         u32 i;
 574 #ifdef CONFIG_IWLWIFI_DEBUG
 575         u32 inta_mask;
 576 #endif
 577
 578         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 579         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
 580
 581
 582         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 583
 584         /* Ack/clear/reset pending uCode interrupts.
 585          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
 586          */
 587         /* There is a hardware bug in the interrupt mask function that some
 588          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
 589          * they are disabled in the CSR_INT_MASK register. Furthermore the
 590          * ICT interrupt handling mechanism has another bug that might cause
 591          * these unmasked interrupts fail to be detected. We workaround the
 592          * hardware bugs here by ACKing all the possible interrupts so that
 593          * interrupt coalescing can still be achieved.
 594          */
 595         iwl_write32(trans, CSR_INT,
 596                 trans_pcie->inta | ~trans_pcie->inta_mask);
 597
 598         inta = trans_pcie->inta;
 599
 600 #ifdef CONFIG_IWLWIFI_DEBUG
 601         if (iwl_have_debug_level(IWL_DL_ISR)) {
 602                 /* just for debug */
 603                 inta_mask = iwl_read32(trans, CSR_INT_MASK);
 604                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
 605                                 inta, inta_mask);
 606         }
 607 #endif
 608
 609         /* saved interrupt in inta variable now we can reset trans_pcie->inta */
 610         trans_pcie->inta = 0;
 611
 612         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 613
 614         /* Now service all interrupt bits discovered above. */
 615         if (inta & CSR_INT_BIT_HW_ERR) {
 616                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
 617
 618                 /* Tell the device to stop sending interrupts */
 619                 iwl_disable_interrupts(trans);
 620
 621                 isr_stats->hw++;
 622                 iwl_irq_handle_error(trans);
 623
 624                 handled |= CSR_INT_BIT_HW_ERR;
 625
 626                 return;
 627         }
 628
 629 #ifdef CONFIG_IWLWIFI_DEBUG
 630         if (iwl_have_debug_level(IWL_DL_ISR)) {
 631                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
 632                 if (inta & CSR_INT_BIT_SCD) {
 633                         IWL_DEBUG_ISR(trans, "Scheduler finished to transmit "
 634                                       "the frame/frames.\n");
 635                         isr_stats->sch++;
 636                 }
 637
 638                 /* Alive notification via Rx interrupt will do the real work */
 639                 if (inta & CSR_INT_BIT_ALIVE) {
 640                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
 641                         isr_stats->alive++;
 642                 }
 643         }
 644 #endif
 645         /* Safely ignore these bits for debug checks below */
 646         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
 647
 648         /* HW RF KILL switch toggled */
 649         if (inta & CSR_INT_BIT_RF_KILL) {
 650                 bool hw_rfkill;
 651
 652                 hw_rfkill = !(iwl_read32(trans, CSR_GP_CNTRL) &
 653                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW);
 654                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
 655                                 hw_rfkill ? "disable radio" : "enable radio");
 656
 657                 isr_stats->rfkill++;
 658
 659                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 660
 661                 handled |= CSR_INT_BIT_RF_KILL;
 662         }
 663
 664         /* Chip got too hot and stopped itself */
 665         if (inta & CSR_INT_BIT_CT_KILL) {
 666                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
 667                 isr_stats->ctkill++;
 668                 handled |= CSR_INT_BIT_CT_KILL;
 669         }
 670
 671         /* Error detected by uCode */
 672         if (inta & CSR_INT_BIT_SW_ERR) {
 673                 IWL_ERR(trans, "Microcode SW error detected. "
 674                         " Restarting 0x%X.\n", inta);
 675                 isr_stats->sw++;
 676                 iwl_irq_handle_error(trans);
 677                 handled |= CSR_INT_BIT_SW_ERR;
 678         }
 679
 680         /* uCode wakes up after power-down sleep */
 681         if (inta & CSR_INT_BIT_WAKEUP) {
 682                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
 683                 iwl_rx_queue_update_write_ptr(trans, &trans_pcie->rxq);
 684                 for (i = 0; i < cfg(trans)->base_params->num_of_queues; i++)
 685                         iwl_txq_update_write_ptr(trans,
 686                                                  &trans_pcie->txq[i]);
 687
 688                 isr_stats->wakeup++;
 689
 690                 handled |= CSR_INT_BIT_WAKEUP;
 691         }
 692
 693         /* All uCode command responses, including Tx command responses,
 694          * Rx "responses" (frame-received notification), and other
 695          * notifications from uCode come through here*/
 696         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
 697                         CSR_INT_BIT_RX_PERIODIC)) {
 698                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
 699                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
 700                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
 701                         iwl_write32(trans, CSR_FH_INT_STATUS,
 702                                         CSR_FH_INT_RX_MASK);
 703                 }
 704                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
 705                         handled |= CSR_INT_BIT_RX_PERIODIC;
 706                         iwl_write32(trans,
 707                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
 708                 }
 709                 /* Sending RX interrupt require many steps to be done in the
 710                  * the device:
 711                  * 1- write interrupt to current index in ICT table.
 712                  * 2- dma RX frame.
 713                  * 3- update RX shared data to indicate last write index.
 714                  * 4- send interrupt.
 715                  * This could lead to RX race, driver could receive RX interrupt
 716                  * but the shared data changes does not reflect this;
 717                  * periodic interrupt will detect any dangling Rx activity.
 718                  */
 719
 720                 /* Disable periodic interrupt; we use it as just a one-shot. */
 721                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
 722                             CSR_INT_PERIODIC_DIS);
 723 #ifdef CONFIG_IWLWIFI_IDI
 724                 iwl_amfh_rx_handler();
 725 #else
 726                 iwl_rx_handle(trans);
 727 #endif
 728                 /*
 729                  * Enable periodic interrupt in 8 msec only if we received
 730                  * real RX interrupt (instead of just periodic int), to catch
 731                  * any dangling Rx interrupt.  If it was just the periodic
 732                  * interrupt, there was no dangling Rx activity, and no need
 733                  * to extend the periodic interrupt; one-shot is enough.
 734                  */
 735                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
 736                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
 737                                     CSR_INT_PERIODIC_ENA);
 738
 739                 isr_stats->rx++;
 740         }
 741
 742         /* This "Tx" DMA channel is used only for loading uCode */
 743         if (inta & CSR_INT_BIT_FH_TX) {
 744                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
 745                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
 746                 isr_stats->tx++;
 747                 handled |= CSR_INT_BIT_FH_TX;
 748                 /* Wake up uCode load routine, now that load is complete */
 749                 trans_pcie->ucode_write_complete = true;
 750                 wake_up(&trans_pcie->ucode_write_waitq);
 751         }
 752
 753         if (inta & ~handled) {
 754                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
 755                 isr_stats->unhandled++;
 756         }
 757
 758         if (inta & ~(trans_pcie->inta_mask)) {
 759                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
 760                          inta & ~trans_pcie->inta_mask);
 761         }
 762
 763         /* Re-enable all interrupts */
 764         /* only Re-enable if disabled by irq */
 765         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status))
 766                 iwl_enable_interrupts(trans);
 767         /* Re-enable RF_KILL if it occurred */
 768         else if (handled & CSR_INT_BIT_RF_KILL)
 769                 iwl_enable_rfkill_int(trans);
 770 }
 771
 772 /******************************************************************************
 773  *
 774  * ICT functions
 775  *
 776  ******************************************************************************/
 777
 778 /* a device (PCI-E) page is 4096 bytes long */
 779 #define ICT_SHIFT       12
 780 #define ICT_SIZE        (1 << ICT_SHIFT)
 781 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
 782
 783 /* Free dram table */
 784 void iwl_free_isr_ict(struct iwl_trans *trans)
 785 {
 786         struct iwl_trans_pcie *trans_pcie =
 787                 IWL_TRANS_GET_PCIE_TRANS(trans);
 788
 789         if (trans_pcie->ict_tbl) {
 790                 dma_free_coherent(trans->dev, ICT_SIZE,
 791                                   trans_pcie->ict_tbl,
 792                                   trans_pcie->ict_tbl_dma);
 793                 trans_pcie->ict_tbl = NULL;
 794                 trans_pcie->ict_tbl_dma = 0;
 795         }
 796 }
 797
 798
 799 /*
 800  * allocate dram shared table, it is an aligned memory
 801  * block of ICT_SIZE.
 802  * also reset all data related to ICT table interrupt.
 803  */
 804 int iwl_alloc_isr_ict(struct iwl_trans *trans)
 805 {
 806         struct iwl_trans_pcie *trans_pcie =
 807                 IWL_TRANS_GET_PCIE_TRANS(trans);
 808
 809         trans_pcie->ict_tbl =
 810                 dma_alloc_coherent(trans->dev, ICT_SIZE,
 811                                    &trans_pcie->ict_tbl_dma,
 812                                    GFP_KERNEL);
 813         if (!trans_pcie->ict_tbl)
 814                 return -ENOMEM;
 815
 816         /* just an API sanity check ... it is guaranteed to be aligned */
 817         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
 818                 iwl_free_isr_ict(trans);
 819                 return -EINVAL;
 820         }
 821
 822         IWL_DEBUG_ISR(trans, "ict dma addr %Lx\n",
 823                       (unsigned long long)trans_pcie->ict_tbl_dma);
 824
 825         IWL_DEBUG_ISR(trans, "ict vir addr %p\n", trans_pcie->ict_tbl);
 826
 827         /* reset table and index to all 0 */
 828         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
 829         trans_pcie->ict_index = 0;
 830
 831         /* add periodic RX interrupt */
 832         trans_pcie->inta_mask |= CSR_INT_BIT_RX_PERIODIC;
 833         return 0;
 834 }
 835
 836 /* Device is going up inform it about using ICT interrupt table,
 837  * also we need to tell the driver to start using ICT interrupt.
 838  */
 839 void iwl_reset_ict(struct iwl_trans *trans)
 840 {
 841         u32 val;
 842         unsigned long flags;
 843         struct iwl_trans_pcie *trans_pcie =
 844                 IWL_TRANS_GET_PCIE_TRANS(trans);
 845
 846         if (!trans_pcie->ict_tbl)
 847                 return;
 848
 849         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 850         iwl_disable_interrupts(trans);
 851
 852         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
 853
 854         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
 855
 856         val |= CSR_DRAM_INT_TBL_ENABLE;
 857         val |= CSR_DRAM_INIT_TBL_WRAP_CHECK;
 858
 859         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
 860
 861         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
 862         trans_pcie->use_ict = true;
 863         trans_pcie->ict_index = 0;
 864         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
 865         iwl_enable_interrupts(trans);
 866         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 867 }
 868
 869 /* Device is going down disable ict interrupt usage */
 870 void iwl_disable_ict(struct iwl_trans *trans)
 871 {
 872         struct iwl_trans_pcie *trans_pcie =
 873                 IWL_TRANS_GET_PCIE_TRANS(trans);
 874
 875         unsigned long flags;
 876
 877         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 878         trans_pcie->use_ict = false;
 879         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 880 }
 881
 882 static irqreturn_t iwl_isr(int irq, void *data)
 883 {
 884         struct iwl_trans *trans = data;
 885         struct iwl_trans_pcie *trans_pcie;
 886         u32 inta, inta_mask;
 887         unsigned long flags;
 888 #ifdef CONFIG_IWLWIFI_DEBUG
 889         u32 inta_fh;
 890 #endif
 891         if (!trans)
 892                 return IRQ_NONE;
 893
 894         trace_iwlwifi_dev_irq(trans->dev);
 895
 896         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 897
 898         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 899
 900         /* Disable (but don't clear!) interrupts here to avoid
 901          *    back-to-back ISRs and sporadic interrupts from our NIC.
 902          * If we have something to service, the tasklet will re-enable ints.
 903          * If we *don't* have something, we'll re-enable before leaving here. */
 904         inta_mask = iwl_read32(trans, CSR_INT_MASK);  /* just for debug */
 905         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
 906
 907         /* Discover which interrupts are active/pending */
 908         inta = iwl_read32(trans, CSR_INT);
 909
 910         /* Ignore interrupt if there's nothing in NIC to service.
 911          * This may be due to IRQ shared with another device,
 912          * or due to sporadic interrupts thrown from our NIC. */
 913         if (!inta) {
 914                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
 915                 goto none;
 916         }
 917
 918         if ((inta == 0xFFFFFFFF) || ((inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
 919                 /* Hardware disappeared. It might have already raised
 920                  * an interrupt */
 921                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
 922                 goto unplugged;
 923         }
 924
 925 #ifdef CONFIG_IWLWIFI_DEBUG
 926         if (iwl_have_debug_level(IWL_DL_ISR)) {
 927                 inta_fh = iwl_read32(trans, CSR_FH_INT_STATUS);
 928                 IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x, "
 929                               "fh 0x%08x\n", inta, inta_mask, inta_fh);
 930         }
 931 #endif
 932
 933         trans_pcie->inta |= inta;
 934         /* iwl_irq_tasklet() will service interrupts and re-enable them */
 935         if (likely(inta))
 936                 tasklet_schedule(&trans_pcie->irq_tasklet);
 937         else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
 938                         !trans_pcie->inta)
 939                 iwl_enable_interrupts(trans);
 940
 941  unplugged:
 942         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 943         return IRQ_HANDLED;
 944
 945  none:
 946         /* re-enable interrupts here since we don't have anything to service. */
 947         /* only Re-enable if disabled by irq  and no schedules tasklet. */
 948         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
 949                 !trans_pcie->inta)
 950                 iwl_enable_interrupts(trans);
 951
 952         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 953         return IRQ_NONE;
 954 }
 955
 956 /* interrupt handler using ict table, with this interrupt driver will
 957  * stop using INTA register to get device's interrupt, reading this register
 958  * is expensive, device will write interrupts in ICT dram table, increment
 959  * index then will fire interrupt to driver, driver will OR all ICT table
 960  * entries from current index up to table entry with 0 value. the result is
 961  * the interrupt we need to service, driver will set the entries back to 0 and
 962  * set index.
 963  */
 964 irqreturn_t iwl_isr_ict(int irq, void *data)
 965 {
 966         struct iwl_trans *trans = data;
 967         struct iwl_trans_pcie *trans_pcie;
 968         u32 inta, inta_mask;
 969         u32 val = 0;
 970         u32 read;
 971         unsigned long flags;
 972
 973         if (!trans)
 974                 return IRQ_NONE;
 975
 976         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 977
 978         /* dram interrupt table not set yet,
 979          * use legacy interrupt.
 980          */
 981         if (!trans_pcie->use_ict)
 982                 return iwl_isr(irq, data);
 983
 984         trace_iwlwifi_dev_irq(trans->dev);
 985
 986         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 987
 988         /* Disable (but don't clear!) interrupts here to avoid
 989          * back-to-back ISRs and sporadic interrupts from our NIC.
 990          * If we have something to service, the tasklet will re-enable ints.
 991          * If we *don't* have something, we'll re-enable before leaving here.
 992          */
 993         inta_mask = iwl_read32(trans, CSR_INT_MASK);  /* just for debug */
 994         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
 995
 996
 997         /* Ignore interrupt if there's nothing in NIC to service.
 998          * This may be due to IRQ shared with another device,
 999          * or due to sporadic interrupts thrown from our NIC. */
1000         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1001         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1002         if (!read) {
1003                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1004                 goto none;
1005         }
1006
1007         /*
1008          * Collect all entries up to the first 0, starting from ict_index;
1009          * note we already read at ict_index.
1010          */
1011         do {
1012                 val |= read;
1013                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1014                                 trans_pcie->ict_index, read);
1015                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1016                 trans_pcie->ict_index =
1017                         iwl_queue_inc_wrap(trans_pcie->ict_index, ICT_COUNT);
1018
1019                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1020                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1021                                            read);
1022         } while (read);
1023
1024         /* We should not get this value, just ignore it. */
1025         if (val == 0xffffffff)
1026                 val = 0;
1027
1028         /*
1029          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1030          * (bit 15 before shifting it to 31) to clear when using interrupt
1031          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1032          * so we use them to decide on the real state of the Rx bit.
1033          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1034          */
1035         if (val & 0xC0000)
1036                 val |= 0x8000;
1037
1038         inta = (0xff & val) | ((0xff00 & val) << 16);
1039         IWL_DEBUG_ISR(trans, "ISR inta 0x%08x, enabled 0x%08x ict 0x%08x\n",
1040                         inta, inta_mask, val);
1041
1042         inta &= trans_pcie->inta_mask;
1043         trans_pcie->inta |= inta;
1044
1045         /* iwl_irq_tasklet() will service interrupts and re-enable them */
1046         if (likely(inta))
1047                 tasklet_schedule(&trans_pcie->irq_tasklet);
1048         else if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1049                  !trans_pcie->inta) {
1050                 /* Allow interrupt if was disabled by this handler and
1051                  * no tasklet was schedules, We should not enable interrupt,
1052                  * tasklet will enable it.
1053                  */
1054                 iwl_enable_interrupts(trans);
1055         }
1056
1057         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1058         return IRQ_HANDLED;
1059
1060  none:
1061         /* re-enable interrupts here since we don't have anything to service.
1062          * only Re-enable if disabled by irq.
1063          */
1064         if (test_bit(STATUS_INT_ENABLED, &trans_pcie->status) &&
1065             !trans_pcie->inta)
1066                 iwl_enable_interrupts(trans);
1067
1068         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
1069         return IRQ_NONE;
1070 }