2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 static u16 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
66 struct ath_atx_tid *tid,
77 static int ath_max_4ms_framelen[4][32] = {
79 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
80 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
81 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
82 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
85 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
86 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
87 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
88 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
91 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
92 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
93 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
94 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
97 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
98 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
99 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
100 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
104 /*********************/
105 /* Aggregation logic */
106 /*********************/
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
110 struct ath_atx_ac *ac = tid->ac;
119 list_add_tail(&tid->list, &ac->tid_q);
125 list_add_tail(&ac->list, &txq->axq_acq);
128 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
130 struct ath_txq *txq = tid->ac->txq;
132 WARN_ON(!tid->paused);
134 spin_lock_bh(&txq->axq_lock);
137 if (skb_queue_empty(&tid->buf_q))
140 ath_tx_queue_tid(txq, tid);
141 ath_txq_schedule(sc, txq);
143 spin_unlock_bh(&txq->axq_lock);
146 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
148 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
149 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
150 sizeof(tx_info->rate_driver_data));
151 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
154 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
156 struct ath_txq *txq = tid->ac->txq;
159 struct list_head bf_head;
160 struct ath_tx_status ts;
161 struct ath_frame_info *fi;
163 INIT_LIST_HEAD(&bf_head);
165 memset(&ts, 0, sizeof(ts));
166 spin_lock_bh(&txq->axq_lock);
168 while ((skb = __skb_dequeue(&tid->buf_q))) {
169 fi = get_frame_info(skb);
172 spin_unlock_bh(&txq->axq_lock);
173 if (bf && fi->retries) {
174 list_add_tail(&bf->list, &bf_head);
175 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
176 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
178 ath_tx_send_normal(sc, txq, NULL, skb);
180 spin_lock_bh(&txq->axq_lock);
183 spin_unlock_bh(&txq->axq_lock);
186 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
191 index = ATH_BA_INDEX(tid->seq_start, seqno);
192 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
194 __clear_bit(cindex, tid->tx_buf);
196 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
197 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
198 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
202 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
207 index = ATH_BA_INDEX(tid->seq_start, seqno);
208 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
209 __set_bit(cindex, tid->tx_buf);
211 if (index >= ((tid->baw_tail - tid->baw_head) &
212 (ATH_TID_MAX_BUFS - 1))) {
213 tid->baw_tail = cindex;
214 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
219 * TODO: For frame(s) that are in the retry state, we will reuse the
220 * sequence number(s) without setting the retry bit. The
221 * alternative is to give up on these and BAR the receiver's window
224 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
225 struct ath_atx_tid *tid)
230 struct list_head bf_head;
231 struct ath_tx_status ts;
232 struct ath_frame_info *fi;
234 memset(&ts, 0, sizeof(ts));
235 INIT_LIST_HEAD(&bf_head);
237 while ((skb = __skb_dequeue(&tid->buf_q))) {
238 fi = get_frame_info(skb);
242 spin_unlock(&txq->axq_lock);
243 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
244 spin_lock(&txq->axq_lock);
248 list_add_tail(&bf->list, &bf_head);
251 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
253 spin_unlock(&txq->axq_lock);
254 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
255 spin_lock(&txq->axq_lock);
258 tid->seq_next = tid->seq_start;
259 tid->baw_tail = tid->baw_head;
262 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
265 struct ath_frame_info *fi = get_frame_info(skb);
266 struct ath_buf *bf = fi->bf;
267 struct ieee80211_hdr *hdr;
269 TX_STAT_INC(txq->axq_qnum, a_retries);
270 if (fi->retries++ > 0)
273 hdr = (struct ieee80211_hdr *)skb->data;
274 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
275 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
276 sizeof(*hdr), DMA_TO_DEVICE);
279 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
281 struct ath_buf *bf = NULL;
283 spin_lock_bh(&sc->tx.txbuflock);
285 if (unlikely(list_empty(&sc->tx.txbuf))) {
286 spin_unlock_bh(&sc->tx.txbuflock);
290 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
294 spin_unlock_bh(&sc->tx.txbuflock);
299 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
301 spin_lock_bh(&sc->tx.txbuflock);
302 list_add_tail(&bf->list, &sc->tx.txbuf);
303 spin_unlock_bh(&sc->tx.txbuflock);
306 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
310 tbf = ath_tx_get_buffer(sc);
314 ATH_TXBUF_RESET(tbf);
316 tbf->bf_mpdu = bf->bf_mpdu;
317 tbf->bf_buf_addr = bf->bf_buf_addr;
318 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
319 tbf->bf_state = bf->bf_state;
324 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
325 struct ath_tx_status *ts, int txok,
326 int *nframes, int *nbad)
328 struct ath_frame_info *fi;
330 u32 ba[WME_BA_BMP_SIZE >> 5];
337 isaggr = bf_isaggr(bf);
339 seq_st = ts->ts_seqnum;
340 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
344 fi = get_frame_info(bf->bf_mpdu);
345 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
348 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
356 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
357 struct ath_buf *bf, struct list_head *bf_q,
358 struct ath_tx_status *ts, int txok, bool retry)
360 struct ath_node *an = NULL;
362 struct ieee80211_sta *sta;
363 struct ieee80211_hw *hw = sc->hw;
364 struct ieee80211_hdr *hdr;
365 struct ieee80211_tx_info *tx_info;
366 struct ath_atx_tid *tid = NULL;
367 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
368 struct list_head bf_head;
369 struct sk_buff_head bf_pending;
370 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
371 u32 ba[WME_BA_BMP_SIZE >> 5];
372 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
373 bool rc_update = true;
374 struct ieee80211_tx_rate rates[4];
375 struct ath_frame_info *fi;
378 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
381 hdr = (struct ieee80211_hdr *)skb->data;
383 tx_info = IEEE80211_SKB_CB(skb);
385 memcpy(rates, tx_info->control.rates, sizeof(rates));
389 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
393 INIT_LIST_HEAD(&bf_head);
395 bf_next = bf->bf_next;
397 if (!bf->bf_stale || bf_next != NULL)
398 list_move_tail(&bf->list, &bf_head);
400 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
408 an = (struct ath_node *)sta->drv_priv;
409 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
410 tid = ATH_AN_2_TID(an, tidno);
413 * The hardware occasionally sends a tx status for the wrong TID.
414 * In this case, the BA status cannot be considered valid and all
415 * subframes need to be retransmitted
417 if (tidno != ts->tid)
420 isaggr = bf_isaggr(bf);
421 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
423 if (isaggr && txok) {
424 if (ts->ts_flags & ATH9K_TX_BA) {
425 seq_st = ts->ts_seqnum;
426 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
429 * AR5416 can become deaf/mute when BA
430 * issue happens. Chip needs to be reset.
431 * But AP code may have sychronization issues
432 * when perform internal reset in this routine.
433 * Only enable reset in STA mode for now.
435 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
440 __skb_queue_head_init(&bf_pending);
442 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
444 u16 seqno = bf->bf_state.seqno;
446 txfail = txpending = sendbar = 0;
447 bf_next = bf->bf_next;
450 tx_info = IEEE80211_SKB_CB(skb);
451 fi = get_frame_info(skb);
453 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
454 /* transmit completion, subframe is
455 * acked by block ack */
457 } else if (!isaggr && txok) {
458 /* transmit completion */
461 if ((tid->state & AGGR_CLEANUP) || !retry) {
463 * cleanup in progress, just fail
464 * the un-acked sub-frames
469 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
470 if (txok || !an->sleeping)
471 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
482 * Make sure the last desc is reclaimed if it
483 * not a holding desc.
485 INIT_LIST_HEAD(&bf_head);
486 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
487 bf_next != NULL || !bf_last->bf_stale)
488 list_move_tail(&bf->list, &bf_head);
490 if (!txpending || (tid->state & AGGR_CLEANUP)) {
492 * complete the acked-ones/xretried ones; update
495 spin_lock_bh(&txq->axq_lock);
496 ath_tx_update_baw(sc, tid, seqno);
497 spin_unlock_bh(&txq->axq_lock);
499 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
500 memcpy(tx_info->control.rates, rates, sizeof(rates));
501 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
505 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
508 /* retry the un-acked ones */
509 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
510 if (bf->bf_next == NULL && bf_last->bf_stale) {
513 tbf = ath_clone_txbuf(sc, bf_last);
515 * Update tx baw and complete the
516 * frame with failed status if we
520 spin_lock_bh(&txq->axq_lock);
521 ath_tx_update_baw(sc, tid, seqno);
522 spin_unlock_bh(&txq->axq_lock);
524 ath_tx_complete_buf(sc, bf, txq,
536 * Put this buffer to the temporary pending
537 * queue to retain ordering
539 __skb_queue_tail(&bf_pending, skb);
545 /* prepend un-acked frames to the beginning of the pending frame queue */
546 if (!skb_queue_empty(&bf_pending)) {
548 ieee80211_sta_set_buffered(sta, tid->tidno, true);
550 spin_lock_bh(&txq->axq_lock);
551 skb_queue_splice(&bf_pending, &tid->buf_q);
553 ath_tx_queue_tid(txq, tid);
555 if (ts->ts_status & ATH9K_TXERR_FILT)
556 tid->ac->clear_ps_filter = true;
558 spin_unlock_bh(&txq->axq_lock);
561 if (tid->state & AGGR_CLEANUP) {
562 ath_tx_flush_tid(sc, tid);
564 if (tid->baw_head == tid->baw_tail) {
565 tid->state &= ~AGGR_ADDBA_COMPLETE;
566 tid->state &= ~AGGR_CLEANUP;
573 RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR);
574 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
578 static bool ath_lookup_legacy(struct ath_buf *bf)
581 struct ieee80211_tx_info *tx_info;
582 struct ieee80211_tx_rate *rates;
586 tx_info = IEEE80211_SKB_CB(skb);
587 rates = tx_info->control.rates;
589 for (i = 0; i < 4; i++) {
590 if (!rates[i].count || rates[i].idx < 0)
593 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
600 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
601 struct ath_atx_tid *tid)
604 struct ieee80211_tx_info *tx_info;
605 struct ieee80211_tx_rate *rates;
606 u32 max_4ms_framelen, frmlen;
607 u16 aggr_limit, legacy = 0;
611 tx_info = IEEE80211_SKB_CB(skb);
612 rates = tx_info->control.rates;
615 * Find the lowest frame length among the rate series that will have a
616 * 4ms transmit duration.
617 * TODO - TXOP limit needs to be considered.
619 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
621 for (i = 0; i < 4; i++) {
622 if (rates[i].count) {
624 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
629 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
634 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
637 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
638 max_4ms_framelen = min(max_4ms_framelen, frmlen);
643 * limit aggregate size by the minimum rate if rate selected is
644 * not a probe rate, if rate selected is a probe rate then
645 * avoid aggregation of this packet.
647 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
650 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
651 aggr_limit = min((max_4ms_framelen * 3) / 8,
652 (u32)ATH_AMPDU_LIMIT_MAX);
654 aggr_limit = min(max_4ms_framelen,
655 (u32)ATH_AMPDU_LIMIT_MAX);
658 * h/w can accept aggregates up to 16 bit lengths (65535).
659 * The IE, however can hold up to 65536, which shows up here
660 * as zero. Ignore 65536 since we are constrained by hw.
662 if (tid->an->maxampdu)
663 aggr_limit = min(aggr_limit, tid->an->maxampdu);
669 * Returns the number of delimiters to be added to
670 * meet the minimum required mpdudensity.
672 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
673 struct ath_buf *bf, u16 frmlen,
676 #define FIRST_DESC_NDELIMS 60
677 struct sk_buff *skb = bf->bf_mpdu;
678 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
679 u32 nsymbits, nsymbols;
682 int width, streams, half_gi, ndelim, mindelim;
683 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
685 /* Select standard number of delimiters based on frame length alone */
686 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
689 * If encryption enabled, hardware requires some more padding between
691 * TODO - this could be improved to be dependent on the rate.
692 * The hardware can keep up at lower rates, but not higher rates
694 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
695 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
696 ndelim += ATH_AGGR_ENCRYPTDELIM;
699 * Add delimiter when using RTS/CTS with aggregation
700 * and non enterprise AR9003 card
702 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
703 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
704 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
707 * Convert desired mpdu density from microeconds to bytes based
708 * on highest rate in rate series (i.e. first rate) to determine
709 * required minimum length for subframe. Take into account
710 * whether high rate is 20 or 40Mhz and half or full GI.
712 * If there is no mpdu density restriction, no further calculation
716 if (tid->an->mpdudensity == 0)
719 rix = tx_info->control.rates[0].idx;
720 flags = tx_info->control.rates[0].flags;
721 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
722 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
725 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
727 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
732 streams = HT_RC_2_STREAMS(rix);
733 nsymbits = bits_per_symbol[rix % 8][width] * streams;
734 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
736 if (frmlen < minlen) {
737 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
738 ndelim = max(mindelim, ndelim);
744 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
746 struct ath_atx_tid *tid,
747 struct list_head *bf_q,
750 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
751 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
752 int rl = 0, nframes = 0, ndelim, prev_al = 0;
753 u16 aggr_limit = 0, al = 0, bpad = 0,
754 al_delta, h_baw = tid->baw_size / 2;
755 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
756 struct ieee80211_tx_info *tx_info;
757 struct ath_frame_info *fi;
762 skb = skb_peek(&tid->buf_q);
763 fi = get_frame_info(skb);
766 bf = ath_tx_setup_buffer(sc, txq, tid, skb, true);
771 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
772 seqno = bf->bf_state.seqno;
776 /* do not step over block-ack window */
777 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
778 status = ATH_AGGR_BAW_CLOSED;
783 aggr_limit = ath_lookup_rate(sc, bf, tid);
787 /* do not exceed aggregation limit */
788 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
791 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
792 ath_lookup_legacy(bf))) {
793 status = ATH_AGGR_LIMITED;
797 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
798 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
801 /* do not exceed subframe limit */
802 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
803 status = ATH_AGGR_LIMITED;
807 /* add padding for previous frame to aggregation length */
808 al += bpad + al_delta;
811 * Get the delimiters needed to meet the MPDU
812 * density for this node.
814 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
816 bpad = PADBYTES(al_delta) + (ndelim << 2);
821 /* link buffers of this frame to the aggregate */
823 ath_tx_addto_baw(sc, tid, seqno);
824 bf->bf_state.ndelim = ndelim;
826 __skb_unlink(skb, &tid->buf_q);
827 list_add_tail(&bf->list, bf_q);
829 bf_prev->bf_next = bf;
833 } while (!skb_queue_empty(&tid->buf_q));
843 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
844 * width - 0 for 20 MHz, 1 for 40 MHz
845 * half_gi - to use 4us v/s 3.6 us for symbol time
847 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
848 int width, int half_gi, bool shortPreamble)
850 u32 nbits, nsymbits, duration, nsymbols;
853 /* find number of symbols: PLCP + data */
854 streams = HT_RC_2_STREAMS(rix);
855 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
856 nsymbits = bits_per_symbol[rix % 8][width] * streams;
857 nsymbols = (nbits + nsymbits - 1) / nsymbits;
860 duration = SYMBOL_TIME(nsymbols);
862 duration = SYMBOL_TIME_HALFGI(nsymbols);
864 /* addup duration for legacy/ht training and signal fields */
865 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
870 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
871 struct ath_tx_info *info, int len)
873 struct ath_hw *ah = sc->sc_ah;
875 struct ieee80211_tx_info *tx_info;
876 struct ieee80211_tx_rate *rates;
877 const struct ieee80211_rate *rate;
878 struct ieee80211_hdr *hdr;
883 tx_info = IEEE80211_SKB_CB(skb);
884 rates = tx_info->control.rates;
885 hdr = (struct ieee80211_hdr *)skb->data;
887 /* set dur_update_en for l-sig computation except for PS-Poll frames */
888 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
891 * We check if Short Preamble is needed for the CTS rate by
892 * checking the BSS's global flag.
893 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
895 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
896 info->rtscts_rate = rate->hw_value;
897 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
898 info->rtscts_rate |= rate->hw_value_short;
900 for (i = 0; i < 4; i++) {
901 bool is_40, is_sgi, is_sp;
904 if (!rates[i].count || (rates[i].idx < 0))
908 info->rates[i].Tries = rates[i].count;
910 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
911 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
912 info->flags |= ATH9K_TXDESC_RTSENA;
913 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
914 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
915 info->flags |= ATH9K_TXDESC_CTSENA;
918 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
919 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
920 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
921 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
923 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
924 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
925 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
927 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
929 info->rates[i].Rate = rix | 0x80;
930 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
931 ah->txchainmask, info->rates[i].Rate);
932 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
933 is_40, is_sgi, is_sp);
934 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
935 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
940 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
941 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
942 !(rate->flags & IEEE80211_RATE_ERP_G))
943 phy = WLAN_RC_PHY_CCK;
945 phy = WLAN_RC_PHY_OFDM;
947 info->rates[i].Rate = rate->hw_value;
948 if (rate->hw_value_short) {
949 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
950 info->rates[i].Rate |= rate->hw_value_short;
955 if (bf->bf_state.bfs_paprd)
956 info->rates[i].ChSel = ah->txchainmask;
958 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
959 ah->txchainmask, info->rates[i].Rate);
961 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
962 phy, rate->bitrate * 100, len, rix, is_sp);
965 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
966 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
967 info->flags &= ~ATH9K_TXDESC_RTSENA;
969 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
970 if (info->flags & ATH9K_TXDESC_RTSENA)
971 info->flags &= ~ATH9K_TXDESC_CTSENA;
974 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
976 struct ieee80211_hdr *hdr;
977 enum ath9k_pkt_type htype;
980 hdr = (struct ieee80211_hdr *)skb->data;
981 fc = hdr->frame_control;
983 if (ieee80211_is_beacon(fc))
984 htype = ATH9K_PKT_TYPE_BEACON;
985 else if (ieee80211_is_probe_resp(fc))
986 htype = ATH9K_PKT_TYPE_PROBE_RESP;
987 else if (ieee80211_is_atim(fc))
988 htype = ATH9K_PKT_TYPE_ATIM;
989 else if (ieee80211_is_pspoll(fc))
990 htype = ATH9K_PKT_TYPE_PSPOLL;
992 htype = ATH9K_PKT_TYPE_NORMAL;
997 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
998 struct ath_txq *txq, int len)
1000 struct ath_hw *ah = sc->sc_ah;
1001 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1002 struct ath_buf *bf_first = bf;
1003 struct ath_tx_info info;
1004 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1006 memset(&info, 0, sizeof(info));
1007 info.is_first = true;
1008 info.is_last = true;
1009 info.txpower = MAX_RATE_POWER;
1010 info.qcu = txq->axq_qnum;
1012 info.flags = ATH9K_TXDESC_INTREQ;
1013 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1014 info.flags |= ATH9K_TXDESC_NOACK;
1015 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1016 info.flags |= ATH9K_TXDESC_LDPC;
1018 ath_buf_set_rate(sc, bf, &info, len);
1020 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1021 info.flags |= ATH9K_TXDESC_CLRDMASK;
1023 if (bf->bf_state.bfs_paprd)
1024 info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
1028 struct sk_buff *skb = bf->bf_mpdu;
1029 struct ath_frame_info *fi = get_frame_info(skb);
1031 info.type = get_hw_packet_type(skb);
1033 info.link = bf->bf_next->bf_daddr;
1037 info.buf_addr[0] = bf->bf_buf_addr;
1038 info.buf_len[0] = skb->len;
1039 info.pkt_len = fi->framelen;
1040 info.keyix = fi->keyix;
1041 info.keytype = fi->keytype;
1045 info.aggr = AGGR_BUF_FIRST;
1046 else if (!bf->bf_next)
1047 info.aggr = AGGR_BUF_LAST;
1049 info.aggr = AGGR_BUF_MIDDLE;
1051 info.ndelim = bf->bf_state.ndelim;
1052 info.aggr_len = len;
1055 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1060 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1061 struct ath_atx_tid *tid)
1064 enum ATH_AGGR_STATUS status;
1065 struct ieee80211_tx_info *tx_info;
1066 struct list_head bf_q;
1070 if (skb_queue_empty(&tid->buf_q))
1073 INIT_LIST_HEAD(&bf_q);
1075 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1078 * no frames picked up to be aggregated;
1079 * block-ack window is not open.
1081 if (list_empty(&bf_q))
1084 bf = list_first_entry(&bf_q, struct ath_buf, list);
1085 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1086 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1088 if (tid->ac->clear_ps_filter) {
1089 tid->ac->clear_ps_filter = false;
1090 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1092 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1095 /* if only one frame, send as non-aggregate */
1096 if (bf == bf->bf_lastbf) {
1097 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1098 bf->bf_state.bf_type = BUF_AMPDU;
1100 TX_STAT_INC(txq->axq_qnum, a_aggr);
1103 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1104 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1105 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1106 status != ATH_AGGR_BAW_CLOSED);
1109 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1112 struct ath_atx_tid *txtid;
1113 struct ath_node *an;
1115 an = (struct ath_node *)sta->drv_priv;
1116 txtid = ATH_AN_2_TID(an, tid);
1118 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
1121 txtid->state |= AGGR_ADDBA_PROGRESS;
1122 txtid->paused = true;
1123 *ssn = txtid->seq_start = txtid->seq_next;
1125 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1126 txtid->baw_head = txtid->baw_tail = 0;
1131 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1133 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1134 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1135 struct ath_txq *txq = txtid->ac->txq;
1137 if (txtid->state & AGGR_CLEANUP)
1140 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
1141 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1145 spin_lock_bh(&txq->axq_lock);
1146 txtid->paused = true;
1149 * If frames are still being transmitted for this TID, they will be
1150 * cleaned up during tx completion. To prevent race conditions, this
1151 * TID can only be reused after all in-progress subframes have been
1154 if (txtid->baw_head != txtid->baw_tail)
1155 txtid->state |= AGGR_CLEANUP;
1157 txtid->state &= ~AGGR_ADDBA_COMPLETE;
1158 spin_unlock_bh(&txq->axq_lock);
1160 ath_tx_flush_tid(sc, txtid);
1163 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1164 struct ath_node *an)
1166 struct ath_atx_tid *tid;
1167 struct ath_atx_ac *ac;
1168 struct ath_txq *txq;
1172 for (tidno = 0, tid = &an->tid[tidno];
1173 tidno < WME_NUM_TID; tidno++, tid++) {
1181 spin_lock_bh(&txq->axq_lock);
1183 buffered = !skb_queue_empty(&tid->buf_q);
1186 list_del(&tid->list);
1190 list_del(&ac->list);
1193 spin_unlock_bh(&txq->axq_lock);
1195 ieee80211_sta_set_buffered(sta, tidno, buffered);
1199 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1201 struct ath_atx_tid *tid;
1202 struct ath_atx_ac *ac;
1203 struct ath_txq *txq;
1206 for (tidno = 0, tid = &an->tid[tidno];
1207 tidno < WME_NUM_TID; tidno++, tid++) {
1212 spin_lock_bh(&txq->axq_lock);
1213 ac->clear_ps_filter = true;
1215 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1216 ath_tx_queue_tid(txq, tid);
1217 ath_txq_schedule(sc, txq);
1220 spin_unlock_bh(&txq->axq_lock);
1224 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1226 struct ath_atx_tid *txtid;
1227 struct ath_node *an;
1229 an = (struct ath_node *)sta->drv_priv;
1231 if (sc->sc_flags & SC_OP_TXAGGR) {
1232 txtid = ATH_AN_2_TID(an, tid);
1234 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1235 txtid->state |= AGGR_ADDBA_COMPLETE;
1236 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1237 ath_tx_resume_tid(sc, txtid);
1241 /********************/
1242 /* Queue Management */
1243 /********************/
1245 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1246 struct ath_txq *txq)
1248 struct ath_atx_ac *ac, *ac_tmp;
1249 struct ath_atx_tid *tid, *tid_tmp;
1251 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1252 list_del(&ac->list);
1254 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1255 list_del(&tid->list);
1257 ath_tid_drain(sc, txq, tid);
1262 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1264 struct ath_hw *ah = sc->sc_ah;
1265 struct ath9k_tx_queue_info qi;
1266 static const int subtype_txq_to_hwq[] = {
1267 [WME_AC_BE] = ATH_TXQ_AC_BE,
1268 [WME_AC_BK] = ATH_TXQ_AC_BK,
1269 [WME_AC_VI] = ATH_TXQ_AC_VI,
1270 [WME_AC_VO] = ATH_TXQ_AC_VO,
1274 memset(&qi, 0, sizeof(qi));
1275 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1276 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1277 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1278 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1279 qi.tqi_physCompBuf = 0;
1282 * Enable interrupts only for EOL and DESC conditions.
1283 * We mark tx descriptors to receive a DESC interrupt
1284 * when a tx queue gets deep; otherwise waiting for the
1285 * EOL to reap descriptors. Note that this is done to
1286 * reduce interrupt load and this only defers reaping
1287 * descriptors, never transmitting frames. Aside from
1288 * reducing interrupts this also permits more concurrency.
1289 * The only potential downside is if the tx queue backs
1290 * up in which case the top half of the kernel may backup
1291 * due to a lack of tx descriptors.
1293 * The UAPSD queue is an exception, since we take a desc-
1294 * based intr on the EOSP frames.
1296 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1297 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1298 TXQ_FLAG_TXERRINT_ENABLE;
1300 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1301 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1303 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1304 TXQ_FLAG_TXDESCINT_ENABLE;
1306 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1307 if (axq_qnum == -1) {
1309 * NB: don't print a message, this happens
1310 * normally on parts with too few tx queues
1314 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1315 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1317 txq->axq_qnum = axq_qnum;
1318 txq->mac80211_qnum = -1;
1319 txq->axq_link = NULL;
1320 INIT_LIST_HEAD(&txq->axq_q);
1321 INIT_LIST_HEAD(&txq->axq_acq);
1322 spin_lock_init(&txq->axq_lock);
1324 txq->axq_ampdu_depth = 0;
1325 txq->axq_tx_inprogress = false;
1326 sc->tx.txqsetup |= 1<<axq_qnum;
1328 txq->txq_headidx = txq->txq_tailidx = 0;
1329 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1330 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1332 return &sc->tx.txq[axq_qnum];
1335 int ath_txq_update(struct ath_softc *sc, int qnum,
1336 struct ath9k_tx_queue_info *qinfo)
1338 struct ath_hw *ah = sc->sc_ah;
1340 struct ath9k_tx_queue_info qi;
1342 if (qnum == sc->beacon.beaconq) {
1344 * XXX: for beacon queue, we just save the parameter.
1345 * It will be picked up by ath_beaconq_config when
1348 sc->beacon.beacon_qi = *qinfo;
1352 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1354 ath9k_hw_get_txq_props(ah, qnum, &qi);
1355 qi.tqi_aifs = qinfo->tqi_aifs;
1356 qi.tqi_cwmin = qinfo->tqi_cwmin;
1357 qi.tqi_cwmax = qinfo->tqi_cwmax;
1358 qi.tqi_burstTime = qinfo->tqi_burstTime;
1359 qi.tqi_readyTime = qinfo->tqi_readyTime;
1361 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1362 ath_err(ath9k_hw_common(sc->sc_ah),
1363 "Unable to update hardware queue %u!\n", qnum);
1366 ath9k_hw_resettxqueue(ah, qnum);
1372 int ath_cabq_update(struct ath_softc *sc)
1374 struct ath9k_tx_queue_info qi;
1375 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1376 int qnum = sc->beacon.cabq->axq_qnum;
1378 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1380 * Ensure the readytime % is within the bounds.
1382 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1383 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1384 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1385 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1387 qi.tqi_readyTime = (cur_conf->beacon_interval *
1388 sc->config.cabqReadytime) / 100;
1389 ath_txq_update(sc, qnum, &qi);
1394 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1396 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1397 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1400 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1401 struct list_head *list, bool retry_tx)
1402 __releases(txq->axq_lock)
1403 __acquires(txq->axq_lock)
1405 struct ath_buf *bf, *lastbf;
1406 struct list_head bf_head;
1407 struct ath_tx_status ts;
1409 memset(&ts, 0, sizeof(ts));
1410 ts.ts_status = ATH9K_TX_FLUSH;
1411 INIT_LIST_HEAD(&bf_head);
1413 while (!list_empty(list)) {
1414 bf = list_first_entry(list, struct ath_buf, list);
1417 list_del(&bf->list);
1419 ath_tx_return_buffer(sc, bf);
1423 lastbf = bf->bf_lastbf;
1424 list_cut_position(&bf_head, list, &lastbf->list);
1427 if (bf_is_ampdu_not_probing(bf))
1428 txq->axq_ampdu_depth--;
1430 spin_unlock_bh(&txq->axq_lock);
1432 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1435 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1436 spin_lock_bh(&txq->axq_lock);
1441 * Drain a given TX queue (could be Beacon or Data)
1443 * This assumes output has been stopped and
1444 * we do not need to block ath_tx_tasklet.
1446 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1448 spin_lock_bh(&txq->axq_lock);
1449 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1450 int idx = txq->txq_tailidx;
1452 while (!list_empty(&txq->txq_fifo[idx])) {
1453 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1456 INCR(idx, ATH_TXFIFO_DEPTH);
1458 txq->txq_tailidx = idx;
1461 txq->axq_link = NULL;
1462 txq->axq_tx_inprogress = false;
1463 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1465 /* flush any pending frames if aggregation is enabled */
1466 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1467 ath_txq_drain_pending_buffers(sc, txq);
1469 spin_unlock_bh(&txq->axq_lock);
1472 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1474 struct ath_hw *ah = sc->sc_ah;
1475 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1476 struct ath_txq *txq;
1480 if (sc->sc_flags & SC_OP_INVALID)
1483 ath9k_hw_abort_tx_dma(ah);
1485 /* Check if any queue remains active */
1486 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1487 if (!ATH_TXQ_SETUP(sc, i))
1490 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1495 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1497 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1498 if (!ATH_TXQ_SETUP(sc, i))
1502 * The caller will resume queues with ieee80211_wake_queues.
1503 * Mark the queue as not stopped to prevent ath_tx_complete
1504 * from waking the queue too early.
1506 txq = &sc->tx.txq[i];
1507 txq->stopped = false;
1508 ath_draintxq(sc, txq, retry_tx);
1514 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1516 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1517 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1520 /* For each axq_acq entry, for each tid, try to schedule packets
1521 * for transmit until ampdu_depth has reached min Q depth.
1523 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1525 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1526 struct ath_atx_tid *tid, *last_tid;
1528 if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) ||
1529 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1532 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1533 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1535 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1536 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1537 list_del(&ac->list);
1540 while (!list_empty(&ac->tid_q)) {
1541 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1543 list_del(&tid->list);
1549 ath_tx_sched_aggr(sc, txq, tid);
1552 * add tid to round-robin queue if more frames
1553 * are pending for the tid
1555 if (!skb_queue_empty(&tid->buf_q))
1556 ath_tx_queue_tid(txq, tid);
1558 if (tid == last_tid ||
1559 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1563 if (!list_empty(&ac->tid_q)) {
1566 list_add_tail(&ac->list, &txq->axq_acq);
1570 if (ac == last_ac ||
1571 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1581 * Insert a chain of ath_buf (descriptors) on a txq and
1582 * assume the descriptors are already chained together by caller.
1584 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1585 struct list_head *head, bool internal)
1587 struct ath_hw *ah = sc->sc_ah;
1588 struct ath_common *common = ath9k_hw_common(ah);
1589 struct ath_buf *bf, *bf_last;
1590 bool puttxbuf = false;
1594 * Insert the frame on the outbound list and
1595 * pass it on to the hardware.
1598 if (list_empty(head))
1601 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1602 bf = list_first_entry(head, struct ath_buf, list);
1603 bf_last = list_entry(head->prev, struct ath_buf, list);
1605 ath_dbg(common, ATH_DBG_QUEUE,
1606 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1608 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1609 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1610 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1613 list_splice_tail_init(head, &txq->axq_q);
1615 if (txq->axq_link) {
1616 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1617 ath_dbg(common, ATH_DBG_XMIT,
1618 "link[%u] (%p)=%llx (%p)\n",
1619 txq->axq_qnum, txq->axq_link,
1620 ito64(bf->bf_daddr), bf->bf_desc);
1624 txq->axq_link = bf_last->bf_desc;
1628 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1629 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1630 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1631 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1635 TX_STAT_INC(txq->axq_qnum, txstart);
1636 ath9k_hw_txstart(ah, txq->axq_qnum);
1641 if (bf_is_ampdu_not_probing(bf))
1642 txq->axq_ampdu_depth++;
1646 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1647 struct sk_buff *skb, struct ath_tx_control *txctl)
1649 struct ath_frame_info *fi = get_frame_info(skb);
1650 struct list_head bf_head;
1654 * Do not queue to h/w when any of the following conditions is true:
1655 * - there are pending frames in software queue
1656 * - the TID is currently paused for ADDBA/BAR request
1657 * - seqno is not within block-ack window
1658 * - h/w queue depth exceeds low water mark
1660 if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1661 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1662 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1664 * Add this frame to software queue for scheduling later
1667 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1668 __skb_queue_tail(&tid->buf_q, skb);
1669 if (!txctl->an || !txctl->an->sleeping)
1670 ath_tx_queue_tid(txctl->txq, tid);
1674 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb, false);
1678 bf->bf_state.bf_type = BUF_AMPDU;
1679 INIT_LIST_HEAD(&bf_head);
1680 list_add(&bf->list, &bf_head);
1682 /* Add sub-frame to BAW */
1683 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1685 /* Queue to h/w without aggregation */
1686 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1688 ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
1689 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1692 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1693 struct ath_atx_tid *tid, struct sk_buff *skb)
1695 struct ath_frame_info *fi = get_frame_info(skb);
1696 struct list_head bf_head;
1701 bf = ath_tx_setup_buffer(sc, txq, tid, skb, false);
1706 INIT_LIST_HEAD(&bf_head);
1707 list_add_tail(&bf->list, &bf_head);
1708 bf->bf_state.bf_type = 0;
1710 /* update starting sequence number for subsequent ADDBA request */
1712 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1716 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1717 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1718 TX_STAT_INC(txq->axq_qnum, queued);
1721 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1724 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1725 struct ieee80211_sta *sta = tx_info->control.sta;
1726 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1727 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1728 struct ath_frame_info *fi = get_frame_info(skb);
1729 struct ath_node *an = NULL;
1730 enum ath9k_key_type keytype;
1732 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1735 an = (struct ath_node *) sta->drv_priv;
1737 memset(fi, 0, sizeof(*fi));
1739 fi->keyix = hw_key->hw_key_idx;
1740 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1741 fi->keyix = an->ps_key;
1743 fi->keyix = ATH9K_TXKEYIX_INVALID;
1744 fi->keytype = keytype;
1745 fi->framelen = framelen;
1748 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1750 struct ath_hw *ah = sc->sc_ah;
1751 struct ath9k_channel *curchan = ah->curchan;
1752 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1753 (curchan->channelFlags & CHANNEL_5GHZ) &&
1754 (chainmask == 0x7) && (rate < 0x90))
1761 * Assign a descriptor (and sequence number if necessary,
1762 * and map buffer for DMA. Frees skb on error
1764 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1765 struct ath_txq *txq,
1766 struct ath_atx_tid *tid,
1767 struct sk_buff *skb,
1770 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1771 struct ath_frame_info *fi = get_frame_info(skb);
1772 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1776 bf = ath_tx_get_buffer(sc);
1778 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1782 ATH_TXBUF_RESET(bf);
1785 seqno = tid->seq_next;
1786 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1787 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1788 bf->bf_state.seqno = seqno;
1793 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1794 skb->len, DMA_TO_DEVICE);
1795 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1797 bf->bf_buf_addr = 0;
1798 ath_err(ath9k_hw_common(sc->sc_ah),
1799 "dma_mapping_error() on TX\n");
1800 ath_tx_return_buffer(sc, bf);
1810 __skb_unlink(skb, &tid->buf_q);
1811 dev_kfree_skb_any(skb);
1815 /* FIXME: tx power */
1816 static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
1817 struct ath_tx_control *txctl)
1819 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1820 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1821 struct ath_atx_tid *tid = NULL;
1825 spin_lock_bh(&txctl->txq->axq_lock);
1826 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1827 ieee80211_is_data_qos(hdr->frame_control)) {
1828 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1829 IEEE80211_QOS_CTL_TID_MASK;
1830 tid = ATH_AN_2_TID(txctl->an, tidno);
1832 WARN_ON(tid->ac->txq != txctl->txq);
1835 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1837 * Try aggregation if it's a unicast data frame
1838 * and the destination is HT capable.
1840 ath_tx_send_ampdu(sc, tid, skb, txctl);
1842 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb, false);
1846 bf->bf_state.bfs_paprd = txctl->paprd;
1849 bf->bf_state.bfs_paprd_timestamp = jiffies;
1851 ath_tx_send_normal(sc, txctl->txq, tid, skb);
1855 spin_unlock_bh(&txctl->txq->axq_lock);
1858 /* Upon failure caller should free skb */
1859 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1860 struct ath_tx_control *txctl)
1862 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1863 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1864 struct ieee80211_sta *sta = info->control.sta;
1865 struct ieee80211_vif *vif = info->control.vif;
1866 struct ath_softc *sc = hw->priv;
1867 struct ath_txq *txq = txctl->txq;
1868 int padpos, padsize;
1869 int frmlen = skb->len + FCS_LEN;
1872 /* NOTE: sta can be NULL according to net/mac80211.h */
1874 txctl->an = (struct ath_node *)sta->drv_priv;
1876 if (info->control.hw_key)
1877 frmlen += info->control.hw_key->icv_len;
1880 * As a temporary workaround, assign seq# here; this will likely need
1881 * to be cleaned up to work better with Beacon transmission and virtual
1884 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1885 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1886 sc->tx.seq_no += 0x10;
1887 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1888 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1891 /* Add the padding after the header if this is not already done */
1892 padpos = ath9k_cmn_padpos(hdr->frame_control);
1893 padsize = padpos & 3;
1894 if (padsize && skb->len > padpos) {
1895 if (skb_headroom(skb) < padsize)
1898 skb_push(skb, padsize);
1899 memmove(skb->data, skb->data + padsize, padpos);
1900 hdr = (struct ieee80211_hdr *) skb->data;
1903 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1904 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1905 !ieee80211_is_data(hdr->frame_control))
1906 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1908 setup_frame_info(hw, skb, frmlen);
1911 * At this point, the vif, hw_key and sta pointers in the tx control
1912 * info are no longer valid (overwritten by the ath_frame_info data.
1915 q = skb_get_queue_mapping(skb);
1916 spin_lock_bh(&txq->axq_lock);
1917 if (txq == sc->tx.txq_map[q] &&
1918 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1919 ieee80211_stop_queue(sc->hw, q);
1922 spin_unlock_bh(&txq->axq_lock);
1924 ath_tx_start_dma(sc, skb, txctl);
1932 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1933 int tx_flags, struct ath_txq *txq)
1935 struct ieee80211_hw *hw = sc->hw;
1936 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1937 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1938 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1939 int q, padpos, padsize;
1941 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1943 if (tx_flags & ATH_TX_BAR)
1944 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1946 if (!(tx_flags & ATH_TX_ERROR))
1947 /* Frame was ACKed */
1948 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1950 padpos = ath9k_cmn_padpos(hdr->frame_control);
1951 padsize = padpos & 3;
1952 if (padsize && skb->len>padpos+padsize) {
1954 * Remove MAC header padding before giving the frame back to
1957 memmove(skb->data + padsize, skb->data, padpos);
1958 skb_pull(skb, padsize);
1961 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1962 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1963 ath_dbg(common, ATH_DBG_PS,
1964 "Going back to sleep after having received TX status (0x%lx)\n",
1965 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1967 PS_WAIT_FOR_PSPOLL_DATA |
1968 PS_WAIT_FOR_TX_ACK));
1971 q = skb_get_queue_mapping(skb);
1972 if (txq == sc->tx.txq_map[q]) {
1973 spin_lock_bh(&txq->axq_lock);
1974 if (WARN_ON(--txq->pending_frames < 0))
1975 txq->pending_frames = 0;
1977 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1978 ieee80211_wake_queue(sc->hw, q);
1981 spin_unlock_bh(&txq->axq_lock);
1984 ieee80211_tx_status(hw, skb);
1987 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1988 struct ath_txq *txq, struct list_head *bf_q,
1989 struct ath_tx_status *ts, int txok, int sendbar)
1991 struct sk_buff *skb = bf->bf_mpdu;
1992 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1993 unsigned long flags;
1997 tx_flags = ATH_TX_BAR;
2000 tx_flags |= ATH_TX_ERROR;
2002 if (ts->ts_status & ATH9K_TXERR_FILT)
2003 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2005 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2006 bf->bf_buf_addr = 0;
2008 if (bf->bf_state.bfs_paprd) {
2009 if (time_after(jiffies,
2010 bf->bf_state.bfs_paprd_timestamp +
2011 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2012 dev_kfree_skb_any(skb);
2014 complete(&sc->paprd_complete);
2016 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2017 ath_tx_complete(sc, skb, tx_flags, txq);
2019 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2020 * accidentally reference it later.
2025 * Return the list of ath_buf of this mpdu to free queue
2027 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2028 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2029 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2032 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2033 struct ath_tx_status *ts, int nframes, int nbad,
2036 struct sk_buff *skb = bf->bf_mpdu;
2037 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2038 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2039 struct ieee80211_hw *hw = sc->hw;
2040 struct ath_hw *ah = sc->sc_ah;
2044 tx_info->status.ack_signal = ts->ts_rssi;
2046 tx_rateindex = ts->ts_rateindex;
2047 WARN_ON(tx_rateindex >= hw->max_rates);
2049 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2050 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2052 BUG_ON(nbad > nframes);
2054 tx_info->status.ampdu_len = nframes;
2055 tx_info->status.ampdu_ack_len = nframes - nbad;
2057 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2058 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2060 * If an underrun error is seen assume it as an excessive
2061 * retry only if max frame trigger level has been reached
2062 * (2 KB for single stream, and 4 KB for dual stream).
2063 * Adjust the long retry as if the frame was tried
2064 * hw->max_rate_tries times to affect how rate control updates
2065 * PER for the failed rate.
2066 * In case of congestion on the bus penalizing this type of
2067 * underruns should help hardware actually transmit new frames
2068 * successfully by eventually preferring slower rates.
2069 * This itself should also alleviate congestion on the bus.
2071 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2072 ATH9K_TX_DELIM_UNDERRUN)) &&
2073 ieee80211_is_data(hdr->frame_control) &&
2074 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2075 tx_info->status.rates[tx_rateindex].count =
2079 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2080 tx_info->status.rates[i].count = 0;
2081 tx_info->status.rates[i].idx = -1;
2084 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2087 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2088 struct ath_tx_status *ts, struct ath_buf *bf,
2089 struct list_head *bf_head)
2090 __releases(txq->axq_lock)
2091 __acquires(txq->axq_lock)
2096 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2097 txq->axq_tx_inprogress = false;
2098 if (bf_is_ampdu_not_probing(bf))
2099 txq->axq_ampdu_depth--;
2101 spin_unlock_bh(&txq->axq_lock);
2103 if (!bf_isampdu(bf)) {
2104 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
2105 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2107 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2109 spin_lock_bh(&txq->axq_lock);
2111 if (sc->sc_flags & SC_OP_TXAGGR)
2112 ath_txq_schedule(sc, txq);
2115 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2117 struct ath_hw *ah = sc->sc_ah;
2118 struct ath_common *common = ath9k_hw_common(ah);
2119 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2120 struct list_head bf_head;
2121 struct ath_desc *ds;
2122 struct ath_tx_status ts;
2125 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2126 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2129 spin_lock_bh(&txq->axq_lock);
2131 if (work_pending(&sc->hw_reset_work))
2134 if (list_empty(&txq->axq_q)) {
2135 txq->axq_link = NULL;
2136 if (sc->sc_flags & SC_OP_TXAGGR)
2137 ath_txq_schedule(sc, txq);
2140 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2143 * There is a race condition that a BH gets scheduled
2144 * after sw writes TxE and before hw re-load the last
2145 * descriptor to get the newly chained one.
2146 * Software must keep the last DONE descriptor as a
2147 * holding descriptor - software does so by marking
2148 * it with the STALE flag.
2153 if (list_is_last(&bf_held->list, &txq->axq_q))
2156 bf = list_entry(bf_held->list.next, struct ath_buf,
2160 lastbf = bf->bf_lastbf;
2161 ds = lastbf->bf_desc;
2163 memset(&ts, 0, sizeof(ts));
2164 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2165 if (status == -EINPROGRESS)
2168 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2171 * Remove ath_buf's of the same transmit unit from txq,
2172 * however leave the last descriptor back as the holding
2173 * descriptor for hw.
2175 lastbf->bf_stale = true;
2176 INIT_LIST_HEAD(&bf_head);
2177 if (!list_is_singular(&lastbf->list))
2178 list_cut_position(&bf_head,
2179 &txq->axq_q, lastbf->list.prev);
2182 list_del(&bf_held->list);
2183 ath_tx_return_buffer(sc, bf_held);
2186 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2188 spin_unlock_bh(&txq->axq_lock);
2191 static void ath_tx_complete_poll_work(struct work_struct *work)
2193 struct ath_softc *sc = container_of(work, struct ath_softc,
2194 tx_complete_work.work);
2195 struct ath_txq *txq;
2197 bool needreset = false;
2198 #ifdef CONFIG_ATH9K_DEBUGFS
2199 sc->tx_complete_poll_work_seen++;
2202 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2203 if (ATH_TXQ_SETUP(sc, i)) {
2204 txq = &sc->tx.txq[i];
2205 spin_lock_bh(&txq->axq_lock);
2206 if (txq->axq_depth) {
2207 if (txq->axq_tx_inprogress) {
2209 spin_unlock_bh(&txq->axq_lock);
2212 txq->axq_tx_inprogress = true;
2215 spin_unlock_bh(&txq->axq_lock);
2219 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2220 "tx hung, resetting the chip\n");
2221 RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
2222 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2225 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2226 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2231 void ath_tx_tasklet(struct ath_softc *sc)
2234 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2236 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2238 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2239 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2240 ath_tx_processq(sc, &sc->tx.txq[i]);
2244 void ath_tx_edma_tasklet(struct ath_softc *sc)
2246 struct ath_tx_status ts;
2247 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2248 struct ath_hw *ah = sc->sc_ah;
2249 struct ath_txq *txq;
2250 struct ath_buf *bf, *lastbf;
2251 struct list_head bf_head;
2255 if (work_pending(&sc->hw_reset_work))
2258 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2259 if (status == -EINPROGRESS)
2261 if (status == -EIO) {
2262 ath_dbg(common, ATH_DBG_XMIT,
2263 "Error processing tx status\n");
2267 /* Skip beacon completions */
2268 if (ts.qid == sc->beacon.beaconq)
2271 txq = &sc->tx.txq[ts.qid];
2273 spin_lock_bh(&txq->axq_lock);
2275 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2276 spin_unlock_bh(&txq->axq_lock);
2280 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2281 struct ath_buf, list);
2282 lastbf = bf->bf_lastbf;
2284 INIT_LIST_HEAD(&bf_head);
2285 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2288 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2289 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2291 if (!list_empty(&txq->axq_q)) {
2292 struct list_head bf_q;
2294 INIT_LIST_HEAD(&bf_q);
2295 txq->axq_link = NULL;
2296 list_splice_tail_init(&txq->axq_q, &bf_q);
2297 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2301 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2302 spin_unlock_bh(&txq->axq_lock);
2310 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2312 struct ath_descdma *dd = &sc->txsdma;
2313 u8 txs_len = sc->sc_ah->caps.txs_len;
2315 dd->dd_desc_len = size * txs_len;
2316 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2317 &dd->dd_desc_paddr, GFP_KERNEL);
2324 static int ath_tx_edma_init(struct ath_softc *sc)
2328 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2330 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2331 sc->txsdma.dd_desc_paddr,
2332 ATH_TXSTATUS_RING_SIZE);
2337 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2339 struct ath_descdma *dd = &sc->txsdma;
2341 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2345 int ath_tx_init(struct ath_softc *sc, int nbufs)
2347 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2350 spin_lock_init(&sc->tx.txbuflock);
2352 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2356 "Failed to allocate tx descriptors: %d\n", error);
2360 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2361 "beacon", ATH_BCBUF, 1, 1);
2364 "Failed to allocate beacon descriptors: %d\n", error);
2368 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2370 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2371 error = ath_tx_edma_init(sc);
2383 void ath_tx_cleanup(struct ath_softc *sc)
2385 if (sc->beacon.bdma.dd_desc_len != 0)
2386 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2388 if (sc->tx.txdma.dd_desc_len != 0)
2389 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2391 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2392 ath_tx_edma_cleanup(sc);
2395 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2397 struct ath_atx_tid *tid;
2398 struct ath_atx_ac *ac;
2401 for (tidno = 0, tid = &an->tid[tidno];
2402 tidno < WME_NUM_TID;
2406 tid->seq_start = tid->seq_next = 0;
2407 tid->baw_size = WME_MAX_BA;
2408 tid->baw_head = tid->baw_tail = 0;
2410 tid->paused = false;
2411 tid->state &= ~AGGR_CLEANUP;
2412 __skb_queue_head_init(&tid->buf_q);
2413 acno = TID_TO_WME_AC(tidno);
2414 tid->ac = &an->ac[acno];
2415 tid->state &= ~AGGR_ADDBA_COMPLETE;
2416 tid->state &= ~AGGR_ADDBA_PROGRESS;
2419 for (acno = 0, ac = &an->ac[acno];
2420 acno < WME_NUM_AC; acno++, ac++) {
2422 ac->txq = sc->tx.txq_map[acno];
2423 INIT_LIST_HEAD(&ac->tid_q);
2427 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2429 struct ath_atx_ac *ac;
2430 struct ath_atx_tid *tid;
2431 struct ath_txq *txq;
2434 for (tidno = 0, tid = &an->tid[tidno];
2435 tidno < WME_NUM_TID; tidno++, tid++) {
2440 spin_lock_bh(&txq->axq_lock);
2443 list_del(&tid->list);
2448 list_del(&ac->list);
2449 tid->ac->sched = false;
2452 ath_tid_drain(sc, txq, tid);
2453 tid->state &= ~AGGR_ADDBA_COMPLETE;
2454 tid->state &= ~AGGR_CLEANUP;
2456 spin_unlock_bh(&txq->axq_lock);