2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 static u16 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
66 struct ath_atx_tid *tid,
76 static int ath_max_4ms_framelen[4][32] = {
78 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
79 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
80 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
81 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
84 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
85 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
86 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
87 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
90 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
91 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
92 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
93 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
96 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
97 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
98 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
99 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
103 /*********************/
104 /* Aggregation logic */
105 /*********************/
107 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
109 struct ath_atx_ac *ac = tid->ac;
118 list_add_tail(&tid->list, &ac->tid_q);
124 list_add_tail(&ac->list, &txq->axq_acq);
127 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
129 struct ath_txq *txq = tid->ac->txq;
131 WARN_ON(!tid->paused);
133 spin_lock_bh(&txq->axq_lock);
136 if (skb_queue_empty(&tid->buf_q))
139 ath_tx_queue_tid(txq, tid);
140 ath_txq_schedule(sc, txq);
142 spin_unlock_bh(&txq->axq_lock);
145 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
147 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
148 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
149 sizeof(tx_info->rate_driver_data));
150 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
153 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
155 struct ath_txq *txq = tid->ac->txq;
158 struct list_head bf_head;
159 struct ath_tx_status ts;
160 struct ath_frame_info *fi;
162 INIT_LIST_HEAD(&bf_head);
164 memset(&ts, 0, sizeof(ts));
165 spin_lock_bh(&txq->axq_lock);
167 while ((skb = __skb_dequeue(&tid->buf_q))) {
168 fi = get_frame_info(skb);
171 spin_unlock_bh(&txq->axq_lock);
172 if (bf && fi->retries) {
173 list_add_tail(&bf->list, &bf_head);
174 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
175 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
177 ath_tx_send_normal(sc, txq, NULL, skb);
179 spin_lock_bh(&txq->axq_lock);
182 spin_unlock_bh(&txq->axq_lock);
185 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
190 index = ATH_BA_INDEX(tid->seq_start, seqno);
191 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
193 __clear_bit(cindex, tid->tx_buf);
195 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
196 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
197 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
201 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
206 index = ATH_BA_INDEX(tid->seq_start, seqno);
207 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
208 __set_bit(cindex, tid->tx_buf);
210 if (index >= ((tid->baw_tail - tid->baw_head) &
211 (ATH_TID_MAX_BUFS - 1))) {
212 tid->baw_tail = cindex;
213 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
218 * TODO: For frame(s) that are in the retry state, we will reuse the
219 * sequence number(s) without setting the retry bit. The
220 * alternative is to give up on these and BAR the receiver's window
223 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
224 struct ath_atx_tid *tid)
229 struct list_head bf_head;
230 struct ath_tx_status ts;
231 struct ath_frame_info *fi;
233 memset(&ts, 0, sizeof(ts));
234 INIT_LIST_HEAD(&bf_head);
236 while ((skb = __skb_dequeue(&tid->buf_q))) {
237 fi = get_frame_info(skb);
241 spin_unlock(&txq->axq_lock);
242 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
243 spin_lock(&txq->axq_lock);
247 list_add_tail(&bf->list, &bf_head);
250 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
252 spin_unlock(&txq->axq_lock);
253 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
254 spin_lock(&txq->axq_lock);
257 tid->seq_next = tid->seq_start;
258 tid->baw_tail = tid->baw_head;
261 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
264 struct ath_frame_info *fi = get_frame_info(skb);
265 struct ath_buf *bf = fi->bf;
266 struct ieee80211_hdr *hdr;
268 TX_STAT_INC(txq->axq_qnum, a_retries);
269 if (fi->retries++ > 0)
272 hdr = (struct ieee80211_hdr *)skb->data;
273 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
274 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
275 sizeof(*hdr), DMA_TO_DEVICE);
278 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
280 struct ath_buf *bf = NULL;
282 spin_lock_bh(&sc->tx.txbuflock);
284 if (unlikely(list_empty(&sc->tx.txbuf))) {
285 spin_unlock_bh(&sc->tx.txbuflock);
289 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
292 spin_unlock_bh(&sc->tx.txbuflock);
297 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
299 spin_lock_bh(&sc->tx.txbuflock);
300 list_add_tail(&bf->list, &sc->tx.txbuf);
301 spin_unlock_bh(&sc->tx.txbuflock);
304 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
308 tbf = ath_tx_get_buffer(sc);
312 ATH_TXBUF_RESET(tbf);
314 tbf->bf_mpdu = bf->bf_mpdu;
315 tbf->bf_buf_addr = bf->bf_buf_addr;
316 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
317 tbf->bf_state = bf->bf_state;
322 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
323 struct ath_tx_status *ts, int txok,
324 int *nframes, int *nbad)
326 struct ath_frame_info *fi;
328 u32 ba[WME_BA_BMP_SIZE >> 5];
335 isaggr = bf_isaggr(bf);
337 seq_st = ts->ts_seqnum;
338 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
342 fi = get_frame_info(bf->bf_mpdu);
343 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
346 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
354 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
355 struct ath_buf *bf, struct list_head *bf_q,
356 struct ath_tx_status *ts, int txok, bool retry)
358 struct ath_node *an = NULL;
360 struct ieee80211_sta *sta;
361 struct ieee80211_hw *hw = sc->hw;
362 struct ieee80211_hdr *hdr;
363 struct ieee80211_tx_info *tx_info;
364 struct ath_atx_tid *tid = NULL;
365 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
366 struct list_head bf_head;
367 struct sk_buff_head bf_pending;
368 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
369 u32 ba[WME_BA_BMP_SIZE >> 5];
370 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
371 bool rc_update = true;
372 struct ieee80211_tx_rate rates[4];
373 struct ath_frame_info *fi;
376 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
379 hdr = (struct ieee80211_hdr *)skb->data;
381 tx_info = IEEE80211_SKB_CB(skb);
383 memcpy(rates, tx_info->control.rates, sizeof(rates));
387 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
391 INIT_LIST_HEAD(&bf_head);
393 bf_next = bf->bf_next;
395 if (!bf->bf_stale || bf_next != NULL)
396 list_move_tail(&bf->list, &bf_head);
398 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
406 an = (struct ath_node *)sta->drv_priv;
407 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
408 tid = ATH_AN_2_TID(an, tidno);
411 * The hardware occasionally sends a tx status for the wrong TID.
412 * In this case, the BA status cannot be considered valid and all
413 * subframes need to be retransmitted
415 if (tidno != ts->tid)
418 isaggr = bf_isaggr(bf);
419 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
421 if (isaggr && txok) {
422 if (ts->ts_flags & ATH9K_TX_BA) {
423 seq_st = ts->ts_seqnum;
424 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
427 * AR5416 can become deaf/mute when BA
428 * issue happens. Chip needs to be reset.
429 * But AP code may have sychronization issues
430 * when perform internal reset in this routine.
431 * Only enable reset in STA mode for now.
433 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
438 __skb_queue_head_init(&bf_pending);
440 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
442 u16 seqno = bf->bf_state.seqno;
444 txfail = txpending = sendbar = 0;
445 bf_next = bf->bf_next;
448 tx_info = IEEE80211_SKB_CB(skb);
449 fi = get_frame_info(skb);
451 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
452 /* transmit completion, subframe is
453 * acked by block ack */
455 } else if (!isaggr && txok) {
456 /* transmit completion */
459 if ((tid->state & AGGR_CLEANUP) || !retry) {
461 * cleanup in progress, just fail
462 * the un-acked sub-frames
467 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
468 if (txok || !an->sleeping)
469 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
480 * Make sure the last desc is reclaimed if it
481 * not a holding desc.
483 INIT_LIST_HEAD(&bf_head);
484 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
485 bf_next != NULL || !bf_last->bf_stale)
486 list_move_tail(&bf->list, &bf_head);
488 if (!txpending || (tid->state & AGGR_CLEANUP)) {
490 * complete the acked-ones/xretried ones; update
493 spin_lock_bh(&txq->axq_lock);
494 ath_tx_update_baw(sc, tid, seqno);
495 spin_unlock_bh(&txq->axq_lock);
497 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
498 memcpy(tx_info->control.rates, rates, sizeof(rates));
499 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
503 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
506 /* retry the un-acked ones */
507 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
508 if (bf->bf_next == NULL && bf_last->bf_stale) {
511 tbf = ath_clone_txbuf(sc, bf_last);
513 * Update tx baw and complete the
514 * frame with failed status if we
518 spin_lock_bh(&txq->axq_lock);
519 ath_tx_update_baw(sc, tid, seqno);
520 spin_unlock_bh(&txq->axq_lock);
522 ath_tx_complete_buf(sc, bf, txq,
534 * Put this buffer to the temporary pending
535 * queue to retain ordering
537 __skb_queue_tail(&bf_pending, skb);
543 /* prepend un-acked frames to the beginning of the pending frame queue */
544 if (!skb_queue_empty(&bf_pending)) {
546 ieee80211_sta_set_buffered(sta, tid->tidno, true);
548 spin_lock_bh(&txq->axq_lock);
549 skb_queue_splice(&bf_pending, &tid->buf_q);
551 ath_tx_queue_tid(txq, tid);
553 if (ts->ts_status & ATH9K_TXERR_FILT)
554 tid->ac->clear_ps_filter = true;
556 spin_unlock_bh(&txq->axq_lock);
559 if (tid->state & AGGR_CLEANUP) {
560 ath_tx_flush_tid(sc, tid);
562 if (tid->baw_head == tid->baw_tail) {
563 tid->state &= ~AGGR_ADDBA_COMPLETE;
564 tid->state &= ~AGGR_CLEANUP;
571 RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR);
572 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
576 static bool ath_lookup_legacy(struct ath_buf *bf)
579 struct ieee80211_tx_info *tx_info;
580 struct ieee80211_tx_rate *rates;
584 tx_info = IEEE80211_SKB_CB(skb);
585 rates = tx_info->control.rates;
587 for (i = 0; i < 4; i++) {
588 if (!rates[i].count || rates[i].idx < 0)
591 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
598 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
599 struct ath_atx_tid *tid)
602 struct ieee80211_tx_info *tx_info;
603 struct ieee80211_tx_rate *rates;
604 u32 max_4ms_framelen, frmlen;
605 u16 aggr_limit, legacy = 0;
609 tx_info = IEEE80211_SKB_CB(skb);
610 rates = tx_info->control.rates;
613 * Find the lowest frame length among the rate series that will have a
614 * 4ms transmit duration.
615 * TODO - TXOP limit needs to be considered.
617 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
619 for (i = 0; i < 4; i++) {
620 if (rates[i].count) {
622 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
627 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
632 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
635 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
636 max_4ms_framelen = min(max_4ms_framelen, frmlen);
641 * limit aggregate size by the minimum rate if rate selected is
642 * not a probe rate, if rate selected is a probe rate then
643 * avoid aggregation of this packet.
645 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
648 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
649 aggr_limit = min((max_4ms_framelen * 3) / 8,
650 (u32)ATH_AMPDU_LIMIT_MAX);
652 aggr_limit = min(max_4ms_framelen,
653 (u32)ATH_AMPDU_LIMIT_MAX);
656 * h/w can accept aggregates up to 16 bit lengths (65535).
657 * The IE, however can hold up to 65536, which shows up here
658 * as zero. Ignore 65536 since we are constrained by hw.
660 if (tid->an->maxampdu)
661 aggr_limit = min(aggr_limit, tid->an->maxampdu);
667 * Returns the number of delimiters to be added to
668 * meet the minimum required mpdudensity.
670 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
671 struct ath_buf *bf, u16 frmlen,
674 #define FIRST_DESC_NDELIMS 60
675 struct sk_buff *skb = bf->bf_mpdu;
676 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
677 u32 nsymbits, nsymbols;
680 int width, streams, half_gi, ndelim, mindelim;
681 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
683 /* Select standard number of delimiters based on frame length alone */
684 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
687 * If encryption enabled, hardware requires some more padding between
689 * TODO - this could be improved to be dependent on the rate.
690 * The hardware can keep up at lower rates, but not higher rates
692 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
693 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
694 ndelim += ATH_AGGR_ENCRYPTDELIM;
697 * Add delimiter when using RTS/CTS with aggregation
698 * and non enterprise AR9003 card
700 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
701 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
702 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
705 * Convert desired mpdu density from microeconds to bytes based
706 * on highest rate in rate series (i.e. first rate) to determine
707 * required minimum length for subframe. Take into account
708 * whether high rate is 20 or 40Mhz and half or full GI.
710 * If there is no mpdu density restriction, no further calculation
714 if (tid->an->mpdudensity == 0)
717 rix = tx_info->control.rates[0].idx;
718 flags = tx_info->control.rates[0].flags;
719 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
720 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
723 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
725 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
730 streams = HT_RC_2_STREAMS(rix);
731 nsymbits = bits_per_symbol[rix % 8][width] * streams;
732 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
734 if (frmlen < minlen) {
735 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
736 ndelim = max(mindelim, ndelim);
742 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
744 struct ath_atx_tid *tid,
745 struct list_head *bf_q,
748 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
749 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
750 int rl = 0, nframes = 0, ndelim, prev_al = 0;
751 u16 aggr_limit = 0, al = 0, bpad = 0,
752 al_delta, h_baw = tid->baw_size / 2;
753 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
754 struct ieee80211_tx_info *tx_info;
755 struct ath_frame_info *fi;
760 skb = skb_peek(&tid->buf_q);
761 fi = get_frame_info(skb);
764 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
769 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
770 seqno = bf->bf_state.seqno;
774 /* do not step over block-ack window */
775 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
776 status = ATH_AGGR_BAW_CLOSED;
781 aggr_limit = ath_lookup_rate(sc, bf, tid);
785 /* do not exceed aggregation limit */
786 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
789 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
790 ath_lookup_legacy(bf))) {
791 status = ATH_AGGR_LIMITED;
795 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
796 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
799 /* do not exceed subframe limit */
800 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
801 status = ATH_AGGR_LIMITED;
805 /* add padding for previous frame to aggregation length */
806 al += bpad + al_delta;
809 * Get the delimiters needed to meet the MPDU
810 * density for this node.
812 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
814 bpad = PADBYTES(al_delta) + (ndelim << 2);
819 /* link buffers of this frame to the aggregate */
821 ath_tx_addto_baw(sc, tid, seqno);
822 bf->bf_state.ndelim = ndelim;
824 __skb_unlink(skb, &tid->buf_q);
825 list_add_tail(&bf->list, bf_q);
827 bf_prev->bf_next = bf;
831 } while (!skb_queue_empty(&tid->buf_q));
841 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
842 * width - 0 for 20 MHz, 1 for 40 MHz
843 * half_gi - to use 4us v/s 3.6 us for symbol time
845 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
846 int width, int half_gi, bool shortPreamble)
848 u32 nbits, nsymbits, duration, nsymbols;
851 /* find number of symbols: PLCP + data */
852 streams = HT_RC_2_STREAMS(rix);
853 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
854 nsymbits = bits_per_symbol[rix % 8][width] * streams;
855 nsymbols = (nbits + nsymbits - 1) / nsymbits;
858 duration = SYMBOL_TIME(nsymbols);
860 duration = SYMBOL_TIME_HALFGI(nsymbols);
862 /* addup duration for legacy/ht training and signal fields */
863 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
868 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
869 struct ath_tx_info *info, int len)
871 struct ath_hw *ah = sc->sc_ah;
873 struct ieee80211_tx_info *tx_info;
874 struct ieee80211_tx_rate *rates;
875 const struct ieee80211_rate *rate;
876 struct ieee80211_hdr *hdr;
881 tx_info = IEEE80211_SKB_CB(skb);
882 rates = tx_info->control.rates;
883 hdr = (struct ieee80211_hdr *)skb->data;
885 /* set dur_update_en for l-sig computation except for PS-Poll frames */
886 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
889 * We check if Short Preamble is needed for the CTS rate by
890 * checking the BSS's global flag.
891 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
893 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
894 info->rtscts_rate = rate->hw_value;
895 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
896 info->rtscts_rate |= rate->hw_value_short;
898 for (i = 0; i < 4; i++) {
899 bool is_40, is_sgi, is_sp;
902 if (!rates[i].count || (rates[i].idx < 0))
906 info->rates[i].Tries = rates[i].count;
908 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
909 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
910 info->flags |= ATH9K_TXDESC_RTSENA;
911 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
912 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
913 info->flags |= ATH9K_TXDESC_CTSENA;
916 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
917 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
918 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
919 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
921 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
922 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
923 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
925 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
927 info->rates[i].Rate = rix | 0x80;
928 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
929 ah->txchainmask, info->rates[i].Rate);
930 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
931 is_40, is_sgi, is_sp);
932 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
933 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
938 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
939 !(rate->flags & IEEE80211_RATE_ERP_G))
940 phy = WLAN_RC_PHY_CCK;
942 phy = WLAN_RC_PHY_OFDM;
944 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
945 info->rates[i].Rate = rate->hw_value;
946 if (rate->hw_value_short) {
947 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
948 info->rates[i].Rate |= rate->hw_value_short;
953 if (bf->bf_state.bfs_paprd)
954 info->rates[i].ChSel = ah->txchainmask;
956 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
957 ah->txchainmask, info->rates[i].Rate);
959 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
960 phy, rate->bitrate * 100, len, rix, is_sp);
963 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
964 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
965 info->flags &= ~ATH9K_TXDESC_RTSENA;
967 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
968 if (info->flags & ATH9K_TXDESC_RTSENA)
969 info->flags &= ~ATH9K_TXDESC_CTSENA;
972 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
974 struct ieee80211_hdr *hdr;
975 enum ath9k_pkt_type htype;
978 hdr = (struct ieee80211_hdr *)skb->data;
979 fc = hdr->frame_control;
981 if (ieee80211_is_beacon(fc))
982 htype = ATH9K_PKT_TYPE_BEACON;
983 else if (ieee80211_is_probe_resp(fc))
984 htype = ATH9K_PKT_TYPE_PROBE_RESP;
985 else if (ieee80211_is_atim(fc))
986 htype = ATH9K_PKT_TYPE_ATIM;
987 else if (ieee80211_is_pspoll(fc))
988 htype = ATH9K_PKT_TYPE_PSPOLL;
990 htype = ATH9K_PKT_TYPE_NORMAL;
995 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
996 struct ath_txq *txq, int len)
998 struct ath_hw *ah = sc->sc_ah;
999 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1000 struct ath_buf *bf_first = bf;
1001 struct ath_tx_info info;
1002 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1004 memset(&info, 0, sizeof(info));
1005 info.is_first = true;
1006 info.is_last = true;
1007 info.txpower = MAX_RATE_POWER;
1008 info.qcu = txq->axq_qnum;
1010 info.flags = ATH9K_TXDESC_INTREQ;
1011 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1012 info.flags |= ATH9K_TXDESC_NOACK;
1013 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1014 info.flags |= ATH9K_TXDESC_LDPC;
1016 ath_buf_set_rate(sc, bf, &info, len);
1018 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1019 info.flags |= ATH9K_TXDESC_CLRDMASK;
1021 if (bf->bf_state.bfs_paprd)
1022 info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
1026 struct sk_buff *skb = bf->bf_mpdu;
1027 struct ath_frame_info *fi = get_frame_info(skb);
1029 info.type = get_hw_packet_type(skb);
1031 info.link = bf->bf_next->bf_daddr;
1035 info.buf_addr[0] = bf->bf_buf_addr;
1036 info.buf_len[0] = skb->len;
1037 info.pkt_len = fi->framelen;
1038 info.keyix = fi->keyix;
1039 info.keytype = fi->keytype;
1043 info.aggr = AGGR_BUF_FIRST;
1044 else if (!bf->bf_next)
1045 info.aggr = AGGR_BUF_LAST;
1047 info.aggr = AGGR_BUF_MIDDLE;
1049 info.ndelim = bf->bf_state.ndelim;
1050 info.aggr_len = len;
1053 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1058 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1059 struct ath_atx_tid *tid)
1062 enum ATH_AGGR_STATUS status;
1063 struct ieee80211_tx_info *tx_info;
1064 struct list_head bf_q;
1068 if (skb_queue_empty(&tid->buf_q))
1071 INIT_LIST_HEAD(&bf_q);
1073 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1076 * no frames picked up to be aggregated;
1077 * block-ack window is not open.
1079 if (list_empty(&bf_q))
1082 bf = list_first_entry(&bf_q, struct ath_buf, list);
1083 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1084 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1086 if (tid->ac->clear_ps_filter) {
1087 tid->ac->clear_ps_filter = false;
1088 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1090 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1093 /* if only one frame, send as non-aggregate */
1094 if (bf == bf->bf_lastbf) {
1095 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1096 bf->bf_state.bf_type = BUF_AMPDU;
1098 TX_STAT_INC(txq->axq_qnum, a_aggr);
1101 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1102 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1103 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1104 status != ATH_AGGR_BAW_CLOSED);
1107 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1110 struct ath_atx_tid *txtid;
1111 struct ath_node *an;
1113 an = (struct ath_node *)sta->drv_priv;
1114 txtid = ATH_AN_2_TID(an, tid);
1116 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
1119 txtid->state |= AGGR_ADDBA_PROGRESS;
1120 txtid->paused = true;
1121 *ssn = txtid->seq_start = txtid->seq_next;
1123 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1124 txtid->baw_head = txtid->baw_tail = 0;
1129 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1131 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1132 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1133 struct ath_txq *txq = txtid->ac->txq;
1135 if (txtid->state & AGGR_CLEANUP)
1138 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
1139 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1143 spin_lock_bh(&txq->axq_lock);
1144 txtid->paused = true;
1147 * If frames are still being transmitted for this TID, they will be
1148 * cleaned up during tx completion. To prevent race conditions, this
1149 * TID can only be reused after all in-progress subframes have been
1152 if (txtid->baw_head != txtid->baw_tail)
1153 txtid->state |= AGGR_CLEANUP;
1155 txtid->state &= ~AGGR_ADDBA_COMPLETE;
1156 spin_unlock_bh(&txq->axq_lock);
1158 ath_tx_flush_tid(sc, txtid);
1161 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1162 struct ath_node *an)
1164 struct ath_atx_tid *tid;
1165 struct ath_atx_ac *ac;
1166 struct ath_txq *txq;
1170 for (tidno = 0, tid = &an->tid[tidno];
1171 tidno < WME_NUM_TID; tidno++, tid++) {
1179 spin_lock_bh(&txq->axq_lock);
1181 buffered = !skb_queue_empty(&tid->buf_q);
1184 list_del(&tid->list);
1188 list_del(&ac->list);
1191 spin_unlock_bh(&txq->axq_lock);
1193 ieee80211_sta_set_buffered(sta, tidno, buffered);
1197 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1199 struct ath_atx_tid *tid;
1200 struct ath_atx_ac *ac;
1201 struct ath_txq *txq;
1204 for (tidno = 0, tid = &an->tid[tidno];
1205 tidno < WME_NUM_TID; tidno++, tid++) {
1210 spin_lock_bh(&txq->axq_lock);
1211 ac->clear_ps_filter = true;
1213 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1214 ath_tx_queue_tid(txq, tid);
1215 ath_txq_schedule(sc, txq);
1218 spin_unlock_bh(&txq->axq_lock);
1222 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1224 struct ath_atx_tid *txtid;
1225 struct ath_node *an;
1227 an = (struct ath_node *)sta->drv_priv;
1229 if (sc->sc_flags & SC_OP_TXAGGR) {
1230 txtid = ATH_AN_2_TID(an, tid);
1232 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1233 txtid->state |= AGGR_ADDBA_COMPLETE;
1234 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1235 ath_tx_resume_tid(sc, txtid);
1239 /********************/
1240 /* Queue Management */
1241 /********************/
1243 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1244 struct ath_txq *txq)
1246 struct ath_atx_ac *ac, *ac_tmp;
1247 struct ath_atx_tid *tid, *tid_tmp;
1249 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1250 list_del(&ac->list);
1252 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1253 list_del(&tid->list);
1255 ath_tid_drain(sc, txq, tid);
1260 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1262 struct ath_hw *ah = sc->sc_ah;
1263 struct ath9k_tx_queue_info qi;
1264 static const int subtype_txq_to_hwq[] = {
1265 [WME_AC_BE] = ATH_TXQ_AC_BE,
1266 [WME_AC_BK] = ATH_TXQ_AC_BK,
1267 [WME_AC_VI] = ATH_TXQ_AC_VI,
1268 [WME_AC_VO] = ATH_TXQ_AC_VO,
1272 memset(&qi, 0, sizeof(qi));
1273 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1274 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1275 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1276 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1277 qi.tqi_physCompBuf = 0;
1280 * Enable interrupts only for EOL and DESC conditions.
1281 * We mark tx descriptors to receive a DESC interrupt
1282 * when a tx queue gets deep; otherwise waiting for the
1283 * EOL to reap descriptors. Note that this is done to
1284 * reduce interrupt load and this only defers reaping
1285 * descriptors, never transmitting frames. Aside from
1286 * reducing interrupts this also permits more concurrency.
1287 * The only potential downside is if the tx queue backs
1288 * up in which case the top half of the kernel may backup
1289 * due to a lack of tx descriptors.
1291 * The UAPSD queue is an exception, since we take a desc-
1292 * based intr on the EOSP frames.
1294 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1295 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1296 TXQ_FLAG_TXERRINT_ENABLE;
1298 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1299 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1301 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1302 TXQ_FLAG_TXDESCINT_ENABLE;
1304 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1305 if (axq_qnum == -1) {
1307 * NB: don't print a message, this happens
1308 * normally on parts with too few tx queues
1312 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1313 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1315 txq->axq_qnum = axq_qnum;
1316 txq->mac80211_qnum = -1;
1317 txq->axq_link = NULL;
1318 INIT_LIST_HEAD(&txq->axq_q);
1319 INIT_LIST_HEAD(&txq->axq_acq);
1320 spin_lock_init(&txq->axq_lock);
1322 txq->axq_ampdu_depth = 0;
1323 txq->axq_tx_inprogress = false;
1324 sc->tx.txqsetup |= 1<<axq_qnum;
1326 txq->txq_headidx = txq->txq_tailidx = 0;
1327 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1328 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1330 return &sc->tx.txq[axq_qnum];
1333 int ath_txq_update(struct ath_softc *sc, int qnum,
1334 struct ath9k_tx_queue_info *qinfo)
1336 struct ath_hw *ah = sc->sc_ah;
1338 struct ath9k_tx_queue_info qi;
1340 if (qnum == sc->beacon.beaconq) {
1342 * XXX: for beacon queue, we just save the parameter.
1343 * It will be picked up by ath_beaconq_config when
1346 sc->beacon.beacon_qi = *qinfo;
1350 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1352 ath9k_hw_get_txq_props(ah, qnum, &qi);
1353 qi.tqi_aifs = qinfo->tqi_aifs;
1354 qi.tqi_cwmin = qinfo->tqi_cwmin;
1355 qi.tqi_cwmax = qinfo->tqi_cwmax;
1356 qi.tqi_burstTime = qinfo->tqi_burstTime;
1357 qi.tqi_readyTime = qinfo->tqi_readyTime;
1359 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1360 ath_err(ath9k_hw_common(sc->sc_ah),
1361 "Unable to update hardware queue %u!\n", qnum);
1364 ath9k_hw_resettxqueue(ah, qnum);
1370 int ath_cabq_update(struct ath_softc *sc)
1372 struct ath9k_tx_queue_info qi;
1373 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1374 int qnum = sc->beacon.cabq->axq_qnum;
1376 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1378 * Ensure the readytime % is within the bounds.
1380 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1381 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1382 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1383 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1385 qi.tqi_readyTime = (cur_conf->beacon_interval *
1386 sc->config.cabqReadytime) / 100;
1387 ath_txq_update(sc, qnum, &qi);
1392 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1394 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1395 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1398 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1399 struct list_head *list, bool retry_tx)
1400 __releases(txq->axq_lock)
1401 __acquires(txq->axq_lock)
1403 struct ath_buf *bf, *lastbf;
1404 struct list_head bf_head;
1405 struct ath_tx_status ts;
1407 memset(&ts, 0, sizeof(ts));
1408 ts.ts_status = ATH9K_TX_FLUSH;
1409 INIT_LIST_HEAD(&bf_head);
1411 while (!list_empty(list)) {
1412 bf = list_first_entry(list, struct ath_buf, list);
1415 list_del(&bf->list);
1417 ath_tx_return_buffer(sc, bf);
1421 lastbf = bf->bf_lastbf;
1422 list_cut_position(&bf_head, list, &lastbf->list);
1425 if (bf_is_ampdu_not_probing(bf))
1426 txq->axq_ampdu_depth--;
1428 spin_unlock_bh(&txq->axq_lock);
1430 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1433 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1434 spin_lock_bh(&txq->axq_lock);
1439 * Drain a given TX queue (could be Beacon or Data)
1441 * This assumes output has been stopped and
1442 * we do not need to block ath_tx_tasklet.
1444 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1446 spin_lock_bh(&txq->axq_lock);
1447 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1448 int idx = txq->txq_tailidx;
1450 while (!list_empty(&txq->txq_fifo[idx])) {
1451 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1454 INCR(idx, ATH_TXFIFO_DEPTH);
1456 txq->txq_tailidx = idx;
1459 txq->axq_link = NULL;
1460 txq->axq_tx_inprogress = false;
1461 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1463 /* flush any pending frames if aggregation is enabled */
1464 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1465 ath_txq_drain_pending_buffers(sc, txq);
1467 spin_unlock_bh(&txq->axq_lock);
1470 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1472 struct ath_hw *ah = sc->sc_ah;
1473 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1474 struct ath_txq *txq;
1478 if (sc->sc_flags & SC_OP_INVALID)
1481 ath9k_hw_abort_tx_dma(ah);
1483 /* Check if any queue remains active */
1484 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1485 if (!ATH_TXQ_SETUP(sc, i))
1488 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1493 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1495 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1496 if (!ATH_TXQ_SETUP(sc, i))
1500 * The caller will resume queues with ieee80211_wake_queues.
1501 * Mark the queue as not stopped to prevent ath_tx_complete
1502 * from waking the queue too early.
1504 txq = &sc->tx.txq[i];
1505 txq->stopped = false;
1506 ath_draintxq(sc, txq, retry_tx);
1512 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1514 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1515 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1518 /* For each axq_acq entry, for each tid, try to schedule packets
1519 * for transmit until ampdu_depth has reached min Q depth.
1521 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1523 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1524 struct ath_atx_tid *tid, *last_tid;
1526 if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) ||
1527 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1530 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1531 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1533 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1534 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1535 list_del(&ac->list);
1538 while (!list_empty(&ac->tid_q)) {
1539 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1541 list_del(&tid->list);
1547 ath_tx_sched_aggr(sc, txq, tid);
1550 * add tid to round-robin queue if more frames
1551 * are pending for the tid
1553 if (!skb_queue_empty(&tid->buf_q))
1554 ath_tx_queue_tid(txq, tid);
1556 if (tid == last_tid ||
1557 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1561 if (!list_empty(&ac->tid_q)) {
1564 list_add_tail(&ac->list, &txq->axq_acq);
1568 if (ac == last_ac ||
1569 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1579 * Insert a chain of ath_buf (descriptors) on a txq and
1580 * assume the descriptors are already chained together by caller.
1582 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1583 struct list_head *head, bool internal)
1585 struct ath_hw *ah = sc->sc_ah;
1586 struct ath_common *common = ath9k_hw_common(ah);
1587 struct ath_buf *bf, *bf_last;
1588 bool puttxbuf = false;
1592 * Insert the frame on the outbound list and
1593 * pass it on to the hardware.
1596 if (list_empty(head))
1599 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1600 bf = list_first_entry(head, struct ath_buf, list);
1601 bf_last = list_entry(head->prev, struct ath_buf, list);
1603 ath_dbg(common, ATH_DBG_QUEUE,
1604 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1606 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1607 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1608 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1611 list_splice_tail_init(head, &txq->axq_q);
1613 if (txq->axq_link) {
1614 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1615 ath_dbg(common, ATH_DBG_XMIT,
1616 "link[%u] (%p)=%llx (%p)\n",
1617 txq->axq_qnum, txq->axq_link,
1618 ito64(bf->bf_daddr), bf->bf_desc);
1622 txq->axq_link = bf_last->bf_desc;
1626 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1627 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1628 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1629 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1633 TX_STAT_INC(txq->axq_qnum, txstart);
1634 ath9k_hw_txstart(ah, txq->axq_qnum);
1639 if (bf_is_ampdu_not_probing(bf))
1640 txq->axq_ampdu_depth++;
1644 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1645 struct sk_buff *skb, struct ath_tx_control *txctl)
1647 struct ath_frame_info *fi = get_frame_info(skb);
1648 struct list_head bf_head;
1652 * Do not queue to h/w when any of the following conditions is true:
1653 * - there are pending frames in software queue
1654 * - the TID is currently paused for ADDBA/BAR request
1655 * - seqno is not within block-ack window
1656 * - h/w queue depth exceeds low water mark
1658 if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1659 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1660 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1662 * Add this frame to software queue for scheduling later
1665 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1666 __skb_queue_tail(&tid->buf_q, skb);
1667 if (!txctl->an || !txctl->an->sleeping)
1668 ath_tx_queue_tid(txctl->txq, tid);
1672 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1676 bf->bf_state.bf_type = BUF_AMPDU;
1677 INIT_LIST_HEAD(&bf_head);
1678 list_add(&bf->list, &bf_head);
1680 /* Add sub-frame to BAW */
1681 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1683 /* Queue to h/w without aggregation */
1684 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1686 ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
1687 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1690 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1691 struct ath_atx_tid *tid, struct sk_buff *skb)
1693 struct ath_frame_info *fi = get_frame_info(skb);
1694 struct list_head bf_head;
1699 bf = ath_tx_setup_buffer(sc, txq, tid, skb);
1704 INIT_LIST_HEAD(&bf_head);
1705 list_add_tail(&bf->list, &bf_head);
1706 bf->bf_state.bf_type = 0;
1708 /* update starting sequence number for subsequent ADDBA request */
1710 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1713 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1714 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1715 TX_STAT_INC(txq->axq_qnum, queued);
1718 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1721 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1722 struct ieee80211_sta *sta = tx_info->control.sta;
1723 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1724 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1725 struct ath_frame_info *fi = get_frame_info(skb);
1726 struct ath_node *an = NULL;
1727 enum ath9k_key_type keytype;
1729 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1732 an = (struct ath_node *) sta->drv_priv;
1734 memset(fi, 0, sizeof(*fi));
1736 fi->keyix = hw_key->hw_key_idx;
1737 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1738 fi->keyix = an->ps_key;
1740 fi->keyix = ATH9K_TXKEYIX_INVALID;
1741 fi->keytype = keytype;
1742 fi->framelen = framelen;
1745 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1747 struct ath_hw *ah = sc->sc_ah;
1748 struct ath9k_channel *curchan = ah->curchan;
1749 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1750 (curchan->channelFlags & CHANNEL_5GHZ) &&
1751 (chainmask == 0x7) && (rate < 0x90))
1758 * Assign a descriptor (and sequence number if necessary,
1759 * and map buffer for DMA. Frees skb on error
1761 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1762 struct ath_txq *txq,
1763 struct ath_atx_tid *tid,
1764 struct sk_buff *skb)
1766 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1767 struct ath_frame_info *fi = get_frame_info(skb);
1768 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1772 bf = ath_tx_get_buffer(sc);
1774 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1778 ATH_TXBUF_RESET(bf);
1781 seqno = tid->seq_next;
1782 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1783 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1784 bf->bf_state.seqno = seqno;
1789 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1790 skb->len, DMA_TO_DEVICE);
1791 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1793 bf->bf_buf_addr = 0;
1794 ath_err(ath9k_hw_common(sc->sc_ah),
1795 "dma_mapping_error() on TX\n");
1796 ath_tx_return_buffer(sc, bf);
1805 dev_kfree_skb_any(skb);
1809 /* FIXME: tx power */
1810 static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
1811 struct ath_tx_control *txctl)
1813 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1814 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1815 struct ath_atx_tid *tid = NULL;
1819 spin_lock_bh(&txctl->txq->axq_lock);
1820 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1821 ieee80211_is_data_qos(hdr->frame_control)) {
1822 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1823 IEEE80211_QOS_CTL_TID_MASK;
1824 tid = ATH_AN_2_TID(txctl->an, tidno);
1826 WARN_ON(tid->ac->txq != txctl->txq);
1829 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1831 * Try aggregation if it's a unicast data frame
1832 * and the destination is HT capable.
1834 ath_tx_send_ampdu(sc, tid, skb, txctl);
1836 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb);
1840 bf->bf_state.bfs_paprd = txctl->paprd;
1843 bf->bf_state.bfs_paprd_timestamp = jiffies;
1845 ath_tx_send_normal(sc, txctl->txq, tid, skb);
1849 spin_unlock_bh(&txctl->txq->axq_lock);
1852 /* Upon failure caller should free skb */
1853 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1854 struct ath_tx_control *txctl)
1856 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1857 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1858 struct ieee80211_sta *sta = info->control.sta;
1859 struct ieee80211_vif *vif = info->control.vif;
1860 struct ath_softc *sc = hw->priv;
1861 struct ath_txq *txq = txctl->txq;
1862 int padpos, padsize;
1863 int frmlen = skb->len + FCS_LEN;
1866 /* NOTE: sta can be NULL according to net/mac80211.h */
1868 txctl->an = (struct ath_node *)sta->drv_priv;
1870 if (info->control.hw_key)
1871 frmlen += info->control.hw_key->icv_len;
1874 * As a temporary workaround, assign seq# here; this will likely need
1875 * to be cleaned up to work better with Beacon transmission and virtual
1878 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1879 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1880 sc->tx.seq_no += 0x10;
1881 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1882 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1885 /* Add the padding after the header if this is not already done */
1886 padpos = ath9k_cmn_padpos(hdr->frame_control);
1887 padsize = padpos & 3;
1888 if (padsize && skb->len > padpos) {
1889 if (skb_headroom(skb) < padsize)
1892 skb_push(skb, padsize);
1893 memmove(skb->data, skb->data + padsize, padpos);
1894 hdr = (struct ieee80211_hdr *) skb->data;
1897 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1898 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1899 !ieee80211_is_data(hdr->frame_control))
1900 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1902 setup_frame_info(hw, skb, frmlen);
1905 * At this point, the vif, hw_key and sta pointers in the tx control
1906 * info are no longer valid (overwritten by the ath_frame_info data.
1909 q = skb_get_queue_mapping(skb);
1910 spin_lock_bh(&txq->axq_lock);
1911 if (txq == sc->tx.txq_map[q] &&
1912 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1913 ieee80211_stop_queue(sc->hw, q);
1916 spin_unlock_bh(&txq->axq_lock);
1918 ath_tx_start_dma(sc, skb, txctl);
1926 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1927 int tx_flags, struct ath_txq *txq)
1929 struct ieee80211_hw *hw = sc->hw;
1930 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1931 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1932 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1933 int q, padpos, padsize;
1935 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1937 if (tx_flags & ATH_TX_BAR)
1938 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1940 if (!(tx_flags & ATH_TX_ERROR))
1941 /* Frame was ACKed */
1942 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1944 padpos = ath9k_cmn_padpos(hdr->frame_control);
1945 padsize = padpos & 3;
1946 if (padsize && skb->len>padpos+padsize) {
1948 * Remove MAC header padding before giving the frame back to
1951 memmove(skb->data + padsize, skb->data, padpos);
1952 skb_pull(skb, padsize);
1955 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1956 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1957 ath_dbg(common, ATH_DBG_PS,
1958 "Going back to sleep after having received TX status (0x%lx)\n",
1959 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1961 PS_WAIT_FOR_PSPOLL_DATA |
1962 PS_WAIT_FOR_TX_ACK));
1965 q = skb_get_queue_mapping(skb);
1966 if (txq == sc->tx.txq_map[q]) {
1967 spin_lock_bh(&txq->axq_lock);
1968 if (WARN_ON(--txq->pending_frames < 0))
1969 txq->pending_frames = 0;
1971 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1972 ieee80211_wake_queue(sc->hw, q);
1975 spin_unlock_bh(&txq->axq_lock);
1978 ieee80211_tx_status(hw, skb);
1981 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1982 struct ath_txq *txq, struct list_head *bf_q,
1983 struct ath_tx_status *ts, int txok, int sendbar)
1985 struct sk_buff *skb = bf->bf_mpdu;
1986 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1987 unsigned long flags;
1991 tx_flags = ATH_TX_BAR;
1994 tx_flags |= ATH_TX_ERROR;
1996 if (ts->ts_status & ATH9K_TXERR_FILT)
1997 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1999 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2000 bf->bf_buf_addr = 0;
2002 if (bf->bf_state.bfs_paprd) {
2003 if (time_after(jiffies,
2004 bf->bf_state.bfs_paprd_timestamp +
2005 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2006 dev_kfree_skb_any(skb);
2008 complete(&sc->paprd_complete);
2010 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2011 ath_tx_complete(sc, skb, tx_flags, txq);
2013 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2014 * accidentally reference it later.
2019 * Return the list of ath_buf of this mpdu to free queue
2021 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2022 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2023 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2026 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2027 struct ath_tx_status *ts, int nframes, int nbad,
2030 struct sk_buff *skb = bf->bf_mpdu;
2031 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2032 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2033 struct ieee80211_hw *hw = sc->hw;
2034 struct ath_hw *ah = sc->sc_ah;
2038 tx_info->status.ack_signal = ts->ts_rssi;
2040 tx_rateindex = ts->ts_rateindex;
2041 WARN_ON(tx_rateindex >= hw->max_rates);
2043 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2044 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2046 BUG_ON(nbad > nframes);
2048 tx_info->status.ampdu_len = nframes;
2049 tx_info->status.ampdu_ack_len = nframes - nbad;
2051 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2052 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2054 * If an underrun error is seen assume it as an excessive
2055 * retry only if max frame trigger level has been reached
2056 * (2 KB for single stream, and 4 KB for dual stream).
2057 * Adjust the long retry as if the frame was tried
2058 * hw->max_rate_tries times to affect how rate control updates
2059 * PER for the failed rate.
2060 * In case of congestion on the bus penalizing this type of
2061 * underruns should help hardware actually transmit new frames
2062 * successfully by eventually preferring slower rates.
2063 * This itself should also alleviate congestion on the bus.
2065 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2066 ATH9K_TX_DELIM_UNDERRUN)) &&
2067 ieee80211_is_data(hdr->frame_control) &&
2068 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2069 tx_info->status.rates[tx_rateindex].count =
2073 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2074 tx_info->status.rates[i].count = 0;
2075 tx_info->status.rates[i].idx = -1;
2078 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2081 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2082 struct ath_tx_status *ts, struct ath_buf *bf,
2083 struct list_head *bf_head)
2084 __releases(txq->axq_lock)
2085 __acquires(txq->axq_lock)
2090 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2091 txq->axq_tx_inprogress = false;
2092 if (bf_is_ampdu_not_probing(bf))
2093 txq->axq_ampdu_depth--;
2095 spin_unlock_bh(&txq->axq_lock);
2097 if (!bf_isampdu(bf)) {
2098 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
2099 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2101 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2103 spin_lock_bh(&txq->axq_lock);
2105 if (sc->sc_flags & SC_OP_TXAGGR)
2106 ath_txq_schedule(sc, txq);
2109 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2111 struct ath_hw *ah = sc->sc_ah;
2112 struct ath_common *common = ath9k_hw_common(ah);
2113 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2114 struct list_head bf_head;
2115 struct ath_desc *ds;
2116 struct ath_tx_status ts;
2119 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2120 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2123 spin_lock_bh(&txq->axq_lock);
2125 if (work_pending(&sc->hw_reset_work))
2128 if (list_empty(&txq->axq_q)) {
2129 txq->axq_link = NULL;
2130 if (sc->sc_flags & SC_OP_TXAGGR)
2131 ath_txq_schedule(sc, txq);
2134 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2137 * There is a race condition that a BH gets scheduled
2138 * after sw writes TxE and before hw re-load the last
2139 * descriptor to get the newly chained one.
2140 * Software must keep the last DONE descriptor as a
2141 * holding descriptor - software does so by marking
2142 * it with the STALE flag.
2147 if (list_is_last(&bf_held->list, &txq->axq_q))
2150 bf = list_entry(bf_held->list.next, struct ath_buf,
2154 lastbf = bf->bf_lastbf;
2155 ds = lastbf->bf_desc;
2157 memset(&ts, 0, sizeof(ts));
2158 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2159 if (status == -EINPROGRESS)
2162 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2165 * Remove ath_buf's of the same transmit unit from txq,
2166 * however leave the last descriptor back as the holding
2167 * descriptor for hw.
2169 lastbf->bf_stale = true;
2170 INIT_LIST_HEAD(&bf_head);
2171 if (!list_is_singular(&lastbf->list))
2172 list_cut_position(&bf_head,
2173 &txq->axq_q, lastbf->list.prev);
2176 list_del(&bf_held->list);
2177 ath_tx_return_buffer(sc, bf_held);
2180 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2182 spin_unlock_bh(&txq->axq_lock);
2185 static void ath_tx_complete_poll_work(struct work_struct *work)
2187 struct ath_softc *sc = container_of(work, struct ath_softc,
2188 tx_complete_work.work);
2189 struct ath_txq *txq;
2191 bool needreset = false;
2192 #ifdef CONFIG_ATH9K_DEBUGFS
2193 sc->tx_complete_poll_work_seen++;
2196 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2197 if (ATH_TXQ_SETUP(sc, i)) {
2198 txq = &sc->tx.txq[i];
2199 spin_lock_bh(&txq->axq_lock);
2200 if (txq->axq_depth) {
2201 if (txq->axq_tx_inprogress) {
2203 spin_unlock_bh(&txq->axq_lock);
2206 txq->axq_tx_inprogress = true;
2209 spin_unlock_bh(&txq->axq_lock);
2213 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2214 "tx hung, resetting the chip\n");
2215 RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
2216 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2219 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2220 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2225 void ath_tx_tasklet(struct ath_softc *sc)
2228 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2230 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2232 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2233 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2234 ath_tx_processq(sc, &sc->tx.txq[i]);
2238 void ath_tx_edma_tasklet(struct ath_softc *sc)
2240 struct ath_tx_status ts;
2241 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2242 struct ath_hw *ah = sc->sc_ah;
2243 struct ath_txq *txq;
2244 struct ath_buf *bf, *lastbf;
2245 struct list_head bf_head;
2249 if (work_pending(&sc->hw_reset_work))
2252 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2253 if (status == -EINPROGRESS)
2255 if (status == -EIO) {
2256 ath_dbg(common, ATH_DBG_XMIT,
2257 "Error processing tx status\n");
2261 /* Skip beacon completions */
2262 if (ts.qid == sc->beacon.beaconq)
2265 txq = &sc->tx.txq[ts.qid];
2267 spin_lock_bh(&txq->axq_lock);
2269 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2270 spin_unlock_bh(&txq->axq_lock);
2274 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2275 struct ath_buf, list);
2276 lastbf = bf->bf_lastbf;
2278 INIT_LIST_HEAD(&bf_head);
2279 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2282 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2283 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2285 if (!list_empty(&txq->axq_q)) {
2286 struct list_head bf_q;
2288 INIT_LIST_HEAD(&bf_q);
2289 txq->axq_link = NULL;
2290 list_splice_tail_init(&txq->axq_q, &bf_q);
2291 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2295 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2296 spin_unlock_bh(&txq->axq_lock);
2304 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2306 struct ath_descdma *dd = &sc->txsdma;
2307 u8 txs_len = sc->sc_ah->caps.txs_len;
2309 dd->dd_desc_len = size * txs_len;
2310 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2311 &dd->dd_desc_paddr, GFP_KERNEL);
2318 static int ath_tx_edma_init(struct ath_softc *sc)
2322 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2324 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2325 sc->txsdma.dd_desc_paddr,
2326 ATH_TXSTATUS_RING_SIZE);
2331 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2333 struct ath_descdma *dd = &sc->txsdma;
2335 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2339 int ath_tx_init(struct ath_softc *sc, int nbufs)
2341 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2344 spin_lock_init(&sc->tx.txbuflock);
2346 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2350 "Failed to allocate tx descriptors: %d\n", error);
2354 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2355 "beacon", ATH_BCBUF, 1, 1);
2358 "Failed to allocate beacon descriptors: %d\n", error);
2362 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2364 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2365 error = ath_tx_edma_init(sc);
2377 void ath_tx_cleanup(struct ath_softc *sc)
2379 if (sc->beacon.bdma.dd_desc_len != 0)
2380 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2382 if (sc->tx.txdma.dd_desc_len != 0)
2383 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2385 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2386 ath_tx_edma_cleanup(sc);
2389 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2391 struct ath_atx_tid *tid;
2392 struct ath_atx_ac *ac;
2395 for (tidno = 0, tid = &an->tid[tidno];
2396 tidno < WME_NUM_TID;
2400 tid->seq_start = tid->seq_next = 0;
2401 tid->baw_size = WME_MAX_BA;
2402 tid->baw_head = tid->baw_tail = 0;
2404 tid->paused = false;
2405 tid->state &= ~AGGR_CLEANUP;
2406 __skb_queue_head_init(&tid->buf_q);
2407 acno = TID_TO_WME_AC(tidno);
2408 tid->ac = &an->ac[acno];
2409 tid->state &= ~AGGR_ADDBA_COMPLETE;
2410 tid->state &= ~AGGR_ADDBA_PROGRESS;
2413 for (acno = 0, ac = &an->ac[acno];
2414 acno < WME_NUM_AC; acno++, ac++) {
2416 ac->txq = sc->tx.txq_map[acno];
2417 INIT_LIST_HEAD(&ac->tid_q);
2421 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2423 struct ath_atx_ac *ac;
2424 struct ath_atx_tid *tid;
2425 struct ath_txq *txq;
2428 for (tidno = 0, tid = &an->tid[tidno];
2429 tidno < WME_NUM_TID; tidno++, tid++) {
2434 spin_lock_bh(&txq->axq_lock);
2437 list_del(&tid->list);
2442 list_del(&ac->list);
2443 tid->ac->sched = false;
2446 ath_tid_drain(sc, txq, tid);
2447 tid->state &= ~AGGR_ADDBA_COMPLETE;
2448 tid->state &= ~AGGR_CLEANUP;
2450 spin_unlock_bh(&txq->axq_lock);