2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 static u16 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid, struct sk_buff *skb);
52 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
53 int tx_flags, struct ath_txq *txq);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head, bool internal);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
64 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
66 struct ath_atx_tid *tid,
77 static int ath_max_4ms_framelen[4][32] = {
79 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
80 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
81 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
82 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
85 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
86 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
87 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
88 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
91 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
92 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
93 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
94 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
97 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
98 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
99 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
100 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
104 /*********************/
105 /* Aggregation logic */
106 /*********************/
108 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
110 struct ath_atx_ac *ac = tid->ac;
119 list_add_tail(&tid->list, &ac->tid_q);
125 list_add_tail(&ac->list, &txq->axq_acq);
128 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
130 struct ath_txq *txq = tid->ac->txq;
132 WARN_ON(!tid->paused);
134 spin_lock_bh(&txq->axq_lock);
137 if (skb_queue_empty(&tid->buf_q))
140 ath_tx_queue_tid(txq, tid);
141 ath_txq_schedule(sc, txq);
143 spin_unlock_bh(&txq->axq_lock);
146 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
148 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
149 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
150 sizeof(tx_info->rate_driver_data));
151 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
154 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
156 struct ath_txq *txq = tid->ac->txq;
159 struct list_head bf_head;
160 struct ath_tx_status ts;
161 struct ath_frame_info *fi;
163 INIT_LIST_HEAD(&bf_head);
165 memset(&ts, 0, sizeof(ts));
166 spin_lock_bh(&txq->axq_lock);
168 while ((skb = __skb_dequeue(&tid->buf_q))) {
169 fi = get_frame_info(skb);
172 spin_unlock_bh(&txq->axq_lock);
173 if (bf && fi->retries) {
174 list_add_tail(&bf->list, &bf_head);
175 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
176 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
178 ath_tx_send_normal(sc, txq, NULL, skb);
180 spin_lock_bh(&txq->axq_lock);
183 spin_unlock_bh(&txq->axq_lock);
186 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
191 index = ATH_BA_INDEX(tid->seq_start, seqno);
192 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
194 __clear_bit(cindex, tid->tx_buf);
196 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
197 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
198 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
202 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
207 index = ATH_BA_INDEX(tid->seq_start, seqno);
208 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
209 __set_bit(cindex, tid->tx_buf);
211 if (index >= ((tid->baw_tail - tid->baw_head) &
212 (ATH_TID_MAX_BUFS - 1))) {
213 tid->baw_tail = cindex;
214 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
219 * TODO: For frame(s) that are in the retry state, we will reuse the
220 * sequence number(s) without setting the retry bit. The
221 * alternative is to give up on these and BAR the receiver's window
224 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
225 struct ath_atx_tid *tid)
230 struct list_head bf_head;
231 struct ath_tx_status ts;
232 struct ath_frame_info *fi;
234 memset(&ts, 0, sizeof(ts));
235 INIT_LIST_HEAD(&bf_head);
237 while ((skb = __skb_dequeue(&tid->buf_q))) {
238 fi = get_frame_info(skb);
242 spin_unlock(&txq->axq_lock);
243 ath_tx_complete(sc, skb, ATH_TX_ERROR, txq);
244 spin_lock(&txq->axq_lock);
248 list_add_tail(&bf->list, &bf_head);
251 ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
253 spin_unlock(&txq->axq_lock);
254 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
255 spin_lock(&txq->axq_lock);
258 tid->seq_next = tid->seq_start;
259 tid->baw_tail = tid->baw_head;
262 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
265 struct ath_frame_info *fi = get_frame_info(skb);
266 struct ath_buf *bf = fi->bf;
267 struct ieee80211_hdr *hdr;
269 TX_STAT_INC(txq->axq_qnum, a_retries);
270 if (fi->retries++ > 0)
273 hdr = (struct ieee80211_hdr *)skb->data;
274 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
275 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
276 sizeof(*hdr), DMA_TO_DEVICE);
279 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
281 struct ath_buf *bf = NULL;
283 spin_lock_bh(&sc->tx.txbuflock);
285 if (unlikely(list_empty(&sc->tx.txbuf))) {
286 spin_unlock_bh(&sc->tx.txbuflock);
290 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
293 spin_unlock_bh(&sc->tx.txbuflock);
298 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
300 spin_lock_bh(&sc->tx.txbuflock);
301 list_add_tail(&bf->list, &sc->tx.txbuf);
302 spin_unlock_bh(&sc->tx.txbuflock);
305 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
309 tbf = ath_tx_get_buffer(sc);
313 ATH_TXBUF_RESET(tbf);
315 tbf->bf_mpdu = bf->bf_mpdu;
316 tbf->bf_buf_addr = bf->bf_buf_addr;
317 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
318 tbf->bf_state = bf->bf_state;
323 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
324 struct ath_tx_status *ts, int txok,
325 int *nframes, int *nbad)
327 struct ath_frame_info *fi;
329 u32 ba[WME_BA_BMP_SIZE >> 5];
336 isaggr = bf_isaggr(bf);
338 seq_st = ts->ts_seqnum;
339 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
343 fi = get_frame_info(bf->bf_mpdu);
344 ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
347 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
355 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
356 struct ath_buf *bf, struct list_head *bf_q,
357 struct ath_tx_status *ts, int txok, bool retry)
359 struct ath_node *an = NULL;
361 struct ieee80211_sta *sta;
362 struct ieee80211_hw *hw = sc->hw;
363 struct ieee80211_hdr *hdr;
364 struct ieee80211_tx_info *tx_info;
365 struct ath_atx_tid *tid = NULL;
366 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
367 struct list_head bf_head;
368 struct sk_buff_head bf_pending;
369 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
370 u32 ba[WME_BA_BMP_SIZE >> 5];
371 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
372 bool rc_update = true;
373 struct ieee80211_tx_rate rates[4];
374 struct ath_frame_info *fi;
377 bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
380 hdr = (struct ieee80211_hdr *)skb->data;
382 tx_info = IEEE80211_SKB_CB(skb);
384 memcpy(rates, tx_info->control.rates, sizeof(rates));
388 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
392 INIT_LIST_HEAD(&bf_head);
394 bf_next = bf->bf_next;
396 if (!bf->bf_stale || bf_next != NULL)
397 list_move_tail(&bf->list, &bf_head);
399 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
407 an = (struct ath_node *)sta->drv_priv;
408 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
409 tid = ATH_AN_2_TID(an, tidno);
412 * The hardware occasionally sends a tx status for the wrong TID.
413 * In this case, the BA status cannot be considered valid and all
414 * subframes need to be retransmitted
416 if (tidno != ts->tid)
419 isaggr = bf_isaggr(bf);
420 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
422 if (isaggr && txok) {
423 if (ts->ts_flags & ATH9K_TX_BA) {
424 seq_st = ts->ts_seqnum;
425 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
428 * AR5416 can become deaf/mute when BA
429 * issue happens. Chip needs to be reset.
430 * But AP code may have sychronization issues
431 * when perform internal reset in this routine.
432 * Only enable reset in STA mode for now.
434 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
439 __skb_queue_head_init(&bf_pending);
441 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
443 u16 seqno = bf->bf_state.seqno;
445 txfail = txpending = sendbar = 0;
446 bf_next = bf->bf_next;
449 tx_info = IEEE80211_SKB_CB(skb);
450 fi = get_frame_info(skb);
452 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
453 /* transmit completion, subframe is
454 * acked by block ack */
456 } else if (!isaggr && txok) {
457 /* transmit completion */
460 if ((tid->state & AGGR_CLEANUP) || !retry) {
462 * cleanup in progress, just fail
463 * the un-acked sub-frames
468 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
469 if (txok || !an->sleeping)
470 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
481 * Make sure the last desc is reclaimed if it
482 * not a holding desc.
484 INIT_LIST_HEAD(&bf_head);
485 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
486 bf_next != NULL || !bf_last->bf_stale)
487 list_move_tail(&bf->list, &bf_head);
489 if (!txpending || (tid->state & AGGR_CLEANUP)) {
491 * complete the acked-ones/xretried ones; update
494 spin_lock_bh(&txq->axq_lock);
495 ath_tx_update_baw(sc, tid, seqno);
496 spin_unlock_bh(&txq->axq_lock);
498 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
499 memcpy(tx_info->control.rates, rates, sizeof(rates));
500 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
504 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
507 /* retry the un-acked ones */
508 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
509 if (bf->bf_next == NULL && bf_last->bf_stale) {
512 tbf = ath_clone_txbuf(sc, bf_last);
514 * Update tx baw and complete the
515 * frame with failed status if we
519 spin_lock_bh(&txq->axq_lock);
520 ath_tx_update_baw(sc, tid, seqno);
521 spin_unlock_bh(&txq->axq_lock);
523 ath_tx_complete_buf(sc, bf, txq,
535 * Put this buffer to the temporary pending
536 * queue to retain ordering
538 __skb_queue_tail(&bf_pending, skb);
544 /* prepend un-acked frames to the beginning of the pending frame queue */
545 if (!skb_queue_empty(&bf_pending)) {
547 ieee80211_sta_set_buffered(sta, tid->tidno, true);
549 spin_lock_bh(&txq->axq_lock);
550 skb_queue_splice(&bf_pending, &tid->buf_q);
552 ath_tx_queue_tid(txq, tid);
554 if (ts->ts_status & ATH9K_TXERR_FILT)
555 tid->ac->clear_ps_filter = true;
557 spin_unlock_bh(&txq->axq_lock);
560 if (tid->state & AGGR_CLEANUP) {
561 ath_tx_flush_tid(sc, tid);
563 if (tid->baw_head == tid->baw_tail) {
564 tid->state &= ~AGGR_ADDBA_COMPLETE;
565 tid->state &= ~AGGR_CLEANUP;
572 RESET_STAT_INC(sc, RESET_TYPE_TX_ERROR);
573 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
577 static bool ath_lookup_legacy(struct ath_buf *bf)
580 struct ieee80211_tx_info *tx_info;
581 struct ieee80211_tx_rate *rates;
585 tx_info = IEEE80211_SKB_CB(skb);
586 rates = tx_info->control.rates;
588 for (i = 0; i < 4; i++) {
589 if (!rates[i].count || rates[i].idx < 0)
592 if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
599 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
600 struct ath_atx_tid *tid)
603 struct ieee80211_tx_info *tx_info;
604 struct ieee80211_tx_rate *rates;
605 u32 max_4ms_framelen, frmlen;
606 u16 aggr_limit, legacy = 0;
610 tx_info = IEEE80211_SKB_CB(skb);
611 rates = tx_info->control.rates;
614 * Find the lowest frame length among the rate series that will have a
615 * 4ms transmit duration.
616 * TODO - TXOP limit needs to be considered.
618 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
620 for (i = 0; i < 4; i++) {
621 if (rates[i].count) {
623 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
628 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
633 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
636 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
637 max_4ms_framelen = min(max_4ms_framelen, frmlen);
642 * limit aggregate size by the minimum rate if rate selected is
643 * not a probe rate, if rate selected is a probe rate then
644 * avoid aggregation of this packet.
646 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
649 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
650 aggr_limit = min((max_4ms_framelen * 3) / 8,
651 (u32)ATH_AMPDU_LIMIT_MAX);
653 aggr_limit = min(max_4ms_framelen,
654 (u32)ATH_AMPDU_LIMIT_MAX);
657 * h/w can accept aggregates up to 16 bit lengths (65535).
658 * The IE, however can hold up to 65536, which shows up here
659 * as zero. Ignore 65536 since we are constrained by hw.
661 if (tid->an->maxampdu)
662 aggr_limit = min(aggr_limit, tid->an->maxampdu);
668 * Returns the number of delimiters to be added to
669 * meet the minimum required mpdudensity.
671 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
672 struct ath_buf *bf, u16 frmlen,
675 #define FIRST_DESC_NDELIMS 60
676 struct sk_buff *skb = bf->bf_mpdu;
677 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
678 u32 nsymbits, nsymbols;
681 int width, streams, half_gi, ndelim, mindelim;
682 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
684 /* Select standard number of delimiters based on frame length alone */
685 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
688 * If encryption enabled, hardware requires some more padding between
690 * TODO - this could be improved to be dependent on the rate.
691 * The hardware can keep up at lower rates, but not higher rates
693 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
694 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
695 ndelim += ATH_AGGR_ENCRYPTDELIM;
698 * Add delimiter when using RTS/CTS with aggregation
699 * and non enterprise AR9003 card
701 if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
702 (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
703 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
706 * Convert desired mpdu density from microeconds to bytes based
707 * on highest rate in rate series (i.e. first rate) to determine
708 * required minimum length for subframe. Take into account
709 * whether high rate is 20 or 40Mhz and half or full GI.
711 * If there is no mpdu density restriction, no further calculation
715 if (tid->an->mpdudensity == 0)
718 rix = tx_info->control.rates[0].idx;
719 flags = tx_info->control.rates[0].flags;
720 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
721 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
724 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
726 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
731 streams = HT_RC_2_STREAMS(rix);
732 nsymbits = bits_per_symbol[rix % 8][width] * streams;
733 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
735 if (frmlen < minlen) {
736 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
737 ndelim = max(mindelim, ndelim);
743 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
745 struct ath_atx_tid *tid,
746 struct list_head *bf_q,
749 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
750 struct ath_buf *bf, *bf_first = NULL, *bf_prev = NULL;
751 int rl = 0, nframes = 0, ndelim, prev_al = 0;
752 u16 aggr_limit = 0, al = 0, bpad = 0,
753 al_delta, h_baw = tid->baw_size / 2;
754 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
755 struct ieee80211_tx_info *tx_info;
756 struct ath_frame_info *fi;
761 skb = skb_peek(&tid->buf_q);
762 fi = get_frame_info(skb);
765 bf = ath_tx_setup_buffer(sc, txq, tid, skb, true);
770 bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
771 seqno = bf->bf_state.seqno;
775 /* do not step over block-ack window */
776 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
777 status = ATH_AGGR_BAW_CLOSED;
782 aggr_limit = ath_lookup_rate(sc, bf, tid);
786 /* do not exceed aggregation limit */
787 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
790 ((aggr_limit < (al + bpad + al_delta + prev_al)) ||
791 ath_lookup_legacy(bf))) {
792 status = ATH_AGGR_LIMITED;
796 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
797 if (nframes && (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE))
800 /* do not exceed subframe limit */
801 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
802 status = ATH_AGGR_LIMITED;
806 /* add padding for previous frame to aggregation length */
807 al += bpad + al_delta;
810 * Get the delimiters needed to meet the MPDU
811 * density for this node.
813 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
815 bpad = PADBYTES(al_delta) + (ndelim << 2);
820 /* link buffers of this frame to the aggregate */
822 ath_tx_addto_baw(sc, tid, seqno);
823 bf->bf_state.ndelim = ndelim;
825 __skb_unlink(skb, &tid->buf_q);
826 list_add_tail(&bf->list, bf_q);
828 bf_prev->bf_next = bf;
832 } while (!skb_queue_empty(&tid->buf_q));
842 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
843 * width - 0 for 20 MHz, 1 for 40 MHz
844 * half_gi - to use 4us v/s 3.6 us for symbol time
846 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
847 int width, int half_gi, bool shortPreamble)
849 u32 nbits, nsymbits, duration, nsymbols;
852 /* find number of symbols: PLCP + data */
853 streams = HT_RC_2_STREAMS(rix);
854 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
855 nsymbits = bits_per_symbol[rix % 8][width] * streams;
856 nsymbols = (nbits + nsymbits - 1) / nsymbits;
859 duration = SYMBOL_TIME(nsymbols);
861 duration = SYMBOL_TIME_HALFGI(nsymbols);
863 /* addup duration for legacy/ht training and signal fields */
864 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
869 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
870 struct ath_tx_info *info, int len)
872 struct ath_hw *ah = sc->sc_ah;
874 struct ieee80211_tx_info *tx_info;
875 struct ieee80211_tx_rate *rates;
876 const struct ieee80211_rate *rate;
877 struct ieee80211_hdr *hdr;
882 tx_info = IEEE80211_SKB_CB(skb);
883 rates = tx_info->control.rates;
884 hdr = (struct ieee80211_hdr *)skb->data;
886 /* set dur_update_en for l-sig computation except for PS-Poll frames */
887 info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
890 * We check if Short Preamble is needed for the CTS rate by
891 * checking the BSS's global flag.
892 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
894 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
895 info->rtscts_rate = rate->hw_value;
896 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
897 info->rtscts_rate |= rate->hw_value_short;
899 for (i = 0; i < 4; i++) {
900 bool is_40, is_sgi, is_sp;
903 if (!rates[i].count || (rates[i].idx < 0))
907 info->rates[i].Tries = rates[i].count;
909 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
910 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
911 info->flags |= ATH9K_TXDESC_RTSENA;
912 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
913 info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
914 info->flags |= ATH9K_TXDESC_CTSENA;
917 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
918 info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
919 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
920 info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
922 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
923 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
924 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
926 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
928 info->rates[i].Rate = rix | 0x80;
929 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
930 ah->txchainmask, info->rates[i].Rate);
931 info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
932 is_40, is_sgi, is_sp);
933 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
934 info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
939 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
940 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
941 !(rate->flags & IEEE80211_RATE_ERP_G))
942 phy = WLAN_RC_PHY_CCK;
944 phy = WLAN_RC_PHY_OFDM;
946 info->rates[i].Rate = rate->hw_value;
947 if (rate->hw_value_short) {
948 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
949 info->rates[i].Rate |= rate->hw_value_short;
954 if (bf->bf_state.bfs_paprd)
955 info->rates[i].ChSel = ah->txchainmask;
957 info->rates[i].ChSel = ath_txchainmask_reduction(sc,
958 ah->txchainmask, info->rates[i].Rate);
960 info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
961 phy, rate->bitrate * 100, len, rix, is_sp);
964 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
965 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
966 info->flags &= ~ATH9K_TXDESC_RTSENA;
968 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
969 if (info->flags & ATH9K_TXDESC_RTSENA)
970 info->flags &= ~ATH9K_TXDESC_CTSENA;
973 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
975 struct ieee80211_hdr *hdr;
976 enum ath9k_pkt_type htype;
979 hdr = (struct ieee80211_hdr *)skb->data;
980 fc = hdr->frame_control;
982 if (ieee80211_is_beacon(fc))
983 htype = ATH9K_PKT_TYPE_BEACON;
984 else if (ieee80211_is_probe_resp(fc))
985 htype = ATH9K_PKT_TYPE_PROBE_RESP;
986 else if (ieee80211_is_atim(fc))
987 htype = ATH9K_PKT_TYPE_ATIM;
988 else if (ieee80211_is_pspoll(fc))
989 htype = ATH9K_PKT_TYPE_PSPOLL;
991 htype = ATH9K_PKT_TYPE_NORMAL;
996 static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
997 struct ath_txq *txq, int len)
999 struct ath_hw *ah = sc->sc_ah;
1000 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1001 struct ath_buf *bf_first = bf;
1002 struct ath_tx_info info;
1003 bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1005 memset(&info, 0, sizeof(info));
1006 info.is_first = true;
1007 info.is_last = true;
1008 info.txpower = MAX_RATE_POWER;
1009 info.qcu = txq->axq_qnum;
1011 info.flags = ATH9K_TXDESC_INTREQ;
1012 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1013 info.flags |= ATH9K_TXDESC_NOACK;
1014 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1015 info.flags |= ATH9K_TXDESC_LDPC;
1017 ath_buf_set_rate(sc, bf, &info, len);
1019 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1020 info.flags |= ATH9K_TXDESC_CLRDMASK;
1022 if (bf->bf_state.bfs_paprd)
1023 info.flags |= (u32) bf->bf_state.bfs_paprd << ATH9K_TXDESC_PAPRD_S;
1027 struct sk_buff *skb = bf->bf_mpdu;
1028 struct ath_frame_info *fi = get_frame_info(skb);
1030 info.type = get_hw_packet_type(skb);
1032 info.link = bf->bf_next->bf_daddr;
1036 info.buf_addr[0] = bf->bf_buf_addr;
1037 info.buf_len[0] = skb->len;
1038 info.pkt_len = fi->framelen;
1039 info.keyix = fi->keyix;
1040 info.keytype = fi->keytype;
1044 info.aggr = AGGR_BUF_FIRST;
1045 else if (!bf->bf_next)
1046 info.aggr = AGGR_BUF_LAST;
1048 info.aggr = AGGR_BUF_MIDDLE;
1050 info.ndelim = bf->bf_state.ndelim;
1051 info.aggr_len = len;
1054 ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1059 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1060 struct ath_atx_tid *tid)
1063 enum ATH_AGGR_STATUS status;
1064 struct ieee80211_tx_info *tx_info;
1065 struct list_head bf_q;
1069 if (skb_queue_empty(&tid->buf_q))
1072 INIT_LIST_HEAD(&bf_q);
1074 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
1077 * no frames picked up to be aggregated;
1078 * block-ack window is not open.
1080 if (list_empty(&bf_q))
1083 bf = list_first_entry(&bf_q, struct ath_buf, list);
1084 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
1085 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1087 if (tid->ac->clear_ps_filter) {
1088 tid->ac->clear_ps_filter = false;
1089 tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1091 tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
1094 /* if only one frame, send as non-aggregate */
1095 if (bf == bf->bf_lastbf) {
1096 aggr_len = get_frame_info(bf->bf_mpdu)->framelen;
1097 bf->bf_state.bf_type = BUF_AMPDU;
1099 TX_STAT_INC(txq->axq_qnum, a_aggr);
1102 ath_tx_fill_desc(sc, bf, txq, aggr_len);
1103 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1104 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
1105 status != ATH_AGGR_BAW_CLOSED);
1108 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1111 struct ath_atx_tid *txtid;
1112 struct ath_node *an;
1114 an = (struct ath_node *)sta->drv_priv;
1115 txtid = ATH_AN_2_TID(an, tid);
1117 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
1120 txtid->state |= AGGR_ADDBA_PROGRESS;
1121 txtid->paused = true;
1122 *ssn = txtid->seq_start = txtid->seq_next;
1124 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1125 txtid->baw_head = txtid->baw_tail = 0;
1130 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1132 struct ath_node *an = (struct ath_node *)sta->drv_priv;
1133 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1134 struct ath_txq *txq = txtid->ac->txq;
1136 if (txtid->state & AGGR_CLEANUP)
1139 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
1140 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1144 spin_lock_bh(&txq->axq_lock);
1145 txtid->paused = true;
1148 * If frames are still being transmitted for this TID, they will be
1149 * cleaned up during tx completion. To prevent race conditions, this
1150 * TID can only be reused after all in-progress subframes have been
1153 if (txtid->baw_head != txtid->baw_tail)
1154 txtid->state |= AGGR_CLEANUP;
1156 txtid->state &= ~AGGR_ADDBA_COMPLETE;
1157 spin_unlock_bh(&txq->axq_lock);
1159 ath_tx_flush_tid(sc, txtid);
1162 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1163 struct ath_node *an)
1165 struct ath_atx_tid *tid;
1166 struct ath_atx_ac *ac;
1167 struct ath_txq *txq;
1171 for (tidno = 0, tid = &an->tid[tidno];
1172 tidno < WME_NUM_TID; tidno++, tid++) {
1180 spin_lock_bh(&txq->axq_lock);
1182 buffered = !skb_queue_empty(&tid->buf_q);
1185 list_del(&tid->list);
1189 list_del(&ac->list);
1192 spin_unlock_bh(&txq->axq_lock);
1194 ieee80211_sta_set_buffered(sta, tidno, buffered);
1198 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1200 struct ath_atx_tid *tid;
1201 struct ath_atx_ac *ac;
1202 struct ath_txq *txq;
1205 for (tidno = 0, tid = &an->tid[tidno];
1206 tidno < WME_NUM_TID; tidno++, tid++) {
1211 spin_lock_bh(&txq->axq_lock);
1212 ac->clear_ps_filter = true;
1214 if (!skb_queue_empty(&tid->buf_q) && !tid->paused) {
1215 ath_tx_queue_tid(txq, tid);
1216 ath_txq_schedule(sc, txq);
1219 spin_unlock_bh(&txq->axq_lock);
1223 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1225 struct ath_atx_tid *txtid;
1226 struct ath_node *an;
1228 an = (struct ath_node *)sta->drv_priv;
1230 if (sc->sc_flags & SC_OP_TXAGGR) {
1231 txtid = ATH_AN_2_TID(an, tid);
1233 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
1234 txtid->state |= AGGR_ADDBA_COMPLETE;
1235 txtid->state &= ~AGGR_ADDBA_PROGRESS;
1236 ath_tx_resume_tid(sc, txtid);
1240 /********************/
1241 /* Queue Management */
1242 /********************/
1244 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1245 struct ath_txq *txq)
1247 struct ath_atx_ac *ac, *ac_tmp;
1248 struct ath_atx_tid *tid, *tid_tmp;
1250 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1251 list_del(&ac->list);
1253 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1254 list_del(&tid->list);
1256 ath_tid_drain(sc, txq, tid);
1261 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1263 struct ath_hw *ah = sc->sc_ah;
1264 struct ath9k_tx_queue_info qi;
1265 static const int subtype_txq_to_hwq[] = {
1266 [WME_AC_BE] = ATH_TXQ_AC_BE,
1267 [WME_AC_BK] = ATH_TXQ_AC_BK,
1268 [WME_AC_VI] = ATH_TXQ_AC_VI,
1269 [WME_AC_VO] = ATH_TXQ_AC_VO,
1273 memset(&qi, 0, sizeof(qi));
1274 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1275 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1276 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1277 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1278 qi.tqi_physCompBuf = 0;
1281 * Enable interrupts only for EOL and DESC conditions.
1282 * We mark tx descriptors to receive a DESC interrupt
1283 * when a tx queue gets deep; otherwise waiting for the
1284 * EOL to reap descriptors. Note that this is done to
1285 * reduce interrupt load and this only defers reaping
1286 * descriptors, never transmitting frames. Aside from
1287 * reducing interrupts this also permits more concurrency.
1288 * The only potential downside is if the tx queue backs
1289 * up in which case the top half of the kernel may backup
1290 * due to a lack of tx descriptors.
1292 * The UAPSD queue is an exception, since we take a desc-
1293 * based intr on the EOSP frames.
1295 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1296 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1297 TXQ_FLAG_TXERRINT_ENABLE;
1299 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1300 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1302 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1303 TXQ_FLAG_TXDESCINT_ENABLE;
1305 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1306 if (axq_qnum == -1) {
1308 * NB: don't print a message, this happens
1309 * normally on parts with too few tx queues
1313 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1314 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1316 txq->axq_qnum = axq_qnum;
1317 txq->mac80211_qnum = -1;
1318 txq->axq_link = NULL;
1319 INIT_LIST_HEAD(&txq->axq_q);
1320 INIT_LIST_HEAD(&txq->axq_acq);
1321 spin_lock_init(&txq->axq_lock);
1323 txq->axq_ampdu_depth = 0;
1324 txq->axq_tx_inprogress = false;
1325 sc->tx.txqsetup |= 1<<axq_qnum;
1327 txq->txq_headidx = txq->txq_tailidx = 0;
1328 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1329 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1331 return &sc->tx.txq[axq_qnum];
1334 int ath_txq_update(struct ath_softc *sc, int qnum,
1335 struct ath9k_tx_queue_info *qinfo)
1337 struct ath_hw *ah = sc->sc_ah;
1339 struct ath9k_tx_queue_info qi;
1341 if (qnum == sc->beacon.beaconq) {
1343 * XXX: for beacon queue, we just save the parameter.
1344 * It will be picked up by ath_beaconq_config when
1347 sc->beacon.beacon_qi = *qinfo;
1351 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1353 ath9k_hw_get_txq_props(ah, qnum, &qi);
1354 qi.tqi_aifs = qinfo->tqi_aifs;
1355 qi.tqi_cwmin = qinfo->tqi_cwmin;
1356 qi.tqi_cwmax = qinfo->tqi_cwmax;
1357 qi.tqi_burstTime = qinfo->tqi_burstTime;
1358 qi.tqi_readyTime = qinfo->tqi_readyTime;
1360 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1361 ath_err(ath9k_hw_common(sc->sc_ah),
1362 "Unable to update hardware queue %u!\n", qnum);
1365 ath9k_hw_resettxqueue(ah, qnum);
1371 int ath_cabq_update(struct ath_softc *sc)
1373 struct ath9k_tx_queue_info qi;
1374 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1375 int qnum = sc->beacon.cabq->axq_qnum;
1377 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1379 * Ensure the readytime % is within the bounds.
1381 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1382 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1383 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1384 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1386 qi.tqi_readyTime = (cur_conf->beacon_interval *
1387 sc->config.cabqReadytime) / 100;
1388 ath_txq_update(sc, qnum, &qi);
1393 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1395 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1396 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1399 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1400 struct list_head *list, bool retry_tx)
1401 __releases(txq->axq_lock)
1402 __acquires(txq->axq_lock)
1404 struct ath_buf *bf, *lastbf;
1405 struct list_head bf_head;
1406 struct ath_tx_status ts;
1408 memset(&ts, 0, sizeof(ts));
1409 ts.ts_status = ATH9K_TX_FLUSH;
1410 INIT_LIST_HEAD(&bf_head);
1412 while (!list_empty(list)) {
1413 bf = list_first_entry(list, struct ath_buf, list);
1416 list_del(&bf->list);
1418 ath_tx_return_buffer(sc, bf);
1422 lastbf = bf->bf_lastbf;
1423 list_cut_position(&bf_head, list, &lastbf->list);
1426 if (bf_is_ampdu_not_probing(bf))
1427 txq->axq_ampdu_depth--;
1429 spin_unlock_bh(&txq->axq_lock);
1431 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1434 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1435 spin_lock_bh(&txq->axq_lock);
1440 * Drain a given TX queue (could be Beacon or Data)
1442 * This assumes output has been stopped and
1443 * we do not need to block ath_tx_tasklet.
1445 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1447 spin_lock_bh(&txq->axq_lock);
1448 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1449 int idx = txq->txq_tailidx;
1451 while (!list_empty(&txq->txq_fifo[idx])) {
1452 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1455 INCR(idx, ATH_TXFIFO_DEPTH);
1457 txq->txq_tailidx = idx;
1460 txq->axq_link = NULL;
1461 txq->axq_tx_inprogress = false;
1462 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1464 /* flush any pending frames if aggregation is enabled */
1465 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1466 ath_txq_drain_pending_buffers(sc, txq);
1468 spin_unlock_bh(&txq->axq_lock);
1471 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1473 struct ath_hw *ah = sc->sc_ah;
1474 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1475 struct ath_txq *txq;
1479 if (sc->sc_flags & SC_OP_INVALID)
1482 ath9k_hw_abort_tx_dma(ah);
1484 /* Check if any queue remains active */
1485 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1486 if (!ATH_TXQ_SETUP(sc, i))
1489 if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1494 ath_err(common, "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1496 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1497 if (!ATH_TXQ_SETUP(sc, i))
1501 * The caller will resume queues with ieee80211_wake_queues.
1502 * Mark the queue as not stopped to prevent ath_tx_complete
1503 * from waking the queue too early.
1505 txq = &sc->tx.txq[i];
1506 txq->stopped = false;
1507 ath_draintxq(sc, txq, retry_tx);
1513 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1515 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1516 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1519 /* For each axq_acq entry, for each tid, try to schedule packets
1520 * for transmit until ampdu_depth has reached min Q depth.
1522 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1524 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1525 struct ath_atx_tid *tid, *last_tid;
1527 if (work_pending(&sc->hw_reset_work) || list_empty(&txq->axq_acq) ||
1528 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1531 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1532 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1534 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1535 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1536 list_del(&ac->list);
1539 while (!list_empty(&ac->tid_q)) {
1540 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1542 list_del(&tid->list);
1548 ath_tx_sched_aggr(sc, txq, tid);
1551 * add tid to round-robin queue if more frames
1552 * are pending for the tid
1554 if (!skb_queue_empty(&tid->buf_q))
1555 ath_tx_queue_tid(txq, tid);
1557 if (tid == last_tid ||
1558 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1562 if (!list_empty(&ac->tid_q)) {
1565 list_add_tail(&ac->list, &txq->axq_acq);
1569 if (ac == last_ac ||
1570 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1580 * Insert a chain of ath_buf (descriptors) on a txq and
1581 * assume the descriptors are already chained together by caller.
1583 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1584 struct list_head *head, bool internal)
1586 struct ath_hw *ah = sc->sc_ah;
1587 struct ath_common *common = ath9k_hw_common(ah);
1588 struct ath_buf *bf, *bf_last;
1589 bool puttxbuf = false;
1593 * Insert the frame on the outbound list and
1594 * pass it on to the hardware.
1597 if (list_empty(head))
1600 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1601 bf = list_first_entry(head, struct ath_buf, list);
1602 bf_last = list_entry(head->prev, struct ath_buf, list);
1604 ath_dbg(common, ATH_DBG_QUEUE,
1605 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1607 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1608 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1609 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1612 list_splice_tail_init(head, &txq->axq_q);
1614 if (txq->axq_link) {
1615 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1616 ath_dbg(common, ATH_DBG_XMIT,
1617 "link[%u] (%p)=%llx (%p)\n",
1618 txq->axq_qnum, txq->axq_link,
1619 ito64(bf->bf_daddr), bf->bf_desc);
1623 txq->axq_link = bf_last->bf_desc;
1627 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1628 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1629 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1630 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1634 TX_STAT_INC(txq->axq_qnum, txstart);
1635 ath9k_hw_txstart(ah, txq->axq_qnum);
1640 if (bf_is_ampdu_not_probing(bf))
1641 txq->axq_ampdu_depth++;
1645 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1646 struct sk_buff *skb, struct ath_tx_control *txctl)
1648 struct ath_frame_info *fi = get_frame_info(skb);
1649 struct list_head bf_head;
1653 * Do not queue to h/w when any of the following conditions is true:
1654 * - there are pending frames in software queue
1655 * - the TID is currently paused for ADDBA/BAR request
1656 * - seqno is not within block-ack window
1657 * - h/w queue depth exceeds low water mark
1659 if (!skb_queue_empty(&tid->buf_q) || tid->paused ||
1660 !BAW_WITHIN(tid->seq_start, tid->baw_size, tid->seq_next) ||
1661 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1663 * Add this frame to software queue for scheduling later
1666 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1667 __skb_queue_tail(&tid->buf_q, skb);
1668 if (!txctl->an || !txctl->an->sleeping)
1669 ath_tx_queue_tid(txctl->txq, tid);
1673 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb, false);
1677 bf->bf_state.bf_type = BUF_AMPDU;
1678 INIT_LIST_HEAD(&bf_head);
1679 list_add(&bf->list, &bf_head);
1681 /* Add sub-frame to BAW */
1682 ath_tx_addto_baw(sc, tid, bf->bf_state.seqno);
1684 /* Queue to h/w without aggregation */
1685 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1687 ath_tx_fill_desc(sc, bf, txctl->txq, fi->framelen);
1688 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1691 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1692 struct ath_atx_tid *tid, struct sk_buff *skb)
1694 struct ath_frame_info *fi = get_frame_info(skb);
1695 struct list_head bf_head;
1700 bf = ath_tx_setup_buffer(sc, txq, tid, skb, false);
1705 INIT_LIST_HEAD(&bf_head);
1706 list_add_tail(&bf->list, &bf_head);
1707 bf->bf_state.bf_type = 0;
1709 /* update starting sequence number for subsequent ADDBA request */
1711 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1714 ath_tx_fill_desc(sc, bf, txq, fi->framelen);
1715 ath_tx_txqaddbuf(sc, txq, &bf_head, false);
1716 TX_STAT_INC(txq->axq_qnum, queued);
1719 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1722 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1723 struct ieee80211_sta *sta = tx_info->control.sta;
1724 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1725 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1726 struct ath_frame_info *fi = get_frame_info(skb);
1727 struct ath_node *an = NULL;
1728 enum ath9k_key_type keytype;
1730 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1733 an = (struct ath_node *) sta->drv_priv;
1735 memset(fi, 0, sizeof(*fi));
1737 fi->keyix = hw_key->hw_key_idx;
1738 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1739 fi->keyix = an->ps_key;
1741 fi->keyix = ATH9K_TXKEYIX_INVALID;
1742 fi->keytype = keytype;
1743 fi->framelen = framelen;
1746 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1748 struct ath_hw *ah = sc->sc_ah;
1749 struct ath9k_channel *curchan = ah->curchan;
1750 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1751 (curchan->channelFlags & CHANNEL_5GHZ) &&
1752 (chainmask == 0x7) && (rate < 0x90))
1759 * Assign a descriptor (and sequence number if necessary,
1760 * and map buffer for DMA. Frees skb on error
1762 static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
1763 struct ath_txq *txq,
1764 struct ath_atx_tid *tid,
1765 struct sk_buff *skb,
1768 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1769 struct ath_frame_info *fi = get_frame_info(skb);
1770 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1774 bf = ath_tx_get_buffer(sc);
1776 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1780 ATH_TXBUF_RESET(bf);
1783 seqno = tid->seq_next;
1784 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1785 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1786 bf->bf_state.seqno = seqno;
1791 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1792 skb->len, DMA_TO_DEVICE);
1793 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1795 bf->bf_buf_addr = 0;
1796 ath_err(ath9k_hw_common(sc->sc_ah),
1797 "dma_mapping_error() on TX\n");
1798 ath_tx_return_buffer(sc, bf);
1808 __skb_unlink(skb, &tid->buf_q);
1809 dev_kfree_skb_any(skb);
1813 /* FIXME: tx power */
1814 static void ath_tx_start_dma(struct ath_softc *sc, struct sk_buff *skb,
1815 struct ath_tx_control *txctl)
1817 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1818 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1819 struct ath_atx_tid *tid = NULL;
1823 spin_lock_bh(&txctl->txq->axq_lock);
1824 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1825 ieee80211_is_data_qos(hdr->frame_control)) {
1826 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1827 IEEE80211_QOS_CTL_TID_MASK;
1828 tid = ATH_AN_2_TID(txctl->an, tidno);
1830 WARN_ON(tid->ac->txq != txctl->txq);
1833 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1835 * Try aggregation if it's a unicast data frame
1836 * and the destination is HT capable.
1838 ath_tx_send_ampdu(sc, tid, skb, txctl);
1840 bf = ath_tx_setup_buffer(sc, txctl->txq, tid, skb, false);
1844 bf->bf_state.bfs_paprd = txctl->paprd;
1847 bf->bf_state.bfs_paprd_timestamp = jiffies;
1849 ath_tx_send_normal(sc, txctl->txq, tid, skb);
1853 spin_unlock_bh(&txctl->txq->axq_lock);
1856 /* Upon failure caller should free skb */
1857 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1858 struct ath_tx_control *txctl)
1860 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1861 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1862 struct ieee80211_sta *sta = info->control.sta;
1863 struct ieee80211_vif *vif = info->control.vif;
1864 struct ath_softc *sc = hw->priv;
1865 struct ath_txq *txq = txctl->txq;
1866 int padpos, padsize;
1867 int frmlen = skb->len + FCS_LEN;
1870 /* NOTE: sta can be NULL according to net/mac80211.h */
1872 txctl->an = (struct ath_node *)sta->drv_priv;
1874 if (info->control.hw_key)
1875 frmlen += info->control.hw_key->icv_len;
1878 * As a temporary workaround, assign seq# here; this will likely need
1879 * to be cleaned up to work better with Beacon transmission and virtual
1882 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1883 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1884 sc->tx.seq_no += 0x10;
1885 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1886 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1889 /* Add the padding after the header if this is not already done */
1890 padpos = ath9k_cmn_padpos(hdr->frame_control);
1891 padsize = padpos & 3;
1892 if (padsize && skb->len > padpos) {
1893 if (skb_headroom(skb) < padsize)
1896 skb_push(skb, padsize);
1897 memmove(skb->data, skb->data + padsize, padpos);
1898 hdr = (struct ieee80211_hdr *) skb->data;
1901 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1902 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1903 !ieee80211_is_data(hdr->frame_control))
1904 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1906 setup_frame_info(hw, skb, frmlen);
1909 * At this point, the vif, hw_key and sta pointers in the tx control
1910 * info are no longer valid (overwritten by the ath_frame_info data.
1913 q = skb_get_queue_mapping(skb);
1914 spin_lock_bh(&txq->axq_lock);
1915 if (txq == sc->tx.txq_map[q] &&
1916 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1917 ieee80211_stop_queue(sc->hw, q);
1920 spin_unlock_bh(&txq->axq_lock);
1922 ath_tx_start_dma(sc, skb, txctl);
1930 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1931 int tx_flags, struct ath_txq *txq)
1933 struct ieee80211_hw *hw = sc->hw;
1934 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1935 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1936 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1937 int q, padpos, padsize;
1939 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1941 if (tx_flags & ATH_TX_BAR)
1942 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1944 if (!(tx_flags & ATH_TX_ERROR))
1945 /* Frame was ACKed */
1946 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1948 padpos = ath9k_cmn_padpos(hdr->frame_control);
1949 padsize = padpos & 3;
1950 if (padsize && skb->len>padpos+padsize) {
1952 * Remove MAC header padding before giving the frame back to
1955 memmove(skb->data + padsize, skb->data, padpos);
1956 skb_pull(skb, padsize);
1959 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1960 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1961 ath_dbg(common, ATH_DBG_PS,
1962 "Going back to sleep after having received TX status (0x%lx)\n",
1963 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1965 PS_WAIT_FOR_PSPOLL_DATA |
1966 PS_WAIT_FOR_TX_ACK));
1969 q = skb_get_queue_mapping(skb);
1970 if (txq == sc->tx.txq_map[q]) {
1971 spin_lock_bh(&txq->axq_lock);
1972 if (WARN_ON(--txq->pending_frames < 0))
1973 txq->pending_frames = 0;
1975 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1976 ieee80211_wake_queue(sc->hw, q);
1979 spin_unlock_bh(&txq->axq_lock);
1982 ieee80211_tx_status(hw, skb);
1985 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1986 struct ath_txq *txq, struct list_head *bf_q,
1987 struct ath_tx_status *ts, int txok, int sendbar)
1989 struct sk_buff *skb = bf->bf_mpdu;
1990 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1991 unsigned long flags;
1995 tx_flags = ATH_TX_BAR;
1998 tx_flags |= ATH_TX_ERROR;
2000 if (ts->ts_status & ATH9K_TXERR_FILT)
2001 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2003 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2004 bf->bf_buf_addr = 0;
2006 if (bf->bf_state.bfs_paprd) {
2007 if (time_after(jiffies,
2008 bf->bf_state.bfs_paprd_timestamp +
2009 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2010 dev_kfree_skb_any(skb);
2012 complete(&sc->paprd_complete);
2014 ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2015 ath_tx_complete(sc, skb, tx_flags, txq);
2017 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2018 * accidentally reference it later.
2023 * Return the list of ath_buf of this mpdu to free queue
2025 spin_lock_irqsave(&sc->tx.txbuflock, flags);
2026 list_splice_tail_init(bf_q, &sc->tx.txbuf);
2027 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2030 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2031 struct ath_tx_status *ts, int nframes, int nbad,
2034 struct sk_buff *skb = bf->bf_mpdu;
2035 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2036 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2037 struct ieee80211_hw *hw = sc->hw;
2038 struct ath_hw *ah = sc->sc_ah;
2042 tx_info->status.ack_signal = ts->ts_rssi;
2044 tx_rateindex = ts->ts_rateindex;
2045 WARN_ON(tx_rateindex >= hw->max_rates);
2047 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2048 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2050 BUG_ON(nbad > nframes);
2052 tx_info->status.ampdu_len = nframes;
2053 tx_info->status.ampdu_ack_len = nframes - nbad;
2055 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2056 (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2058 * If an underrun error is seen assume it as an excessive
2059 * retry only if max frame trigger level has been reached
2060 * (2 KB for single stream, and 4 KB for dual stream).
2061 * Adjust the long retry as if the frame was tried
2062 * hw->max_rate_tries times to affect how rate control updates
2063 * PER for the failed rate.
2064 * In case of congestion on the bus penalizing this type of
2065 * underruns should help hardware actually transmit new frames
2066 * successfully by eventually preferring slower rates.
2067 * This itself should also alleviate congestion on the bus.
2069 if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2070 ATH9K_TX_DELIM_UNDERRUN)) &&
2071 ieee80211_is_data(hdr->frame_control) &&
2072 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2073 tx_info->status.rates[tx_rateindex].count =
2077 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2078 tx_info->status.rates[i].count = 0;
2079 tx_info->status.rates[i].idx = -1;
2082 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2085 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2086 struct ath_tx_status *ts, struct ath_buf *bf,
2087 struct list_head *bf_head)
2088 __releases(txq->axq_lock)
2089 __acquires(txq->axq_lock)
2094 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2095 txq->axq_tx_inprogress = false;
2096 if (bf_is_ampdu_not_probing(bf))
2097 txq->axq_ampdu_depth--;
2099 spin_unlock_bh(&txq->axq_lock);
2101 if (!bf_isampdu(bf)) {
2102 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
2103 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2105 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2107 spin_lock_bh(&txq->axq_lock);
2109 if (sc->sc_flags & SC_OP_TXAGGR)
2110 ath_txq_schedule(sc, txq);
2113 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2115 struct ath_hw *ah = sc->sc_ah;
2116 struct ath_common *common = ath9k_hw_common(ah);
2117 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2118 struct list_head bf_head;
2119 struct ath_desc *ds;
2120 struct ath_tx_status ts;
2123 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2124 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2127 spin_lock_bh(&txq->axq_lock);
2129 if (work_pending(&sc->hw_reset_work))
2132 if (list_empty(&txq->axq_q)) {
2133 txq->axq_link = NULL;
2134 if (sc->sc_flags & SC_OP_TXAGGR)
2135 ath_txq_schedule(sc, txq);
2138 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2141 * There is a race condition that a BH gets scheduled
2142 * after sw writes TxE and before hw re-load the last
2143 * descriptor to get the newly chained one.
2144 * Software must keep the last DONE descriptor as a
2145 * holding descriptor - software does so by marking
2146 * it with the STALE flag.
2151 if (list_is_last(&bf_held->list, &txq->axq_q))
2154 bf = list_entry(bf_held->list.next, struct ath_buf,
2158 lastbf = bf->bf_lastbf;
2159 ds = lastbf->bf_desc;
2161 memset(&ts, 0, sizeof(ts));
2162 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2163 if (status == -EINPROGRESS)
2166 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2169 * Remove ath_buf's of the same transmit unit from txq,
2170 * however leave the last descriptor back as the holding
2171 * descriptor for hw.
2173 lastbf->bf_stale = true;
2174 INIT_LIST_HEAD(&bf_head);
2175 if (!list_is_singular(&lastbf->list))
2176 list_cut_position(&bf_head,
2177 &txq->axq_q, lastbf->list.prev);
2180 list_del(&bf_held->list);
2181 ath_tx_return_buffer(sc, bf_held);
2184 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2186 spin_unlock_bh(&txq->axq_lock);
2189 static void ath_tx_complete_poll_work(struct work_struct *work)
2191 struct ath_softc *sc = container_of(work, struct ath_softc,
2192 tx_complete_work.work);
2193 struct ath_txq *txq;
2195 bool needreset = false;
2196 #ifdef CONFIG_ATH9K_DEBUGFS
2197 sc->tx_complete_poll_work_seen++;
2200 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2201 if (ATH_TXQ_SETUP(sc, i)) {
2202 txq = &sc->tx.txq[i];
2203 spin_lock_bh(&txq->axq_lock);
2204 if (txq->axq_depth) {
2205 if (txq->axq_tx_inprogress) {
2207 spin_unlock_bh(&txq->axq_lock);
2210 txq->axq_tx_inprogress = true;
2213 spin_unlock_bh(&txq->axq_lock);
2217 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2218 "tx hung, resetting the chip\n");
2219 RESET_STAT_INC(sc, RESET_TYPE_TX_HANG);
2220 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
2223 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2224 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2229 void ath_tx_tasklet(struct ath_softc *sc)
2232 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2234 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2236 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2237 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2238 ath_tx_processq(sc, &sc->tx.txq[i]);
2242 void ath_tx_edma_tasklet(struct ath_softc *sc)
2244 struct ath_tx_status ts;
2245 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2246 struct ath_hw *ah = sc->sc_ah;
2247 struct ath_txq *txq;
2248 struct ath_buf *bf, *lastbf;
2249 struct list_head bf_head;
2253 if (work_pending(&sc->hw_reset_work))
2256 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2257 if (status == -EINPROGRESS)
2259 if (status == -EIO) {
2260 ath_dbg(common, ATH_DBG_XMIT,
2261 "Error processing tx status\n");
2265 /* Skip beacon completions */
2266 if (ts.qid == sc->beacon.beaconq)
2269 txq = &sc->tx.txq[ts.qid];
2271 spin_lock_bh(&txq->axq_lock);
2273 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2274 spin_unlock_bh(&txq->axq_lock);
2278 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2279 struct ath_buf, list);
2280 lastbf = bf->bf_lastbf;
2282 INIT_LIST_HEAD(&bf_head);
2283 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2286 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2287 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2289 if (!list_empty(&txq->axq_q)) {
2290 struct list_head bf_q;
2292 INIT_LIST_HEAD(&bf_q);
2293 txq->axq_link = NULL;
2294 list_splice_tail_init(&txq->axq_q, &bf_q);
2295 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2299 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2300 spin_unlock_bh(&txq->axq_lock);
2308 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2310 struct ath_descdma *dd = &sc->txsdma;
2311 u8 txs_len = sc->sc_ah->caps.txs_len;
2313 dd->dd_desc_len = size * txs_len;
2314 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2315 &dd->dd_desc_paddr, GFP_KERNEL);
2322 static int ath_tx_edma_init(struct ath_softc *sc)
2326 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2328 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2329 sc->txsdma.dd_desc_paddr,
2330 ATH_TXSTATUS_RING_SIZE);
2335 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2337 struct ath_descdma *dd = &sc->txsdma;
2339 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2343 int ath_tx_init(struct ath_softc *sc, int nbufs)
2345 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2348 spin_lock_init(&sc->tx.txbuflock);
2350 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2354 "Failed to allocate tx descriptors: %d\n", error);
2358 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2359 "beacon", ATH_BCBUF, 1, 1);
2362 "Failed to allocate beacon descriptors: %d\n", error);
2366 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2368 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2369 error = ath_tx_edma_init(sc);
2381 void ath_tx_cleanup(struct ath_softc *sc)
2383 if (sc->beacon.bdma.dd_desc_len != 0)
2384 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2386 if (sc->tx.txdma.dd_desc_len != 0)
2387 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2389 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2390 ath_tx_edma_cleanup(sc);
2393 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2395 struct ath_atx_tid *tid;
2396 struct ath_atx_ac *ac;
2399 for (tidno = 0, tid = &an->tid[tidno];
2400 tidno < WME_NUM_TID;
2404 tid->seq_start = tid->seq_next = 0;
2405 tid->baw_size = WME_MAX_BA;
2406 tid->baw_head = tid->baw_tail = 0;
2408 tid->paused = false;
2409 tid->state &= ~AGGR_CLEANUP;
2410 __skb_queue_head_init(&tid->buf_q);
2411 acno = TID_TO_WME_AC(tidno);
2412 tid->ac = &an->ac[acno];
2413 tid->state &= ~AGGR_ADDBA_COMPLETE;
2414 tid->state &= ~AGGR_ADDBA_PROGRESS;
2417 for (acno = 0, ac = &an->ac[acno];
2418 acno < WME_NUM_AC; acno++, ac++) {
2420 ac->txq = sc->tx.txq_map[acno];
2421 INIT_LIST_HEAD(&ac->tid_q);
2425 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2427 struct ath_atx_ac *ac;
2428 struct ath_atx_tid *tid;
2429 struct ath_txq *txq;
2432 for (tidno = 0, tid = &an->tid[tidno];
2433 tidno < WME_NUM_TID; tidno++, tid++) {
2438 spin_lock_bh(&txq->axq_lock);
2441 list_del(&tid->list);
2446 list_del(&ac->list);
2447 tid->ac->sched = false;
2450 ath_tid_drain(sc, txq, tid);
2451 tid->state &= ~AGGR_ADDBA_COMPLETE;
2452 tid->state &= ~AGGR_CLEANUP;
2454 spin_unlock_bh(&txq->axq_lock);