2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
20 #define BITS_PER_BYTE 8
21 #define OFDM_PLCP_BITS 22
22 #define HT_RC_2_MCS(_rc) ((_rc) & 0x1f)
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
35 #define OFDM_SIFS_TIME 16
37 static u16 bits_per_symbol[][2] = {
39 { 26, 54 }, /* 0: BPSK */
40 { 52, 108 }, /* 1: QPSK 1/2 */
41 { 78, 162 }, /* 2: QPSK 3/4 */
42 { 104, 216 }, /* 3: 16-QAM 1/2 */
43 { 156, 324 }, /* 4: 16-QAM 3/4 */
44 { 208, 432 }, /* 5: 64-QAM 2/3 */
45 { 234, 486 }, /* 6: 64-QAM 3/4 */
46 { 260, 540 }, /* 7: 64-QAM 5/6 */
49 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
51 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
52 struct ath_atx_tid *tid,
53 struct list_head *bf_head);
54 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
55 struct ath_txq *txq, struct list_head *bf_q,
56 struct ath_tx_status *ts, int txok, int sendbar);
57 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
58 struct list_head *head);
59 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
60 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
61 int nframes, int nbad, int txok, bool update_rc);
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
72 static int ath_max_4ms_framelen[4][32] = {
74 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
75 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
76 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
77 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
80 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
81 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
82 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
83 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
86 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
87 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
88 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
89 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
92 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
93 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
94 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
95 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
99 /*********************/
100 /* Aggregation logic */
101 /*********************/
103 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
105 struct ath_atx_ac *ac = tid->ac;
114 list_add_tail(&tid->list, &ac->tid_q);
120 list_add_tail(&ac->list, &txq->axq_acq);
123 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
125 struct ath_txq *txq = tid->ac->txq;
127 WARN_ON(!tid->paused);
129 spin_lock_bh(&txq->axq_lock);
132 if (list_empty(&tid->buf_q))
135 ath_tx_queue_tid(txq, tid);
136 ath_txq_schedule(sc, txq);
138 spin_unlock_bh(&txq->axq_lock);
141 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
143 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
144 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
145 sizeof(tx_info->rate_driver_data));
146 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
149 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
151 struct ath_txq *txq = tid->ac->txq;
153 struct list_head bf_head;
154 struct ath_tx_status ts;
155 struct ath_frame_info *fi;
157 INIT_LIST_HEAD(&bf_head);
159 memset(&ts, 0, sizeof(ts));
160 spin_lock_bh(&txq->axq_lock);
162 while (!list_empty(&tid->buf_q)) {
163 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
164 list_move_tail(&bf->list, &bf_head);
166 spin_unlock_bh(&txq->axq_lock);
167 fi = get_frame_info(bf->bf_mpdu);
169 ath_tx_update_baw(sc, tid, fi->seqno);
170 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
172 ath_tx_send_normal(sc, txq, tid, &bf_head);
174 spin_lock_bh(&txq->axq_lock);
177 spin_unlock_bh(&txq->axq_lock);
180 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
185 index = ATH_BA_INDEX(tid->seq_start, seqno);
186 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
188 __clear_bit(cindex, tid->tx_buf);
190 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
191 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
192 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
196 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
201 index = ATH_BA_INDEX(tid->seq_start, seqno);
202 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
203 __set_bit(cindex, tid->tx_buf);
205 if (index >= ((tid->baw_tail - tid->baw_head) &
206 (ATH_TID_MAX_BUFS - 1))) {
207 tid->baw_tail = cindex;
208 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
213 * TODO: For frame(s) that are in the retry state, we will reuse the
214 * sequence number(s) without setting the retry bit. The
215 * alternative is to give up on these and BAR the receiver's window
218 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
219 struct ath_atx_tid *tid)
223 struct list_head bf_head;
224 struct ath_tx_status ts;
225 struct ath_frame_info *fi;
227 memset(&ts, 0, sizeof(ts));
228 INIT_LIST_HEAD(&bf_head);
231 if (list_empty(&tid->buf_q))
234 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
235 list_move_tail(&bf->list, &bf_head);
237 fi = get_frame_info(bf->bf_mpdu);
239 ath_tx_update_baw(sc, tid, fi->seqno);
241 spin_unlock(&txq->axq_lock);
242 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
243 spin_lock(&txq->axq_lock);
246 tid->seq_next = tid->seq_start;
247 tid->baw_tail = tid->baw_head;
250 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
253 struct ath_frame_info *fi = get_frame_info(skb);
254 struct ieee80211_hdr *hdr;
256 TX_STAT_INC(txq->axq_qnum, a_retries);
257 if (fi->retries++ > 0)
260 hdr = (struct ieee80211_hdr *)skb->data;
261 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
264 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
266 struct ath_buf *bf = NULL;
268 spin_lock_bh(&sc->tx.txbuflock);
270 if (unlikely(list_empty(&sc->tx.txbuf))) {
271 spin_unlock_bh(&sc->tx.txbuflock);
275 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
278 spin_unlock_bh(&sc->tx.txbuflock);
283 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
285 spin_lock_bh(&sc->tx.txbuflock);
286 list_add_tail(&bf->list, &sc->tx.txbuf);
287 spin_unlock_bh(&sc->tx.txbuflock);
290 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
294 tbf = ath_tx_get_buffer(sc);
298 ATH_TXBUF_RESET(tbf);
300 tbf->aphy = bf->aphy;
301 tbf->bf_mpdu = bf->bf_mpdu;
302 tbf->bf_buf_addr = bf->bf_buf_addr;
303 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
304 tbf->bf_state = bf->bf_state;
309 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
310 struct ath_tx_status *ts, int txok,
311 int *nframes, int *nbad)
313 struct ath_frame_info *fi;
315 u32 ba[WME_BA_BMP_SIZE >> 5];
322 isaggr = bf_isaggr(bf);
324 seq_st = ts->ts_seqnum;
325 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
329 fi = get_frame_info(bf->bf_mpdu);
330 ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
333 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
341 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
342 struct ath_buf *bf, struct list_head *bf_q,
343 struct ath_tx_status *ts, int txok, bool retry)
345 struct ath_node *an = NULL;
347 struct ieee80211_sta *sta;
348 struct ieee80211_hw *hw;
349 struct ieee80211_hdr *hdr;
350 struct ieee80211_tx_info *tx_info;
351 struct ath_atx_tid *tid = NULL;
352 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
353 struct list_head bf_head, bf_pending;
354 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
355 u32 ba[WME_BA_BMP_SIZE >> 5];
356 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
357 bool rc_update = true;
358 struct ieee80211_tx_rate rates[4];
359 struct ath_frame_info *fi;
364 hdr = (struct ieee80211_hdr *)skb->data;
366 tx_info = IEEE80211_SKB_CB(skb);
369 memcpy(rates, tx_info->control.rates, sizeof(rates));
373 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
377 INIT_LIST_HEAD(&bf_head);
379 bf_next = bf->bf_next;
381 bf->bf_state.bf_type |= BUF_XRETRY;
382 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) ||
383 !bf->bf_stale || bf_next != NULL)
384 list_move_tail(&bf->list, &bf_head);
386 ath_tx_rc_status(bf, ts, 1, 1, 0, false);
387 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
395 an = (struct ath_node *)sta->drv_priv;
396 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
397 tid = ATH_AN_2_TID(an, tidno);
400 * The hardware occasionally sends a tx status for the wrong TID.
401 * In this case, the BA status cannot be considered valid and all
402 * subframes need to be retransmitted
404 if (tidno != ts->tid)
407 isaggr = bf_isaggr(bf);
408 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
410 if (isaggr && txok) {
411 if (ts->ts_flags & ATH9K_TX_BA) {
412 seq_st = ts->ts_seqnum;
413 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
416 * AR5416 can become deaf/mute when BA
417 * issue happens. Chip needs to be reset.
418 * But AP code may have sychronization issues
419 * when perform internal reset in this routine.
420 * Only enable reset in STA mode for now.
422 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
427 INIT_LIST_HEAD(&bf_pending);
428 INIT_LIST_HEAD(&bf_head);
430 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
432 txfail = txpending = 0;
433 bf_next = bf->bf_next;
436 tx_info = IEEE80211_SKB_CB(skb);
437 fi = get_frame_info(skb);
439 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
440 /* transmit completion, subframe is
441 * acked by block ack */
443 } else if (!isaggr && txok) {
444 /* transmit completion */
447 if (!(tid->state & AGGR_CLEANUP) && retry) {
448 if (fi->retries < ATH_MAX_SW_RETRIES) {
449 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
452 bf->bf_state.bf_type |= BUF_XRETRY;
459 * cleanup in progress, just fail
460 * the un-acked sub-frames
466 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
469 * Make sure the last desc is reclaimed if it
470 * not a holding desc.
472 if (!bf_last->bf_stale)
473 list_move_tail(&bf->list, &bf_head);
475 INIT_LIST_HEAD(&bf_head);
477 BUG_ON(list_empty(bf_q));
478 list_move_tail(&bf->list, &bf_head);
481 if (!txpending || (tid->state & AGGR_CLEANUP)) {
483 * complete the acked-ones/xretried ones; update
486 spin_lock_bh(&txq->axq_lock);
487 ath_tx_update_baw(sc, tid, fi->seqno);
488 spin_unlock_bh(&txq->axq_lock);
490 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
491 memcpy(tx_info->control.rates, rates, sizeof(rates));
492 ath_tx_rc_status(bf, ts, nframes, nbad, txok, true);
495 ath_tx_rc_status(bf, ts, nframes, nbad, txok, false);
498 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
501 /* retry the un-acked ones */
502 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
503 if (bf->bf_next == NULL && bf_last->bf_stale) {
506 tbf = ath_clone_txbuf(sc, bf_last);
508 * Update tx baw and complete the
509 * frame with failed status if we
513 spin_lock_bh(&txq->axq_lock);
514 ath_tx_update_baw(sc, tid, fi->seqno);
515 spin_unlock_bh(&txq->axq_lock);
517 bf->bf_state.bf_type |=
519 ath_tx_rc_status(bf, ts, nframes,
521 ath_tx_complete_buf(sc, bf, txq,
527 ath9k_hw_cleartxdesc(sc->sc_ah,
529 list_add_tail(&tbf->list, &bf_head);
532 * Clear descriptor status words for
535 ath9k_hw_cleartxdesc(sc->sc_ah,
541 * Put this buffer to the temporary pending
542 * queue to retain ordering
544 list_splice_tail_init(&bf_head, &bf_pending);
550 /* prepend un-acked frames to the beginning of the pending frame queue */
551 if (!list_empty(&bf_pending)) {
552 spin_lock_bh(&txq->axq_lock);
553 list_splice(&bf_pending, &tid->buf_q);
554 ath_tx_queue_tid(txq, tid);
555 spin_unlock_bh(&txq->axq_lock);
558 if (tid->state & AGGR_CLEANUP) {
559 ath_tx_flush_tid(sc, tid);
561 if (tid->baw_head == tid->baw_tail) {
562 tid->state &= ~AGGR_ADDBA_COMPLETE;
563 tid->state &= ~AGGR_CLEANUP;
570 ath_reset(sc, false);
573 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
574 struct ath_atx_tid *tid)
577 struct ieee80211_tx_info *tx_info;
578 struct ieee80211_tx_rate *rates;
579 u32 max_4ms_framelen, frmlen;
580 u16 aggr_limit, legacy = 0;
584 tx_info = IEEE80211_SKB_CB(skb);
585 rates = tx_info->control.rates;
588 * Find the lowest frame length among the rate series that will have a
589 * 4ms transmit duration.
590 * TODO - TXOP limit needs to be considered.
592 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
594 for (i = 0; i < 4; i++) {
595 if (rates[i].count) {
597 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
602 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
607 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
610 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
611 max_4ms_framelen = min(max_4ms_framelen, frmlen);
616 * limit aggregate size by the minimum rate if rate selected is
617 * not a probe rate, if rate selected is a probe rate then
618 * avoid aggregation of this packet.
620 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
623 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
624 aggr_limit = min((max_4ms_framelen * 3) / 8,
625 (u32)ATH_AMPDU_LIMIT_MAX);
627 aggr_limit = min(max_4ms_framelen,
628 (u32)ATH_AMPDU_LIMIT_MAX);
631 * h/w can accept aggregates upto 16 bit lengths (65535).
632 * The IE, however can hold upto 65536, which shows up here
633 * as zero. Ignore 65536 since we are constrained by hw.
635 if (tid->an->maxampdu)
636 aggr_limit = min(aggr_limit, tid->an->maxampdu);
642 * Returns the number of delimiters to be added to
643 * meet the minimum required mpdudensity.
645 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
646 struct ath_buf *bf, u16 frmlen)
648 struct sk_buff *skb = bf->bf_mpdu;
649 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
650 u32 nsymbits, nsymbols;
653 int width, streams, half_gi, ndelim, mindelim;
654 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
656 /* Select standard number of delimiters based on frame length alone */
657 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
660 * If encryption enabled, hardware requires some more padding between
662 * TODO - this could be improved to be dependent on the rate.
663 * The hardware can keep up at lower rates, but not higher rates
665 if (fi->keyix != ATH9K_TXKEYIX_INVALID)
666 ndelim += ATH_AGGR_ENCRYPTDELIM;
669 * Convert desired mpdu density from microeconds to bytes based
670 * on highest rate in rate series (i.e. first rate) to determine
671 * required minimum length for subframe. Take into account
672 * whether high rate is 20 or 40Mhz and half or full GI.
674 * If there is no mpdu density restriction, no further calculation
678 if (tid->an->mpdudensity == 0)
681 rix = tx_info->control.rates[0].idx;
682 flags = tx_info->control.rates[0].flags;
683 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
684 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
687 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
689 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
694 streams = HT_RC_2_STREAMS(rix);
695 nsymbits = bits_per_symbol[rix % 8][width] * streams;
696 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
698 if (frmlen < minlen) {
699 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
700 ndelim = max(mindelim, ndelim);
706 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
708 struct ath_atx_tid *tid,
709 struct list_head *bf_q,
712 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
713 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
714 int rl = 0, nframes = 0, ndelim, prev_al = 0;
715 u16 aggr_limit = 0, al = 0, bpad = 0,
716 al_delta, h_baw = tid->baw_size / 2;
717 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
718 struct ieee80211_tx_info *tx_info;
719 struct ath_frame_info *fi;
721 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
724 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
725 fi = get_frame_info(bf->bf_mpdu);
727 /* do not step over block-ack window */
728 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
729 status = ATH_AGGR_BAW_CLOSED;
734 aggr_limit = ath_lookup_rate(sc, bf, tid);
738 /* do not exceed aggregation limit */
739 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
742 (aggr_limit < (al + bpad + al_delta + prev_al))) {
743 status = ATH_AGGR_LIMITED;
747 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
748 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
749 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
752 /* do not exceed subframe limit */
753 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
754 status = ATH_AGGR_LIMITED;
759 /* add padding for previous frame to aggregation length */
760 al += bpad + al_delta;
763 * Get the delimiters needed to meet the MPDU
764 * density for this node.
766 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen);
767 bpad = PADBYTES(al_delta) + (ndelim << 2);
770 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
772 /* link buffers of this frame to the aggregate */
774 ath_tx_addto_baw(sc, tid, fi->seqno);
775 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
776 list_move_tail(&bf->list, bf_q);
778 bf_prev->bf_next = bf;
779 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
784 } while (!list_empty(&tid->buf_q));
792 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
793 struct ath_atx_tid *tid)
796 enum ATH_AGGR_STATUS status;
797 struct ath_frame_info *fi;
798 struct list_head bf_q;
802 if (list_empty(&tid->buf_q))
805 INIT_LIST_HEAD(&bf_q);
807 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
810 * no frames picked up to be aggregated;
811 * block-ack window is not open.
813 if (list_empty(&bf_q))
816 bf = list_first_entry(&bf_q, struct ath_buf, list);
817 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
819 /* if only one frame, send as non-aggregate */
820 if (bf == bf->bf_lastbf) {
821 fi = get_frame_info(bf->bf_mpdu);
823 bf->bf_state.bf_type &= ~BUF_AGGR;
824 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
825 ath_buf_set_rate(sc, bf, fi->framelen);
826 ath_tx_txqaddbuf(sc, txq, &bf_q);
830 /* setup first desc of aggregate */
831 bf->bf_state.bf_type |= BUF_AGGR;
832 ath_buf_set_rate(sc, bf, aggr_len);
833 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
835 /* anchor last desc of aggregate */
836 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
838 ath_tx_txqaddbuf(sc, txq, &bf_q);
839 TX_STAT_INC(txq->axq_qnum, a_aggr);
841 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
842 status != ATH_AGGR_BAW_CLOSED);
845 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
848 struct ath_atx_tid *txtid;
851 an = (struct ath_node *)sta->drv_priv;
852 txtid = ATH_AN_2_TID(an, tid);
854 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
857 txtid->state |= AGGR_ADDBA_PROGRESS;
858 txtid->paused = true;
859 *ssn = txtid->seq_start;
864 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
866 struct ath_node *an = (struct ath_node *)sta->drv_priv;
867 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
868 struct ath_txq *txq = txtid->ac->txq;
870 if (txtid->state & AGGR_CLEANUP)
873 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
874 txtid->state &= ~AGGR_ADDBA_PROGRESS;
878 spin_lock_bh(&txq->axq_lock);
879 txtid->paused = true;
882 * If frames are still being transmitted for this TID, they will be
883 * cleaned up during tx completion. To prevent race conditions, this
884 * TID can only be reused after all in-progress subframes have been
887 if (txtid->baw_head != txtid->baw_tail)
888 txtid->state |= AGGR_CLEANUP;
890 txtid->state &= ~AGGR_ADDBA_COMPLETE;
891 spin_unlock_bh(&txq->axq_lock);
893 ath_tx_flush_tid(sc, txtid);
896 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
898 struct ath_atx_tid *txtid;
901 an = (struct ath_node *)sta->drv_priv;
903 if (sc->sc_flags & SC_OP_TXAGGR) {
904 txtid = ATH_AN_2_TID(an, tid);
906 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
907 txtid->state |= AGGR_ADDBA_COMPLETE;
908 txtid->state &= ~AGGR_ADDBA_PROGRESS;
909 ath_tx_resume_tid(sc, txtid);
913 /********************/
914 /* Queue Management */
915 /********************/
917 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
920 struct ath_atx_ac *ac, *ac_tmp;
921 struct ath_atx_tid *tid, *tid_tmp;
923 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
926 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
927 list_del(&tid->list);
929 ath_tid_drain(sc, txq, tid);
934 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
936 struct ath_hw *ah = sc->sc_ah;
937 struct ath_common *common = ath9k_hw_common(ah);
938 struct ath9k_tx_queue_info qi;
939 static const int subtype_txq_to_hwq[] = {
940 [WME_AC_BE] = ATH_TXQ_AC_BE,
941 [WME_AC_BK] = ATH_TXQ_AC_BK,
942 [WME_AC_VI] = ATH_TXQ_AC_VI,
943 [WME_AC_VO] = ATH_TXQ_AC_VO,
947 memset(&qi, 0, sizeof(qi));
948 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
949 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
950 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
951 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
952 qi.tqi_physCompBuf = 0;
955 * Enable interrupts only for EOL and DESC conditions.
956 * We mark tx descriptors to receive a DESC interrupt
957 * when a tx queue gets deep; otherwise waiting for the
958 * EOL to reap descriptors. Note that this is done to
959 * reduce interrupt load and this only defers reaping
960 * descriptors, never transmitting frames. Aside from
961 * reducing interrupts this also permits more concurrency.
962 * The only potential downside is if the tx queue backs
963 * up in which case the top half of the kernel may backup
964 * due to a lack of tx descriptors.
966 * The UAPSD queue is an exception, since we take a desc-
967 * based intr on the EOSP frames.
969 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
970 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
971 TXQ_FLAG_TXERRINT_ENABLE;
973 if (qtype == ATH9K_TX_QUEUE_UAPSD)
974 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
976 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
977 TXQ_FLAG_TXDESCINT_ENABLE;
979 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
982 * NB: don't print a message, this happens
983 * normally on parts with too few tx queues
987 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
988 ath_print(common, ATH_DBG_FATAL,
989 "qnum %u out of range, max %u!\n",
990 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
991 ath9k_hw_releasetxqueue(ah, qnum);
994 if (!ATH_TXQ_SETUP(sc, qnum)) {
995 struct ath_txq *txq = &sc->tx.txq[qnum];
997 txq->axq_qnum = qnum;
998 txq->axq_link = NULL;
999 INIT_LIST_HEAD(&txq->axq_q);
1000 INIT_LIST_HEAD(&txq->axq_acq);
1001 spin_lock_init(&txq->axq_lock);
1003 txq->axq_tx_inprogress = false;
1004 sc->tx.txqsetup |= 1<<qnum;
1006 txq->txq_headidx = txq->txq_tailidx = 0;
1007 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1008 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1009 INIT_LIST_HEAD(&txq->txq_fifo_pending);
1011 return &sc->tx.txq[qnum];
1014 int ath_txq_update(struct ath_softc *sc, int qnum,
1015 struct ath9k_tx_queue_info *qinfo)
1017 struct ath_hw *ah = sc->sc_ah;
1019 struct ath9k_tx_queue_info qi;
1021 if (qnum == sc->beacon.beaconq) {
1023 * XXX: for beacon queue, we just save the parameter.
1024 * It will be picked up by ath_beaconq_config when
1027 sc->beacon.beacon_qi = *qinfo;
1031 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1033 ath9k_hw_get_txq_props(ah, qnum, &qi);
1034 qi.tqi_aifs = qinfo->tqi_aifs;
1035 qi.tqi_cwmin = qinfo->tqi_cwmin;
1036 qi.tqi_cwmax = qinfo->tqi_cwmax;
1037 qi.tqi_burstTime = qinfo->tqi_burstTime;
1038 qi.tqi_readyTime = qinfo->tqi_readyTime;
1040 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1041 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1042 "Unable to update hardware queue %u!\n", qnum);
1045 ath9k_hw_resettxqueue(ah, qnum);
1051 int ath_cabq_update(struct ath_softc *sc)
1053 struct ath9k_tx_queue_info qi;
1054 int qnum = sc->beacon.cabq->axq_qnum;
1056 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1058 * Ensure the readytime % is within the bounds.
1060 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1061 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1062 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1063 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1065 qi.tqi_readyTime = (sc->beacon_interval *
1066 sc->config.cabqReadytime) / 100;
1067 ath_txq_update(sc, qnum, &qi);
1073 * Drain a given TX queue (could be Beacon or Data)
1075 * This assumes output has been stopped and
1076 * we do not need to block ath_tx_tasklet.
1078 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1080 struct ath_buf *bf, *lastbf;
1081 struct list_head bf_head;
1082 struct ath_tx_status ts;
1084 memset(&ts, 0, sizeof(ts));
1085 INIT_LIST_HEAD(&bf_head);
1088 spin_lock_bh(&txq->axq_lock);
1090 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1091 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
1092 txq->txq_headidx = txq->txq_tailidx = 0;
1093 spin_unlock_bh(&txq->axq_lock);
1096 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
1097 struct ath_buf, list);
1100 if (list_empty(&txq->axq_q)) {
1101 txq->axq_link = NULL;
1102 spin_unlock_bh(&txq->axq_lock);
1105 bf = list_first_entry(&txq->axq_q, struct ath_buf,
1109 list_del(&bf->list);
1110 spin_unlock_bh(&txq->axq_lock);
1112 ath_tx_return_buffer(sc, bf);
1117 lastbf = bf->bf_lastbf;
1119 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1120 list_cut_position(&bf_head,
1121 &txq->txq_fifo[txq->txq_tailidx],
1123 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
1125 /* remove ath_buf's of the same mpdu from txq */
1126 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1131 spin_unlock_bh(&txq->axq_lock);
1134 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1137 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1140 spin_lock_bh(&txq->axq_lock);
1141 txq->axq_tx_inprogress = false;
1142 spin_unlock_bh(&txq->axq_lock);
1144 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1145 spin_lock_bh(&txq->axq_lock);
1146 while (!list_empty(&txq->txq_fifo_pending)) {
1147 bf = list_first_entry(&txq->txq_fifo_pending,
1148 struct ath_buf, list);
1149 list_cut_position(&bf_head,
1150 &txq->txq_fifo_pending,
1151 &bf->bf_lastbf->list);
1152 spin_unlock_bh(&txq->axq_lock);
1155 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
1158 ath_tx_complete_buf(sc, bf, txq, &bf_head,
1160 spin_lock_bh(&txq->axq_lock);
1162 spin_unlock_bh(&txq->axq_lock);
1165 /* flush any pending frames if aggregation is enabled */
1166 if (sc->sc_flags & SC_OP_TXAGGR) {
1168 spin_lock_bh(&txq->axq_lock);
1169 ath_txq_drain_pending_buffers(sc, txq);
1170 spin_unlock_bh(&txq->axq_lock);
1175 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1177 struct ath_hw *ah = sc->sc_ah;
1178 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1179 struct ath_txq *txq;
1182 if (sc->sc_flags & SC_OP_INVALID)
1185 /* Stop beacon queue */
1186 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1188 /* Stop data queues */
1189 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1190 if (ATH_TXQ_SETUP(sc, i)) {
1191 txq = &sc->tx.txq[i];
1192 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1193 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1200 ath_print(common, ATH_DBG_FATAL,
1201 "Failed to stop TX DMA. Resetting hardware!\n");
1203 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
1205 ath_print(common, ATH_DBG_FATAL,
1206 "Unable to reset hardware; reset status %d\n",
1210 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1211 if (ATH_TXQ_SETUP(sc, i))
1212 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1216 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1218 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1219 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1222 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1224 struct ath_atx_ac *ac;
1225 struct ath_atx_tid *tid;
1227 if (list_empty(&txq->axq_acq))
1230 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1231 list_del(&ac->list);
1235 if (list_empty(&ac->tid_q))
1238 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1239 list_del(&tid->list);
1245 ath_tx_sched_aggr(sc, txq, tid);
1248 * add tid to round-robin queue if more frames
1249 * are pending for the tid
1251 if (!list_empty(&tid->buf_q))
1252 ath_tx_queue_tid(txq, tid);
1255 } while (!list_empty(&ac->tid_q));
1257 if (!list_empty(&ac->tid_q)) {
1260 list_add_tail(&ac->list, &txq->axq_acq);
1270 * Insert a chain of ath_buf (descriptors) on a txq and
1271 * assume the descriptors are already chained together by caller.
1273 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1274 struct list_head *head)
1276 struct ath_hw *ah = sc->sc_ah;
1277 struct ath_common *common = ath9k_hw_common(ah);
1281 * Insert the frame on the outbound list and
1282 * pass it on to the hardware.
1285 if (list_empty(head))
1288 bf = list_first_entry(head, struct ath_buf, list);
1290 ath_print(common, ATH_DBG_QUEUE,
1291 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1293 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1294 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
1295 list_splice_tail_init(head, &txq->txq_fifo_pending);
1298 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
1299 ath_print(common, ATH_DBG_XMIT,
1300 "Initializing tx fifo %d which "
1303 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
1304 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
1305 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1306 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1307 ath_print(common, ATH_DBG_XMIT,
1308 "TXDP[%u] = %llx (%p)\n",
1309 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1311 list_splice_tail_init(head, &txq->axq_q);
1313 if (txq->axq_link == NULL) {
1314 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1315 ath_print(common, ATH_DBG_XMIT,
1316 "TXDP[%u] = %llx (%p)\n",
1317 txq->axq_qnum, ito64(bf->bf_daddr),
1320 *txq->axq_link = bf->bf_daddr;
1321 ath_print(common, ATH_DBG_XMIT,
1322 "link[%u] (%p)=%llx (%p)\n",
1323 txq->axq_qnum, txq->axq_link,
1324 ito64(bf->bf_daddr), bf->bf_desc);
1326 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
1328 ath9k_hw_txstart(ah, txq->axq_qnum);
1333 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1334 struct ath_buf *bf, struct ath_tx_control *txctl)
1336 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1337 struct list_head bf_head;
1339 bf->bf_state.bf_type |= BUF_AMPDU;
1340 TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
1343 * Do not queue to h/w when any of the following conditions is true:
1344 * - there are pending frames in software queue
1345 * - the TID is currently paused for ADDBA/BAR request
1346 * - seqno is not within block-ack window
1347 * - h/w queue depth exceeds low water mark
1349 if (!list_empty(&tid->buf_q) || tid->paused ||
1350 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
1351 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1353 * Add this frame to software queue for scheduling later
1356 list_add_tail(&bf->list, &tid->buf_q);
1357 ath_tx_queue_tid(txctl->txq, tid);
1361 INIT_LIST_HEAD(&bf_head);
1362 list_add(&bf->list, &bf_head);
1364 /* Add sub-frame to BAW */
1366 ath_tx_addto_baw(sc, tid, fi->seqno);
1368 /* Queue to h/w without aggregation */
1370 ath_buf_set_rate(sc, bf, fi->framelen);
1371 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
1374 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1375 struct ath_atx_tid *tid,
1376 struct list_head *bf_head)
1378 struct ath_frame_info *fi;
1381 bf = list_first_entry(bf_head, struct ath_buf, list);
1382 bf->bf_state.bf_type &= ~BUF_AMPDU;
1384 /* update starting sequence number for subsequent ADDBA request */
1386 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1389 fi = get_frame_info(bf->bf_mpdu);
1390 ath_buf_set_rate(sc, bf, fi->framelen);
1391 ath_tx_txqaddbuf(sc, txq, bf_head);
1392 TX_STAT_INC(txq->axq_qnum, queued);
1395 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1397 struct ieee80211_hdr *hdr;
1398 enum ath9k_pkt_type htype;
1401 hdr = (struct ieee80211_hdr *)skb->data;
1402 fc = hdr->frame_control;
1404 if (ieee80211_is_beacon(fc))
1405 htype = ATH9K_PKT_TYPE_BEACON;
1406 else if (ieee80211_is_probe_resp(fc))
1407 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1408 else if (ieee80211_is_atim(fc))
1409 htype = ATH9K_PKT_TYPE_ATIM;
1410 else if (ieee80211_is_pspoll(fc))
1411 htype = ATH9K_PKT_TYPE_PSPOLL;
1413 htype = ATH9K_PKT_TYPE_NORMAL;
1418 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1421 struct ath_wiphy *aphy = hw->priv;
1422 struct ath_softc *sc = aphy->sc;
1423 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1424 struct ieee80211_sta *sta = tx_info->control.sta;
1425 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1426 struct ieee80211_hdr *hdr;
1427 struct ath_frame_info *fi = get_frame_info(skb);
1428 struct ath_node *an;
1429 struct ath_atx_tid *tid;
1430 enum ath9k_key_type keytype;
1434 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1436 hdr = (struct ieee80211_hdr *)skb->data;
1437 if (sta && ieee80211_is_data_qos(hdr->frame_control) &&
1438 conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
1440 an = (struct ath_node *) sta->drv_priv;
1441 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
1444 * Override seqno set by upper layer with the one
1445 * in tx aggregation state.
1447 tid = ATH_AN_2_TID(an, tidno);
1448 seqno = tid->seq_next;
1449 hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
1450 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1453 memset(fi, 0, sizeof(*fi));
1455 fi->keyix = hw_key->hw_key_idx;
1457 fi->keyix = ATH9K_TXKEYIX_INVALID;
1458 fi->keytype = keytype;
1459 fi->framelen = framelen;
1463 static int setup_tx_flags(struct sk_buff *skb)
1465 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1468 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1469 flags |= ATH9K_TXDESC_INTREQ;
1471 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1472 flags |= ATH9K_TXDESC_NOACK;
1474 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1475 flags |= ATH9K_TXDESC_LDPC;
1482 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1483 * width - 0 for 20 MHz, 1 for 40 MHz
1484 * half_gi - to use 4us v/s 3.6 us for symbol time
1486 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1487 int width, int half_gi, bool shortPreamble)
1489 u32 nbits, nsymbits, duration, nsymbols;
1492 /* find number of symbols: PLCP + data */
1493 streams = HT_RC_2_STREAMS(rix);
1494 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1495 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1496 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1499 duration = SYMBOL_TIME(nsymbols);
1501 duration = SYMBOL_TIME_HALFGI(nsymbols);
1503 /* addup duration for legacy/ht training and signal fields */
1504 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1509 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1511 struct ath_hw *ah = sc->sc_ah;
1512 struct ath9k_channel *curchan = ah->curchan;
1513 if ((sc->sc_flags & SC_OP_ENABLE_APM) &&
1514 (curchan->channelFlags & CHANNEL_5GHZ) &&
1515 (chainmask == 0x7) && (rate < 0x90))
1521 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1523 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1524 struct ath9k_11n_rate_series series[4];
1525 struct sk_buff *skb;
1526 struct ieee80211_tx_info *tx_info;
1527 struct ieee80211_tx_rate *rates;
1528 const struct ieee80211_rate *rate;
1529 struct ieee80211_hdr *hdr;
1531 u8 rix = 0, ctsrate = 0;
1534 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1537 tx_info = IEEE80211_SKB_CB(skb);
1538 rates = tx_info->control.rates;
1539 hdr = (struct ieee80211_hdr *)skb->data;
1540 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1543 * We check if Short Preamble is needed for the CTS rate by
1544 * checking the BSS's global flag.
1545 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1547 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1548 ctsrate = rate->hw_value;
1549 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1550 ctsrate |= rate->hw_value_short;
1552 for (i = 0; i < 4; i++) {
1553 bool is_40, is_sgi, is_sp;
1556 if (!rates[i].count || (rates[i].idx < 0))
1560 series[i].Tries = rates[i].count;
1562 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
1563 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
1564 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1565 flags |= ATH9K_TXDESC_RTSENA;
1566 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1567 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1568 flags |= ATH9K_TXDESC_CTSENA;
1571 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1572 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1573 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1574 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1576 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1577 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1578 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1580 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1582 series[i].Rate = rix | 0x80;
1583 series[i].ChSel = ath_txchainmask_reduction(sc,
1584 common->tx_chainmask, series[i].Rate);
1585 series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1586 is_40, is_sgi, is_sp);
1587 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1588 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1593 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1594 !(rate->flags & IEEE80211_RATE_ERP_G))
1595 phy = WLAN_RC_PHY_CCK;
1597 phy = WLAN_RC_PHY_OFDM;
1599 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1600 series[i].Rate = rate->hw_value;
1601 if (rate->hw_value_short) {
1602 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1603 series[i].Rate |= rate->hw_value_short;
1608 if (bf->bf_state.bfs_paprd)
1609 series[i].ChSel = common->tx_chainmask;
1611 series[i].ChSel = ath_txchainmask_reduction(sc,
1612 common->tx_chainmask, series[i].Rate);
1614 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1615 phy, rate->bitrate * 100, len, rix, is_sp);
1618 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1619 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1620 flags &= ~ATH9K_TXDESC_RTSENA;
1622 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1623 if (flags & ATH9K_TXDESC_RTSENA)
1624 flags &= ~ATH9K_TXDESC_CTSENA;
1626 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1627 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1628 bf->bf_lastbf->bf_desc,
1629 !is_pspoll, ctsrate,
1630 0, series, 4, flags);
1632 if (sc->config.ath_aggr_prot && flags)
1633 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1636 static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1637 struct ath_txq *txq,
1638 struct sk_buff *skb)
1640 struct ath_wiphy *aphy = hw->priv;
1641 struct ath_softc *sc = aphy->sc;
1642 struct ath_hw *ah = sc->sc_ah;
1643 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1644 struct ath_frame_info *fi = get_frame_info(skb);
1646 struct ath_desc *ds;
1649 bf = ath_tx_get_buffer(sc);
1651 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1655 ATH_TXBUF_RESET(bf);
1658 bf->bf_flags = setup_tx_flags(skb);
1661 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1662 skb->len, DMA_TO_DEVICE);
1663 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1665 bf->bf_buf_addr = 0;
1666 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1667 "dma_mapping_error() on TX\n");
1668 ath_tx_return_buffer(sc, bf);
1672 frm_type = get_hw_packet_type(skb);
1675 ath9k_hw_set_desc_link(ah, ds, 0);
1677 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1678 fi->keyix, fi->keytype, bf->bf_flags);
1680 ath9k_hw_filltxdesc(ah, ds,
1681 skb->len, /* segment length */
1682 true, /* first segment */
1683 true, /* last segment */
1684 ds, /* first descriptor */
1692 /* FIXME: tx power */
1693 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1694 struct ath_tx_control *txctl)
1696 struct sk_buff *skb = bf->bf_mpdu;
1697 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1698 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1699 struct list_head bf_head;
1700 struct ath_atx_tid *tid;
1703 spin_lock_bh(&txctl->txq->axq_lock);
1705 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && txctl->an) {
1706 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1707 IEEE80211_QOS_CTL_TID_MASK;
1708 tid = ATH_AN_2_TID(txctl->an, tidno);
1710 WARN_ON(tid->ac->txq != txctl->txq);
1712 * Try aggregation if it's a unicast data frame
1713 * and the destination is HT capable.
1715 ath_tx_send_ampdu(sc, tid, bf, txctl);
1717 INIT_LIST_HEAD(&bf_head);
1718 list_add_tail(&bf->list, &bf_head);
1720 bf->bf_state.bfs_ftype = txctl->frame_type;
1721 bf->bf_state.bfs_paprd = txctl->paprd;
1723 if (bf->bf_state.bfs_paprd)
1724 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1725 bf->bf_state.bfs_paprd);
1727 ath_tx_send_normal(sc, txctl->txq, NULL, &bf_head);
1730 spin_unlock_bh(&txctl->txq->axq_lock);
1733 /* Upon failure caller should free skb */
1734 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1735 struct ath_tx_control *txctl)
1737 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1738 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1739 struct ieee80211_sta *sta = info->control.sta;
1740 struct ath_wiphy *aphy = hw->priv;
1741 struct ath_softc *sc = aphy->sc;
1742 struct ath_txq *txq = txctl->txq;
1744 int padpos, padsize;
1745 int frmlen = skb->len + FCS_LEN;
1748 txctl->an = (struct ath_node *)sta->drv_priv;
1749 if (info->control.hw_key)
1750 frmlen += info->control.hw_key->icv_len;
1753 * As a temporary workaround, assign seq# here; this will likely need
1754 * to be cleaned up to work better with Beacon transmission and virtual
1757 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1758 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1759 sc->tx.seq_no += 0x10;
1760 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1761 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1764 /* Add the padding after the header if this is not already done */
1765 padpos = ath9k_cmn_padpos(hdr->frame_control);
1766 padsize = padpos & 3;
1767 if (padsize && skb->len > padpos) {
1768 if (skb_headroom(skb) < padsize)
1771 skb_push(skb, padsize);
1772 memmove(skb->data, skb->data + padsize, padpos);
1775 setup_frame_info(hw, skb, frmlen);
1778 * At this point, the vif, hw_key and sta pointers in the tx control
1779 * info are no longer valid (overwritten by the ath_frame_info data.
1782 bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
1786 q = skb_get_queue_mapping(skb);
1787 spin_lock_bh(&txq->axq_lock);
1788 if (txq == sc->tx.txq_map[q] &&
1789 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1790 ath_mac80211_stop_queue(sc, q);
1793 spin_unlock_bh(&txq->axq_lock);
1795 ath_tx_start_dma(sc, bf, txctl);
1804 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1805 struct ath_wiphy *aphy, int tx_flags, int ftype,
1806 struct ath_txq *txq)
1808 struct ieee80211_hw *hw = sc->hw;
1809 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1810 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1811 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1812 int q, padpos, padsize;
1814 ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1819 if (tx_flags & ATH_TX_BAR)
1820 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1822 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1823 /* Frame was ACKed */
1824 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1827 padpos = ath9k_cmn_padpos(hdr->frame_control);
1828 padsize = padpos & 3;
1829 if (padsize && skb->len>padpos+padsize) {
1831 * Remove MAC header padding before giving the frame back to
1834 memmove(skb->data + padsize, skb->data, padpos);
1835 skb_pull(skb, padsize);
1838 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1839 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1840 ath_print(common, ATH_DBG_PS,
1841 "Going back to sleep after having "
1842 "received TX status (0x%lx)\n",
1843 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1845 PS_WAIT_FOR_PSPOLL_DATA |
1846 PS_WAIT_FOR_TX_ACK));
1849 if (unlikely(ftype))
1850 ath9k_tx_status(hw, skb, ftype);
1852 q = skb_get_queue_mapping(skb);
1853 if (txq == sc->tx.txq_map[q]) {
1854 spin_lock_bh(&txq->axq_lock);
1855 if (WARN_ON(--txq->pending_frames < 0))
1856 txq->pending_frames = 0;
1857 spin_unlock_bh(&txq->axq_lock);
1860 ieee80211_tx_status(hw, skb);
1864 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1865 struct ath_txq *txq, struct list_head *bf_q,
1866 struct ath_tx_status *ts, int txok, int sendbar)
1868 struct sk_buff *skb = bf->bf_mpdu;
1869 unsigned long flags;
1873 tx_flags = ATH_TX_BAR;
1876 tx_flags |= ATH_TX_ERROR;
1878 if (bf_isxretried(bf))
1879 tx_flags |= ATH_TX_XRETRY;
1882 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1883 bf->bf_buf_addr = 0;
1885 if (bf->bf_state.bfs_paprd) {
1886 if (!sc->paprd_pending)
1887 dev_kfree_skb_any(skb);
1889 complete(&sc->paprd_complete);
1891 ath_debug_stat_tx(sc, bf, ts);
1892 ath_tx_complete(sc, skb, bf->aphy, tx_flags,
1893 bf->bf_state.bfs_ftype, txq);
1895 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
1896 * accidentally reference it later.
1901 * Return the list of ath_buf of this mpdu to free queue
1903 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1904 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1905 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1908 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
1909 int nframes, int nbad, int txok, bool update_rc)
1911 struct sk_buff *skb = bf->bf_mpdu;
1912 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1913 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1914 struct ieee80211_hw *hw = bf->aphy->hw;
1915 struct ath_softc *sc = bf->aphy->sc;
1916 struct ath_hw *ah = sc->sc_ah;
1920 tx_info->status.ack_signal = ts->ts_rssi;
1922 tx_rateindex = ts->ts_rateindex;
1923 WARN_ON(tx_rateindex >= hw->max_rates);
1925 if (ts->ts_status & ATH9K_TXERR_FILT)
1926 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1927 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
1928 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
1930 BUG_ON(nbad > nframes);
1932 tx_info->status.ampdu_len = nframes;
1933 tx_info->status.ampdu_ack_len = nframes - nbad;
1936 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
1937 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
1939 * If an underrun error is seen assume it as an excessive
1940 * retry only if max frame trigger level has been reached
1941 * (2 KB for single stream, and 4 KB for dual stream).
1942 * Adjust the long retry as if the frame was tried
1943 * hw->max_rate_tries times to affect how rate control updates
1944 * PER for the failed rate.
1945 * In case of congestion on the bus penalizing this type of
1946 * underruns should help hardware actually transmit new frames
1947 * successfully by eventually preferring slower rates.
1948 * This itself should also alleviate congestion on the bus.
1950 if (ieee80211_is_data(hdr->frame_control) &&
1951 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
1952 ATH9K_TX_DELIM_UNDERRUN)) &&
1953 ah->tx_trig_level >= sc->sc_ah->caps.tx_triglevel_max)
1954 tx_info->status.rates[tx_rateindex].count =
1958 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
1959 tx_info->status.rates[i].count = 0;
1960 tx_info->status.rates[i].idx = -1;
1963 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
1966 static void ath_wake_mac80211_queue(struct ath_softc *sc, int qnum)
1968 struct ath_txq *txq;
1970 txq = sc->tx.txq_map[qnum];
1971 spin_lock_bh(&txq->axq_lock);
1972 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1973 if (ath_mac80211_start_queue(sc, qnum))
1976 spin_unlock_bh(&txq->axq_lock);
1979 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1981 struct ath_hw *ah = sc->sc_ah;
1982 struct ath_common *common = ath9k_hw_common(ah);
1983 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1984 struct list_head bf_head;
1985 struct ath_desc *ds;
1986 struct ath_tx_status ts;
1991 ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1992 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1996 spin_lock_bh(&txq->axq_lock);
1997 if (list_empty(&txq->axq_q)) {
1998 txq->axq_link = NULL;
1999 spin_unlock_bh(&txq->axq_lock);
2002 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2005 * There is a race condition that a BH gets scheduled
2006 * after sw writes TxE and before hw re-load the last
2007 * descriptor to get the newly chained one.
2008 * Software must keep the last DONE descriptor as a
2009 * holding descriptor - software does so by marking
2010 * it with the STALE flag.
2015 if (list_is_last(&bf_held->list, &txq->axq_q)) {
2016 spin_unlock_bh(&txq->axq_lock);
2019 bf = list_entry(bf_held->list.next,
2020 struct ath_buf, list);
2024 lastbf = bf->bf_lastbf;
2025 ds = lastbf->bf_desc;
2027 memset(&ts, 0, sizeof(ts));
2028 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2029 if (status == -EINPROGRESS) {
2030 spin_unlock_bh(&txq->axq_lock);
2035 * Remove ath_buf's of the same transmit unit from txq,
2036 * however leave the last descriptor back as the holding
2037 * descriptor for hw.
2039 lastbf->bf_stale = true;
2040 INIT_LIST_HEAD(&bf_head);
2041 if (!list_is_singular(&lastbf->list))
2042 list_cut_position(&bf_head,
2043 &txq->axq_q, lastbf->list.prev);
2046 txok = !(ts.ts_status & ATH9K_TXERR_MASK);
2047 txq->axq_tx_inprogress = false;
2049 list_del(&bf_held->list);
2050 spin_unlock_bh(&txq->axq_lock);
2053 ath_tx_return_buffer(sc, bf_held);
2055 if (!bf_isampdu(bf)) {
2057 * This frame is sent out as a single frame.
2058 * Use hardware retry status for this frame.
2060 if (ts.ts_status & ATH9K_TXERR_XRETRY)
2061 bf->bf_state.bf_type |= BUF_XRETRY;
2062 ath_tx_rc_status(bf, &ts, 1, txok ? 0 : 1, txok, true);
2065 qnum = skb_get_queue_mapping(bf->bf_mpdu);
2068 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok,
2071 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
2073 if (txq == sc->tx.txq_map[qnum])
2074 ath_wake_mac80211_queue(sc, qnum);
2076 spin_lock_bh(&txq->axq_lock);
2077 if (sc->sc_flags & SC_OP_TXAGGR)
2078 ath_txq_schedule(sc, txq);
2079 spin_unlock_bh(&txq->axq_lock);
2083 static void ath_tx_complete_poll_work(struct work_struct *work)
2085 struct ath_softc *sc = container_of(work, struct ath_softc,
2086 tx_complete_work.work);
2087 struct ath_txq *txq;
2089 bool needreset = false;
2091 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2092 if (ATH_TXQ_SETUP(sc, i)) {
2093 txq = &sc->tx.txq[i];
2094 spin_lock_bh(&txq->axq_lock);
2095 if (txq->axq_depth) {
2096 if (txq->axq_tx_inprogress) {
2098 spin_unlock_bh(&txq->axq_lock);
2101 txq->axq_tx_inprogress = true;
2104 spin_unlock_bh(&txq->axq_lock);
2108 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2109 "tx hung, resetting the chip\n");
2110 ath9k_ps_wakeup(sc);
2111 ath_reset(sc, true);
2112 ath9k_ps_restore(sc);
2115 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2116 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2121 void ath_tx_tasklet(struct ath_softc *sc)
2124 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2126 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2128 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2129 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2130 ath_tx_processq(sc, &sc->tx.txq[i]);
2134 void ath_tx_edma_tasklet(struct ath_softc *sc)
2136 struct ath_tx_status txs;
2137 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2138 struct ath_hw *ah = sc->sc_ah;
2139 struct ath_txq *txq;
2140 struct ath_buf *bf, *lastbf;
2141 struct list_head bf_head;
2147 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
2148 if (status == -EINPROGRESS)
2150 if (status == -EIO) {
2151 ath_print(common, ATH_DBG_XMIT,
2152 "Error processing tx status\n");
2156 /* Skip beacon completions */
2157 if (txs.qid == sc->beacon.beaconq)
2160 txq = &sc->tx.txq[txs.qid];
2162 spin_lock_bh(&txq->axq_lock);
2163 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2164 spin_unlock_bh(&txq->axq_lock);
2168 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2169 struct ath_buf, list);
2170 lastbf = bf->bf_lastbf;
2172 INIT_LIST_HEAD(&bf_head);
2173 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2175 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2177 txq->axq_tx_inprogress = false;
2178 spin_unlock_bh(&txq->axq_lock);
2180 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
2182 if (!bf_isampdu(bf)) {
2183 if (txs.ts_status & ATH9K_TXERR_XRETRY)
2184 bf->bf_state.bf_type |= BUF_XRETRY;
2185 ath_tx_rc_status(bf, &txs, 1, txok ? 0 : 1, txok, true);
2188 qnum = skb_get_queue_mapping(bf->bf_mpdu);
2191 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs,
2194 ath_tx_complete_buf(sc, bf, txq, &bf_head,
2197 if (txq == sc->tx.txq_map[qnum])
2198 ath_wake_mac80211_queue(sc, qnum);
2200 spin_lock_bh(&txq->axq_lock);
2201 if (!list_empty(&txq->txq_fifo_pending)) {
2202 INIT_LIST_HEAD(&bf_head);
2203 bf = list_first_entry(&txq->txq_fifo_pending,
2204 struct ath_buf, list);
2205 list_cut_position(&bf_head, &txq->txq_fifo_pending,
2206 &bf->bf_lastbf->list);
2207 ath_tx_txqaddbuf(sc, txq, &bf_head);
2208 } else if (sc->sc_flags & SC_OP_TXAGGR)
2209 ath_txq_schedule(sc, txq);
2210 spin_unlock_bh(&txq->axq_lock);
2218 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2220 struct ath_descdma *dd = &sc->txsdma;
2221 u8 txs_len = sc->sc_ah->caps.txs_len;
2223 dd->dd_desc_len = size * txs_len;
2224 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2225 &dd->dd_desc_paddr, GFP_KERNEL);
2232 static int ath_tx_edma_init(struct ath_softc *sc)
2236 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2238 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2239 sc->txsdma.dd_desc_paddr,
2240 ATH_TXSTATUS_RING_SIZE);
2245 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2247 struct ath_descdma *dd = &sc->txsdma;
2249 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2253 int ath_tx_init(struct ath_softc *sc, int nbufs)
2255 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2258 spin_lock_init(&sc->tx.txbuflock);
2260 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2263 ath_print(common, ATH_DBG_FATAL,
2264 "Failed to allocate tx descriptors: %d\n", error);
2268 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2269 "beacon", ATH_BCBUF, 1, 1);
2271 ath_print(common, ATH_DBG_FATAL,
2272 "Failed to allocate beacon descriptors: %d\n", error);
2276 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2278 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2279 error = ath_tx_edma_init(sc);
2291 void ath_tx_cleanup(struct ath_softc *sc)
2293 if (sc->beacon.bdma.dd_desc_len != 0)
2294 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2296 if (sc->tx.txdma.dd_desc_len != 0)
2297 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2299 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2300 ath_tx_edma_cleanup(sc);
2303 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2305 struct ath_atx_tid *tid;
2306 struct ath_atx_ac *ac;
2309 for (tidno = 0, tid = &an->tid[tidno];
2310 tidno < WME_NUM_TID;
2314 tid->seq_start = tid->seq_next = 0;
2315 tid->baw_size = WME_MAX_BA;
2316 tid->baw_head = tid->baw_tail = 0;
2318 tid->paused = false;
2319 tid->state &= ~AGGR_CLEANUP;
2320 INIT_LIST_HEAD(&tid->buf_q);
2321 acno = TID_TO_WME_AC(tidno);
2322 tid->ac = &an->ac[acno];
2323 tid->state &= ~AGGR_ADDBA_COMPLETE;
2324 tid->state &= ~AGGR_ADDBA_PROGRESS;
2327 for (acno = 0, ac = &an->ac[acno];
2328 acno < WME_NUM_AC; acno++, ac++) {
2330 ac->txq = sc->tx.txq_map[acno];
2331 INIT_LIST_HEAD(&ac->tid_q);
2335 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2337 struct ath_atx_ac *ac;
2338 struct ath_atx_tid *tid;
2339 struct ath_txq *txq;
2342 for (tidno = 0, tid = &an->tid[tidno];
2343 tidno < WME_NUM_TID; tidno++, tid++) {
2348 spin_lock_bh(&txq->axq_lock);
2351 list_del(&tid->list);
2356 list_del(&ac->list);
2357 tid->ac->sched = false;
2360 ath_tid_drain(sc, txq, tid);
2361 tid->state &= ~AGGR_ADDBA_COMPLETE;
2362 tid->state &= ~AGGR_CLEANUP;
2364 spin_unlock_bh(&txq->axq_lock);