2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
20 #define BITS_PER_BYTE 8
21 #define OFDM_PLCP_BITS 22
22 #define HT_RC_2_MCS(_rc) ((_rc) & 0x1f)
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
35 #define OFDM_SIFS_TIME 16
37 static u32 bits_per_symbol[][2] = {
39 { 26, 54 }, /* 0: BPSK */
40 { 52, 108 }, /* 1: QPSK 1/2 */
41 { 78, 162 }, /* 2: QPSK 3/4 */
42 { 104, 216 }, /* 3: 16-QAM 1/2 */
43 { 156, 324 }, /* 4: 16-QAM 3/4 */
44 { 208, 432 }, /* 5: 64-QAM 2/3 */
45 { 234, 486 }, /* 6: 64-QAM 3/4 */
46 { 260, 540 }, /* 7: 64-QAM 5/6 */
47 { 52, 108 }, /* 8: BPSK */
48 { 104, 216 }, /* 9: QPSK 1/2 */
49 { 156, 324 }, /* 10: QPSK 3/4 */
50 { 208, 432 }, /* 11: 16-QAM 1/2 */
51 { 312, 648 }, /* 12: 16-QAM 3/4 */
52 { 416, 864 }, /* 13: 64-QAM 2/3 */
53 { 468, 972 }, /* 14: 64-QAM 3/4 */
54 { 520, 1080 }, /* 15: 64-QAM 5/6 */
57 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
59 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
60 struct ath_atx_tid *tid,
61 struct list_head *bf_head);
62 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
63 struct ath_txq *txq, struct list_head *bf_q,
64 struct ath_tx_status *ts, int txok, int sendbar);
65 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
66 struct list_head *head);
67 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
68 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
69 struct ath_tx_status *ts, int txok);
70 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
71 int nbad, int txok, bool update_rc);
79 static int ath_max_4ms_framelen[3][16] = {
81 3216, 6434, 9650, 12868, 19304, 25740, 28956, 32180,
82 6430, 12860, 19300, 25736, 38600, 51472, 57890, 64320,
85 6684, 13368, 20052, 26738, 40104, 53476, 60156, 66840,
86 13360, 26720, 40080, 53440, 80160, 106880, 120240, 133600,
89 /* TODO: Only MCS 7 and 15 updated, recalculate the rest */
90 6684, 13368, 20052, 26738, 40104, 53476, 60156, 74200,
91 13360, 26720, 40080, 53440, 80160, 106880, 120240, 148400,
95 /*********************/
96 /* Aggregation logic */
97 /*********************/
99 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
101 struct ath_atx_ac *ac = tid->ac;
110 list_add_tail(&tid->list, &ac->tid_q);
116 list_add_tail(&ac->list, &txq->axq_acq);
119 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
121 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
123 spin_lock_bh(&txq->axq_lock);
125 spin_unlock_bh(&txq->axq_lock);
128 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
130 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
132 BUG_ON(tid->paused <= 0);
133 spin_lock_bh(&txq->axq_lock);
140 if (list_empty(&tid->buf_q))
143 ath_tx_queue_tid(txq, tid);
144 ath_txq_schedule(sc, txq);
146 spin_unlock_bh(&txq->axq_lock);
149 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
151 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
153 struct list_head bf_head;
154 INIT_LIST_HEAD(&bf_head);
156 BUG_ON(tid->paused <= 0);
157 spin_lock_bh(&txq->axq_lock);
161 if (tid->paused > 0) {
162 spin_unlock_bh(&txq->axq_lock);
166 while (!list_empty(&tid->buf_q)) {
167 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
168 BUG_ON(bf_isretried(bf));
169 list_move_tail(&bf->list, &bf_head);
170 ath_tx_send_ht_normal(sc, txq, tid, &bf_head);
173 spin_unlock_bh(&txq->axq_lock);
176 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
181 index = ATH_BA_INDEX(tid->seq_start, seqno);
182 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
184 tid->tx_buf[cindex] = NULL;
186 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
187 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
188 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
192 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
197 if (bf_isretried(bf))
200 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
201 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
203 BUG_ON(tid->tx_buf[cindex] != NULL);
204 tid->tx_buf[cindex] = bf;
206 if (index >= ((tid->baw_tail - tid->baw_head) &
207 (ATH_TID_MAX_BUFS - 1))) {
208 tid->baw_tail = cindex;
209 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
214 * TODO: For frame(s) that are in the retry state, we will reuse the
215 * sequence number(s) without setting the retry bit. The
216 * alternative is to give up on these and BAR the receiver's window
219 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
220 struct ath_atx_tid *tid)
224 struct list_head bf_head;
225 struct ath_tx_status ts;
227 memset(&ts, 0, sizeof(ts));
228 INIT_LIST_HEAD(&bf_head);
231 if (list_empty(&tid->buf_q))
234 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
235 list_move_tail(&bf->list, &bf_head);
237 if (bf_isretried(bf))
238 ath_tx_update_baw(sc, tid, bf->bf_seqno);
240 spin_unlock(&txq->axq_lock);
241 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
242 spin_lock(&txq->axq_lock);
245 tid->seq_next = tid->seq_start;
246 tid->baw_tail = tid->baw_head;
249 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
253 struct ieee80211_hdr *hdr;
255 bf->bf_state.bf_type |= BUF_RETRY;
257 TX_STAT_INC(txq->axq_qnum, a_retries);
260 hdr = (struct ieee80211_hdr *)skb->data;
261 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
264 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
266 struct ath_buf *bf = NULL;
268 spin_lock_bh(&sc->tx.txbuflock);
270 if (unlikely(list_empty(&sc->tx.txbuf))) {
271 spin_unlock_bh(&sc->tx.txbuflock);
275 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
278 spin_unlock_bh(&sc->tx.txbuflock);
283 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
285 spin_lock_bh(&sc->tx.txbuflock);
286 list_add_tail(&bf->list, &sc->tx.txbuf);
287 spin_unlock_bh(&sc->tx.txbuflock);
290 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
294 tbf = ath_tx_get_buffer(sc);
298 ATH_TXBUF_RESET(tbf);
300 tbf->aphy = bf->aphy;
301 tbf->bf_mpdu = bf->bf_mpdu;
302 tbf->bf_buf_addr = bf->bf_buf_addr;
303 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
304 tbf->bf_state = bf->bf_state;
305 tbf->bf_dmacontext = bf->bf_dmacontext;
310 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
311 struct ath_buf *bf, struct list_head *bf_q,
312 struct ath_tx_status *ts, int txok)
314 struct ath_node *an = NULL;
316 struct ieee80211_sta *sta;
317 struct ieee80211_hw *hw;
318 struct ieee80211_hdr *hdr;
319 struct ieee80211_tx_info *tx_info;
320 struct ath_atx_tid *tid = NULL;
321 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
322 struct list_head bf_head, bf_pending;
323 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
324 u32 ba[WME_BA_BMP_SIZE >> 5];
325 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
326 bool rc_update = true;
329 hdr = (struct ieee80211_hdr *)skb->data;
331 tx_info = IEEE80211_SKB_CB(skb);
336 /* XXX: use ieee80211_find_sta! */
337 sta = ieee80211_find_sta_by_hw(hw, hdr->addr1);
343 an = (struct ath_node *)sta->drv_priv;
344 tid = ATH_AN_2_TID(an, bf->bf_tidno);
346 isaggr = bf_isaggr(bf);
347 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
349 if (isaggr && txok) {
350 if (ts->ts_flags & ATH9K_TX_BA) {
351 seq_st = ts->ts_seqnum;
352 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
355 * AR5416 can become deaf/mute when BA
356 * issue happens. Chip needs to be reset.
357 * But AP code may have sychronization issues
358 * when perform internal reset in this routine.
359 * Only enable reset in STA mode for now.
361 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
366 INIT_LIST_HEAD(&bf_pending);
367 INIT_LIST_HEAD(&bf_head);
369 nbad = ath_tx_num_badfrms(sc, bf, ts, txok);
371 txfail = txpending = 0;
372 bf_next = bf->bf_next;
374 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
375 /* transmit completion, subframe is
376 * acked by block ack */
378 } else if (!isaggr && txok) {
379 /* transmit completion */
382 if (!(tid->state & AGGR_CLEANUP) &&
383 !bf_last->bf_tx_aborted) {
384 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
385 ath_tx_set_retry(sc, txq, bf);
388 bf->bf_state.bf_type |= BUF_XRETRY;
395 * cleanup in progress, just fail
396 * the un-acked sub-frames
402 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
405 * Make sure the last desc is reclaimed if it
406 * not a holding desc.
408 if (!bf_last->bf_stale)
409 list_move_tail(&bf->list, &bf_head);
411 INIT_LIST_HEAD(&bf_head);
413 BUG_ON(list_empty(bf_q));
414 list_move_tail(&bf->list, &bf_head);
419 * complete the acked-ones/xretried ones; update
422 spin_lock_bh(&txq->axq_lock);
423 ath_tx_update_baw(sc, tid, bf->bf_seqno);
424 spin_unlock_bh(&txq->axq_lock);
426 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
427 ath_tx_rc_status(bf, ts, nbad, txok, true);
430 ath_tx_rc_status(bf, ts, nbad, txok, false);
433 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
436 /* retry the un-acked ones */
437 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
438 if (bf->bf_next == NULL && bf_last->bf_stale) {
441 tbf = ath_clone_txbuf(sc, bf_last);
443 * Update tx baw and complete the
444 * frame with failed status if we
448 spin_lock_bh(&txq->axq_lock);
449 ath_tx_update_baw(sc, tid,
451 spin_unlock_bh(&txq->axq_lock);
453 bf->bf_state.bf_type |=
455 ath_tx_rc_status(bf, ts, nbad,
457 ath_tx_complete_buf(sc, bf, txq,
463 ath9k_hw_cleartxdesc(sc->sc_ah,
465 list_add_tail(&tbf->list, &bf_head);
468 * Clear descriptor status words for
471 ath9k_hw_cleartxdesc(sc->sc_ah,
477 * Put this buffer to the temporary pending
478 * queue to retain ordering
480 list_splice_tail_init(&bf_head, &bf_pending);
486 if (tid->state & AGGR_CLEANUP) {
487 if (tid->baw_head == tid->baw_tail) {
488 tid->state &= ~AGGR_ADDBA_COMPLETE;
489 tid->state &= ~AGGR_CLEANUP;
491 /* send buffered frames as singles */
492 ath_tx_flush_tid(sc, tid);
498 /* prepend un-acked frames to the beginning of the pending frame queue */
499 if (!list_empty(&bf_pending)) {
500 spin_lock_bh(&txq->axq_lock);
501 list_splice(&bf_pending, &tid->buf_q);
502 ath_tx_queue_tid(txq, tid);
503 spin_unlock_bh(&txq->axq_lock);
509 ath_reset(sc, false);
512 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
513 struct ath_atx_tid *tid)
516 struct ieee80211_tx_info *tx_info;
517 struct ieee80211_tx_rate *rates;
518 u32 max_4ms_framelen, frmlen;
519 u16 aggr_limit, legacy = 0;
523 tx_info = IEEE80211_SKB_CB(skb);
524 rates = tx_info->control.rates;
527 * Find the lowest frame length among the rate series that will have a
528 * 4ms transmit duration.
529 * TODO - TXOP limit needs to be considered.
531 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
533 for (i = 0; i < 4; i++) {
534 if (rates[i].count) {
536 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
541 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
542 modeidx = MCS_HT40_SGI;
543 else if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
546 modeidx = MCS_DEFAULT;
548 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
549 max_4ms_framelen = min(max_4ms_framelen, frmlen);
554 * limit aggregate size by the minimum rate if rate selected is
555 * not a probe rate, if rate selected is a probe rate then
556 * avoid aggregation of this packet.
558 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
561 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
562 aggr_limit = min((max_4ms_framelen * 3) / 8,
563 (u32)ATH_AMPDU_LIMIT_MAX);
565 aggr_limit = min(max_4ms_framelen,
566 (u32)ATH_AMPDU_LIMIT_MAX);
569 * h/w can accept aggregates upto 16 bit lengths (65535).
570 * The IE, however can hold upto 65536, which shows up here
571 * as zero. Ignore 65536 since we are constrained by hw.
573 if (tid->an->maxampdu)
574 aggr_limit = min(aggr_limit, tid->an->maxampdu);
580 * Returns the number of delimiters to be added to
581 * meet the minimum required mpdudensity.
583 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
584 struct ath_buf *bf, u16 frmlen)
586 struct sk_buff *skb = bf->bf_mpdu;
587 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
588 u32 nsymbits, nsymbols;
591 int width, half_gi, ndelim, mindelim;
593 /* Select standard number of delimiters based on frame length alone */
594 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
597 * If encryption enabled, hardware requires some more padding between
599 * TODO - this could be improved to be dependent on the rate.
600 * The hardware can keep up at lower rates, but not higher rates
602 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
603 ndelim += ATH_AGGR_ENCRYPTDELIM;
606 * Convert desired mpdu density from microeconds to bytes based
607 * on highest rate in rate series (i.e. first rate) to determine
608 * required minimum length for subframe. Take into account
609 * whether high rate is 20 or 40Mhz and half or full GI.
611 * If there is no mpdu density restriction, no further calculation
615 if (tid->an->mpdudensity == 0)
618 rix = tx_info->control.rates[0].idx;
619 flags = tx_info->control.rates[0].flags;
620 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
621 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
624 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
626 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
631 nsymbits = bits_per_symbol[rix][width];
632 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
634 if (frmlen < minlen) {
635 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
636 ndelim = max(mindelim, ndelim);
642 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
644 struct ath_atx_tid *tid,
645 struct list_head *bf_q)
647 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
648 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
649 int rl = 0, nframes = 0, ndelim, prev_al = 0;
650 u16 aggr_limit = 0, al = 0, bpad = 0,
651 al_delta, h_baw = tid->baw_size / 2;
652 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
654 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
657 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
659 /* do not step over block-ack window */
660 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
661 status = ATH_AGGR_BAW_CLOSED;
666 aggr_limit = ath_lookup_rate(sc, bf, tid);
670 /* do not exceed aggregation limit */
671 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
674 (aggr_limit < (al + bpad + al_delta + prev_al))) {
675 status = ATH_AGGR_LIMITED;
679 /* do not exceed subframe limit */
680 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
681 status = ATH_AGGR_LIMITED;
686 /* add padding for previous frame to aggregation length */
687 al += bpad + al_delta;
690 * Get the delimiters needed to meet the MPDU
691 * density for this node.
693 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
694 bpad = PADBYTES(al_delta) + (ndelim << 2);
697 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
699 /* link buffers of this frame to the aggregate */
700 ath_tx_addto_baw(sc, tid, bf);
701 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
702 list_move_tail(&bf->list, bf_q);
704 bf_prev->bf_next = bf;
705 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
710 } while (!list_empty(&tid->buf_q));
712 bf_first->bf_al = al;
713 bf_first->bf_nframes = nframes;
719 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
720 struct ath_atx_tid *tid)
723 enum ATH_AGGR_STATUS status;
724 struct list_head bf_q;
727 if (list_empty(&tid->buf_q))
730 INIT_LIST_HEAD(&bf_q);
732 status = ath_tx_form_aggr(sc, txq, tid, &bf_q);
735 * no frames picked up to be aggregated;
736 * block-ack window is not open.
738 if (list_empty(&bf_q))
741 bf = list_first_entry(&bf_q, struct ath_buf, list);
742 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
744 /* if only one frame, send as non-aggregate */
745 if (bf->bf_nframes == 1) {
746 bf->bf_state.bf_type &= ~BUF_AGGR;
747 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
748 ath_buf_set_rate(sc, bf);
749 ath_tx_txqaddbuf(sc, txq, &bf_q);
753 /* setup first desc of aggregate */
754 bf->bf_state.bf_type |= BUF_AGGR;
755 ath_buf_set_rate(sc, bf);
756 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
758 /* anchor last desc of aggregate */
759 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
761 ath_tx_txqaddbuf(sc, txq, &bf_q);
762 TX_STAT_INC(txq->axq_qnum, a_aggr);
764 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
765 status != ATH_AGGR_BAW_CLOSED);
768 void ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
771 struct ath_atx_tid *txtid;
774 an = (struct ath_node *)sta->drv_priv;
775 txtid = ATH_AN_2_TID(an, tid);
776 txtid->state |= AGGR_ADDBA_PROGRESS;
777 ath_tx_pause_tid(sc, txtid);
778 *ssn = txtid->seq_start;
781 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
783 struct ath_node *an = (struct ath_node *)sta->drv_priv;
784 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
785 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
786 struct ath_tx_status ts;
788 struct list_head bf_head;
790 memset(&ts, 0, sizeof(ts));
791 INIT_LIST_HEAD(&bf_head);
793 if (txtid->state & AGGR_CLEANUP)
796 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
797 txtid->state &= ~AGGR_ADDBA_PROGRESS;
801 ath_tx_pause_tid(sc, txtid);
803 /* drop all software retried frames and mark this TID */
804 spin_lock_bh(&txq->axq_lock);
805 while (!list_empty(&txtid->buf_q)) {
806 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
807 if (!bf_isretried(bf)) {
809 * NB: it's based on the assumption that
810 * software retried frame will always stay
811 * at the head of software queue.
815 list_move_tail(&bf->list, &bf_head);
816 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
817 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
819 spin_unlock_bh(&txq->axq_lock);
821 if (txtid->baw_head != txtid->baw_tail) {
822 txtid->state |= AGGR_CLEANUP;
824 txtid->state &= ~AGGR_ADDBA_COMPLETE;
825 ath_tx_flush_tid(sc, txtid);
829 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
831 struct ath_atx_tid *txtid;
834 an = (struct ath_node *)sta->drv_priv;
836 if (sc->sc_flags & SC_OP_TXAGGR) {
837 txtid = ATH_AN_2_TID(an, tid);
839 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
840 txtid->state |= AGGR_ADDBA_COMPLETE;
841 txtid->state &= ~AGGR_ADDBA_PROGRESS;
842 ath_tx_resume_tid(sc, txtid);
846 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
848 struct ath_atx_tid *txtid;
850 if (!(sc->sc_flags & SC_OP_TXAGGR))
853 txtid = ATH_AN_2_TID(an, tidno);
855 if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
860 /********************/
861 /* Queue Management */
862 /********************/
864 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
867 struct ath_atx_ac *ac, *ac_tmp;
868 struct ath_atx_tid *tid, *tid_tmp;
870 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
873 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
874 list_del(&tid->list);
876 ath_tid_drain(sc, txq, tid);
881 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
883 struct ath_hw *ah = sc->sc_ah;
884 struct ath_common *common = ath9k_hw_common(ah);
885 struct ath9k_tx_queue_info qi;
888 memset(&qi, 0, sizeof(qi));
889 qi.tqi_subtype = subtype;
890 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
891 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
892 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
893 qi.tqi_physCompBuf = 0;
896 * Enable interrupts only for EOL and DESC conditions.
897 * We mark tx descriptors to receive a DESC interrupt
898 * when a tx queue gets deep; otherwise waiting for the
899 * EOL to reap descriptors. Note that this is done to
900 * reduce interrupt load and this only defers reaping
901 * descriptors, never transmitting frames. Aside from
902 * reducing interrupts this also permits more concurrency.
903 * The only potential downside is if the tx queue backs
904 * up in which case the top half of the kernel may backup
905 * due to a lack of tx descriptors.
907 * The UAPSD queue is an exception, since we take a desc-
908 * based intr on the EOSP frames.
910 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
911 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
912 TXQ_FLAG_TXERRINT_ENABLE;
914 if (qtype == ATH9K_TX_QUEUE_UAPSD)
915 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
917 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
918 TXQ_FLAG_TXDESCINT_ENABLE;
920 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
923 * NB: don't print a message, this happens
924 * normally on parts with too few tx queues
928 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
929 ath_print(common, ATH_DBG_FATAL,
930 "qnum %u out of range, max %u!\n",
931 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
932 ath9k_hw_releasetxqueue(ah, qnum);
935 if (!ATH_TXQ_SETUP(sc, qnum)) {
936 struct ath_txq *txq = &sc->tx.txq[qnum];
938 txq->axq_qnum = qnum;
939 txq->axq_link = NULL;
940 INIT_LIST_HEAD(&txq->axq_q);
941 INIT_LIST_HEAD(&txq->axq_acq);
942 spin_lock_init(&txq->axq_lock);
944 txq->axq_tx_inprogress = false;
945 sc->tx.txqsetup |= 1<<qnum;
947 txq->txq_headidx = txq->txq_tailidx = 0;
948 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
949 INIT_LIST_HEAD(&txq->txq_fifo[i]);
950 INIT_LIST_HEAD(&txq->txq_fifo_pending);
952 return &sc->tx.txq[qnum];
955 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
960 case ATH9K_TX_QUEUE_DATA:
961 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
962 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
963 "HAL AC %u out of range, max %zu!\n",
964 haltype, ARRAY_SIZE(sc->tx.hwq_map));
967 qnum = sc->tx.hwq_map[haltype];
969 case ATH9K_TX_QUEUE_BEACON:
970 qnum = sc->beacon.beaconq;
972 case ATH9K_TX_QUEUE_CAB:
973 qnum = sc->beacon.cabq->axq_qnum;
981 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
983 struct ath_txq *txq = NULL;
984 u16 skb_queue = skb_get_queue_mapping(skb);
987 qnum = ath_get_hal_qnum(skb_queue, sc);
988 txq = &sc->tx.txq[qnum];
990 spin_lock_bh(&txq->axq_lock);
992 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
993 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_XMIT,
994 "TX queue: %d is full, depth: %d\n",
995 qnum, txq->axq_depth);
996 ath_mac80211_stop_queue(sc, skb_queue);
998 spin_unlock_bh(&txq->axq_lock);
1002 spin_unlock_bh(&txq->axq_lock);
1007 int ath_txq_update(struct ath_softc *sc, int qnum,
1008 struct ath9k_tx_queue_info *qinfo)
1010 struct ath_hw *ah = sc->sc_ah;
1012 struct ath9k_tx_queue_info qi;
1014 if (qnum == sc->beacon.beaconq) {
1016 * XXX: for beacon queue, we just save the parameter.
1017 * It will be picked up by ath_beaconq_config when
1020 sc->beacon.beacon_qi = *qinfo;
1024 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1026 ath9k_hw_get_txq_props(ah, qnum, &qi);
1027 qi.tqi_aifs = qinfo->tqi_aifs;
1028 qi.tqi_cwmin = qinfo->tqi_cwmin;
1029 qi.tqi_cwmax = qinfo->tqi_cwmax;
1030 qi.tqi_burstTime = qinfo->tqi_burstTime;
1031 qi.tqi_readyTime = qinfo->tqi_readyTime;
1033 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1034 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1035 "Unable to update hardware queue %u!\n", qnum);
1038 ath9k_hw_resettxqueue(ah, qnum);
1044 int ath_cabq_update(struct ath_softc *sc)
1046 struct ath9k_tx_queue_info qi;
1047 int qnum = sc->beacon.cabq->axq_qnum;
1049 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1051 * Ensure the readytime % is within the bounds.
1053 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1054 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1055 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1056 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1058 qi.tqi_readyTime = (sc->beacon_interval *
1059 sc->config.cabqReadytime) / 100;
1060 ath_txq_update(sc, qnum, &qi);
1066 * Drain a given TX queue (could be Beacon or Data)
1068 * This assumes output has been stopped and
1069 * we do not need to block ath_tx_tasklet.
1071 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1073 struct ath_buf *bf, *lastbf;
1074 struct list_head bf_head;
1075 struct ath_tx_status ts;
1077 memset(&ts, 0, sizeof(ts));
1078 INIT_LIST_HEAD(&bf_head);
1081 spin_lock_bh(&txq->axq_lock);
1083 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1084 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
1085 txq->txq_headidx = txq->txq_tailidx = 0;
1086 spin_unlock_bh(&txq->axq_lock);
1089 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
1090 struct ath_buf, list);
1093 if (list_empty(&txq->axq_q)) {
1094 txq->axq_link = NULL;
1095 spin_unlock_bh(&txq->axq_lock);
1098 bf = list_first_entry(&txq->axq_q, struct ath_buf,
1102 list_del(&bf->list);
1103 spin_unlock_bh(&txq->axq_lock);
1105 ath_tx_return_buffer(sc, bf);
1110 lastbf = bf->bf_lastbf;
1112 lastbf->bf_tx_aborted = true;
1114 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1115 list_cut_position(&bf_head,
1116 &txq->txq_fifo[txq->txq_tailidx],
1118 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
1120 /* remove ath_buf's of the same mpdu from txq */
1121 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1126 spin_unlock_bh(&txq->axq_lock);
1129 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0);
1131 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1134 spin_lock_bh(&txq->axq_lock);
1135 txq->axq_tx_inprogress = false;
1136 spin_unlock_bh(&txq->axq_lock);
1138 /* flush any pending frames if aggregation is enabled */
1139 if (sc->sc_flags & SC_OP_TXAGGR) {
1141 spin_lock_bh(&txq->axq_lock);
1142 ath_txq_drain_pending_buffers(sc, txq);
1143 spin_unlock_bh(&txq->axq_lock);
1147 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1148 spin_lock_bh(&txq->axq_lock);
1149 while (!list_empty(&txq->txq_fifo_pending)) {
1150 bf = list_first_entry(&txq->txq_fifo_pending,
1151 struct ath_buf, list);
1152 list_cut_position(&bf_head,
1153 &txq->txq_fifo_pending,
1154 &bf->bf_lastbf->list);
1155 spin_unlock_bh(&txq->axq_lock);
1158 ath_tx_complete_aggr(sc, txq, bf, &bf_head,
1161 ath_tx_complete_buf(sc, bf, txq, &bf_head,
1163 spin_lock_bh(&txq->axq_lock);
1165 spin_unlock_bh(&txq->axq_lock);
1169 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1171 struct ath_hw *ah = sc->sc_ah;
1172 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1173 struct ath_txq *txq;
1176 if (sc->sc_flags & SC_OP_INVALID)
1179 /* Stop beacon queue */
1180 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1182 /* Stop data queues */
1183 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1184 if (ATH_TXQ_SETUP(sc, i)) {
1185 txq = &sc->tx.txq[i];
1186 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1187 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1194 ath_print(common, ATH_DBG_FATAL,
1195 "Unable to stop TxDMA. Reset HAL!\n");
1197 spin_lock_bh(&sc->sc_resetlock);
1198 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1200 ath_print(common, ATH_DBG_FATAL,
1201 "Unable to reset hardware; reset status %d\n",
1203 spin_unlock_bh(&sc->sc_resetlock);
1206 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1207 if (ATH_TXQ_SETUP(sc, i))
1208 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1212 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1214 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1215 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1218 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1220 struct ath_atx_ac *ac;
1221 struct ath_atx_tid *tid;
1223 if (list_empty(&txq->axq_acq))
1226 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1227 list_del(&ac->list);
1231 if (list_empty(&ac->tid_q))
1234 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1235 list_del(&tid->list);
1241 ath_tx_sched_aggr(sc, txq, tid);
1244 * add tid to round-robin queue if more frames
1245 * are pending for the tid
1247 if (!list_empty(&tid->buf_q))
1248 ath_tx_queue_tid(txq, tid);
1251 } while (!list_empty(&ac->tid_q));
1253 if (!list_empty(&ac->tid_q)) {
1256 list_add_tail(&ac->list, &txq->axq_acq);
1261 int ath_tx_setup(struct ath_softc *sc, int haltype)
1263 struct ath_txq *txq;
1265 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1266 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1267 "HAL AC %u out of range, max %zu!\n",
1268 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1271 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1273 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1284 * Insert a chain of ath_buf (descriptors) on a txq and
1285 * assume the descriptors are already chained together by caller.
1287 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1288 struct list_head *head)
1290 struct ath_hw *ah = sc->sc_ah;
1291 struct ath_common *common = ath9k_hw_common(ah);
1295 * Insert the frame on the outbound list and
1296 * pass it on to the hardware.
1299 if (list_empty(head))
1302 bf = list_first_entry(head, struct ath_buf, list);
1304 ath_print(common, ATH_DBG_QUEUE,
1305 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1307 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1308 if (txq->axq_depth >= ATH_TXFIFO_DEPTH) {
1309 list_splice_tail_init(head, &txq->txq_fifo_pending);
1312 if (!list_empty(&txq->txq_fifo[txq->txq_headidx]))
1313 ath_print(common, ATH_DBG_XMIT,
1314 "Initializing tx fifo %d which "
1317 INIT_LIST_HEAD(&txq->txq_fifo[txq->txq_headidx]);
1318 list_splice_init(head, &txq->txq_fifo[txq->txq_headidx]);
1319 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1320 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1321 ath_print(common, ATH_DBG_XMIT,
1322 "TXDP[%u] = %llx (%p)\n",
1323 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1325 list_splice_tail_init(head, &txq->axq_q);
1327 if (txq->axq_link == NULL) {
1328 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1329 ath_print(common, ATH_DBG_XMIT,
1330 "TXDP[%u] = %llx (%p)\n",
1331 txq->axq_qnum, ito64(bf->bf_daddr),
1334 *txq->axq_link = bf->bf_daddr;
1335 ath_print(common, ATH_DBG_XMIT,
1336 "link[%u] (%p)=%llx (%p)\n",
1337 txq->axq_qnum, txq->axq_link,
1338 ito64(bf->bf_daddr), bf->bf_desc);
1340 ath9k_hw_get_desc_link(ah, bf->bf_lastbf->bf_desc,
1342 ath9k_hw_txstart(ah, txq->axq_qnum);
1347 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1348 struct list_head *bf_head,
1349 struct ath_tx_control *txctl)
1353 bf = list_first_entry(bf_head, struct ath_buf, list);
1354 bf->bf_state.bf_type |= BUF_AMPDU;
1355 TX_STAT_INC(txctl->txq->axq_qnum, a_queued);
1358 * Do not queue to h/w when any of the following conditions is true:
1359 * - there are pending frames in software queue
1360 * - the TID is currently paused for ADDBA/BAR request
1361 * - seqno is not within block-ack window
1362 * - h/w queue depth exceeds low water mark
1364 if (!list_empty(&tid->buf_q) || tid->paused ||
1365 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1366 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1368 * Add this frame to software queue for scheduling later
1371 list_move_tail(&bf->list, &tid->buf_q);
1372 ath_tx_queue_tid(txctl->txq, tid);
1376 /* Add sub-frame to BAW */
1377 ath_tx_addto_baw(sc, tid, bf);
1379 /* Queue to h/w without aggregation */
1382 ath_buf_set_rate(sc, bf);
1383 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1386 static void ath_tx_send_ht_normal(struct ath_softc *sc, struct ath_txq *txq,
1387 struct ath_atx_tid *tid,
1388 struct list_head *bf_head)
1392 bf = list_first_entry(bf_head, struct ath_buf, list);
1393 bf->bf_state.bf_type &= ~BUF_AMPDU;
1395 /* update starting sequence number for subsequent ADDBA request */
1396 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1400 ath_buf_set_rate(sc, bf);
1401 ath_tx_txqaddbuf(sc, txq, bf_head);
1402 TX_STAT_INC(txq->axq_qnum, queued);
1405 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1406 struct list_head *bf_head)
1410 bf = list_first_entry(bf_head, struct ath_buf, list);
1414 ath_buf_set_rate(sc, bf);
1415 ath_tx_txqaddbuf(sc, txq, bf_head);
1416 TX_STAT_INC(txq->axq_qnum, queued);
1419 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1421 struct ieee80211_hdr *hdr;
1422 enum ath9k_pkt_type htype;
1425 hdr = (struct ieee80211_hdr *)skb->data;
1426 fc = hdr->frame_control;
1428 if (ieee80211_is_beacon(fc))
1429 htype = ATH9K_PKT_TYPE_BEACON;
1430 else if (ieee80211_is_probe_resp(fc))
1431 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1432 else if (ieee80211_is_atim(fc))
1433 htype = ATH9K_PKT_TYPE_ATIM;
1434 else if (ieee80211_is_pspoll(fc))
1435 htype = ATH9K_PKT_TYPE_PSPOLL;
1437 htype = ATH9K_PKT_TYPE_NORMAL;
1442 static int get_hw_crypto_keytype(struct sk_buff *skb)
1444 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1446 if (tx_info->control.hw_key) {
1447 if (tx_info->control.hw_key->alg == ALG_WEP)
1448 return ATH9K_KEY_TYPE_WEP;
1449 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1450 return ATH9K_KEY_TYPE_TKIP;
1451 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1452 return ATH9K_KEY_TYPE_AES;
1455 return ATH9K_KEY_TYPE_CLEAR;
1458 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1461 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1462 struct ieee80211_hdr *hdr;
1463 struct ath_node *an;
1464 struct ath_atx_tid *tid;
1468 if (!tx_info->control.sta)
1471 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1472 hdr = (struct ieee80211_hdr *)skb->data;
1473 fc = hdr->frame_control;
1475 if (ieee80211_is_data_qos(fc)) {
1476 qc = ieee80211_get_qos_ctl(hdr);
1477 bf->bf_tidno = qc[0] & 0xf;
1481 * For HT capable stations, we save tidno for later use.
1482 * We also override seqno set by upper layer with the one
1483 * in tx aggregation state.
1485 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1486 hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
1487 bf->bf_seqno = tid->seq_next;
1488 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1491 static int setup_tx_flags(struct sk_buff *skb, bool use_ldpc)
1493 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1496 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1497 flags |= ATH9K_TXDESC_INTREQ;
1499 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1500 flags |= ATH9K_TXDESC_NOACK;
1503 flags |= ATH9K_TXDESC_LDPC;
1510 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1511 * width - 0 for 20 MHz, 1 for 40 MHz
1512 * half_gi - to use 4us v/s 3.6 us for symbol time
1514 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1515 int width, int half_gi, bool shortPreamble)
1517 u32 nbits, nsymbits, duration, nsymbols;
1518 int streams, pktlen;
1520 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1522 /* find number of symbols: PLCP + data */
1523 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1524 nsymbits = bits_per_symbol[rix][width];
1525 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1528 duration = SYMBOL_TIME(nsymbols);
1530 duration = SYMBOL_TIME_HALFGI(nsymbols);
1532 /* addup duration for legacy/ht training and signal fields */
1533 streams = HT_RC_2_STREAMS(rix);
1534 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1539 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1541 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1542 struct ath9k_11n_rate_series series[4];
1543 struct sk_buff *skb;
1544 struct ieee80211_tx_info *tx_info;
1545 struct ieee80211_tx_rate *rates;
1546 const struct ieee80211_rate *rate;
1547 struct ieee80211_hdr *hdr;
1549 u8 rix = 0, ctsrate = 0;
1552 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1555 tx_info = IEEE80211_SKB_CB(skb);
1556 rates = tx_info->control.rates;
1557 hdr = (struct ieee80211_hdr *)skb->data;
1558 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1561 * We check if Short Preamble is needed for the CTS rate by
1562 * checking the BSS's global flag.
1563 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1565 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1566 ctsrate = rate->hw_value;
1567 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1568 ctsrate |= rate->hw_value_short;
1570 for (i = 0; i < 4; i++) {
1571 bool is_40, is_sgi, is_sp;
1574 if (!rates[i].count || (rates[i].idx < 0))
1578 series[i].Tries = rates[i].count;
1579 series[i].ChSel = common->tx_chainmask;
1581 if ((sc->config.ath_aggr_prot && bf_isaggr(bf)) ||
1582 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)) {
1583 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1584 flags |= ATH9K_TXDESC_RTSENA;
1585 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1586 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1587 flags |= ATH9K_TXDESC_CTSENA;
1590 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1591 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1592 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1593 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1595 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1596 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1597 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1599 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1601 series[i].Rate = rix | 0x80;
1602 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1603 is_40, is_sgi, is_sp);
1608 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1609 !(rate->flags & IEEE80211_RATE_ERP_G))
1610 phy = WLAN_RC_PHY_CCK;
1612 phy = WLAN_RC_PHY_OFDM;
1614 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1615 series[i].Rate = rate->hw_value;
1616 if (rate->hw_value_short) {
1617 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1618 series[i].Rate |= rate->hw_value_short;
1623 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1624 phy, rate->bitrate * 100, bf->bf_frmlen, rix, is_sp);
1627 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1628 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1629 flags &= ~ATH9K_TXDESC_RTSENA;
1631 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1632 if (flags & ATH9K_TXDESC_RTSENA)
1633 flags &= ~ATH9K_TXDESC_CTSENA;
1635 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1636 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1637 bf->bf_lastbf->bf_desc,
1638 !is_pspoll, ctsrate,
1639 0, series, 4, flags);
1641 if (sc->config.ath_aggr_prot && flags)
1642 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1645 static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1646 struct sk_buff *skb,
1647 struct ath_tx_control *txctl)
1649 struct ath_wiphy *aphy = hw->priv;
1650 struct ath_softc *sc = aphy->sc;
1651 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1652 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1655 int padpos, padsize;
1656 bool use_ldpc = false;
1658 tx_info->pad[0] = 0;
1659 switch (txctl->frame_type) {
1660 case ATH9K_IFT_NOT_INTERNAL:
1662 case ATH9K_IFT_PAUSE:
1663 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_PAUSE;
1665 case ATH9K_IFT_UNPAUSE:
1666 tx_info->pad[0] |= ATH_TX_INFO_FRAME_TYPE_INTERNAL;
1669 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1670 fc = hdr->frame_control;
1672 ATH_TXBUF_RESET(bf);
1675 bf->bf_frmlen = skb->len + FCS_LEN;
1676 /* Remove the padding size from bf_frmlen, if any */
1677 padpos = ath9k_cmn_padpos(hdr->frame_control);
1678 padsize = padpos & 3;
1679 if (padsize && skb->len>padpos+padsize) {
1680 bf->bf_frmlen -= padsize;
1683 if (conf_is_ht(&hw->conf)) {
1684 bf->bf_state.bf_type |= BUF_HT;
1685 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1689 bf->bf_flags = setup_tx_flags(skb, use_ldpc);
1691 bf->bf_keytype = get_hw_crypto_keytype(skb);
1692 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1693 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1694 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1696 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1699 if (ieee80211_is_data_qos(fc) && bf_isht(bf) &&
1700 (sc->sc_flags & SC_OP_TXAGGR))
1701 assign_aggr_tid_seqno(skb, bf);
1705 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1706 skb->len, DMA_TO_DEVICE);
1707 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1709 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1710 "dma_mapping_error() on TX\n");
1714 bf->bf_buf_addr = bf->bf_dmacontext;
1716 /* tag if this is a nullfunc frame to enable PS when AP acks it */
1717 if (ieee80211_is_nullfunc(fc) && ieee80211_has_pm(fc)) {
1718 bf->bf_isnullfunc = true;
1719 sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
1721 bf->bf_isnullfunc = false;
1726 /* FIXME: tx power */
1727 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1728 struct ath_tx_control *txctl)
1730 struct sk_buff *skb = bf->bf_mpdu;
1731 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1732 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1733 struct ath_node *an = NULL;
1734 struct list_head bf_head;
1735 struct ath_desc *ds;
1736 struct ath_atx_tid *tid;
1737 struct ath_hw *ah = sc->sc_ah;
1741 frm_type = get_hw_packet_type(skb);
1742 fc = hdr->frame_control;
1744 INIT_LIST_HEAD(&bf_head);
1745 list_add_tail(&bf->list, &bf_head);
1748 ath9k_hw_set_desc_link(ah, ds, 0);
1750 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1751 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1753 ath9k_hw_filltxdesc(ah, ds,
1754 skb->len, /* segment length */
1755 true, /* first segment */
1756 true, /* last segment */
1757 ds, /* first descriptor */
1759 txctl->txq->axq_qnum);
1761 spin_lock_bh(&txctl->txq->axq_lock);
1763 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1764 tx_info->control.sta) {
1765 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1766 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1768 if (!ieee80211_is_data_qos(fc)) {
1769 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1773 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1775 * Try aggregation if it's a unicast data frame
1776 * and the destination is HT capable.
1778 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1781 * Send this frame as regular when ADDBA
1782 * exchange is neither complete nor pending.
1784 ath_tx_send_ht_normal(sc, txctl->txq,
1788 ath_tx_send_normal(sc, txctl->txq, &bf_head);
1792 spin_unlock_bh(&txctl->txq->axq_lock);
1795 /* Upon failure caller should free skb */
1796 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1797 struct ath_tx_control *txctl)
1799 struct ath_wiphy *aphy = hw->priv;
1800 struct ath_softc *sc = aphy->sc;
1801 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1805 bf = ath_tx_get_buffer(sc);
1807 ath_print(common, ATH_DBG_XMIT, "TX buffers are full\n");
1811 r = ath_tx_setup_buffer(hw, bf, skb, txctl);
1813 struct ath_txq *txq = txctl->txq;
1815 ath_print(common, ATH_DBG_FATAL, "TX mem alloc failure\n");
1817 /* upon ath_tx_processq() this TX queue will be resumed, we
1818 * guarantee this will happen by knowing beforehand that
1819 * we will at least have to run TX completionon one buffer
1821 spin_lock_bh(&txq->axq_lock);
1822 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1823 ath_mac80211_stop_queue(sc, skb_get_queue_mapping(skb));
1826 spin_unlock_bh(&txq->axq_lock);
1828 ath_tx_return_buffer(sc, bf);
1833 ath_tx_start_dma(sc, bf, txctl);
1838 void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1840 struct ath_wiphy *aphy = hw->priv;
1841 struct ath_softc *sc = aphy->sc;
1842 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1843 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1844 int padpos, padsize;
1845 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1846 struct ath_tx_control txctl;
1848 memset(&txctl, 0, sizeof(struct ath_tx_control));
1851 * As a temporary workaround, assign seq# here; this will likely need
1852 * to be cleaned up to work better with Beacon transmission and virtual
1855 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1856 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1857 sc->tx.seq_no += 0x10;
1858 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1859 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1862 /* Add the padding after the header if this is not already done */
1863 padpos = ath9k_cmn_padpos(hdr->frame_control);
1864 padsize = padpos & 3;
1865 if (padsize && skb->len>padpos) {
1866 if (skb_headroom(skb) < padsize) {
1867 ath_print(common, ATH_DBG_XMIT,
1868 "TX CABQ padding failed\n");
1869 dev_kfree_skb_any(skb);
1872 skb_push(skb, padsize);
1873 memmove(skb->data, skb->data + padsize, padpos);
1876 txctl.txq = sc->beacon.cabq;
1878 ath_print(common, ATH_DBG_XMIT,
1879 "transmitting CABQ packet, skb: %p\n", skb);
1881 if (ath_tx_start(hw, skb, &txctl) != 0) {
1882 ath_print(common, ATH_DBG_XMIT, "CABQ TX failed\n");
1888 dev_kfree_skb_any(skb);
1895 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1896 struct ath_wiphy *aphy, int tx_flags)
1898 struct ieee80211_hw *hw = sc->hw;
1899 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1900 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1901 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1902 int padpos, padsize;
1904 ath_print(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1909 if (tx_flags & ATH_TX_BAR)
1910 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1912 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1913 /* Frame was ACKed */
1914 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1917 padpos = ath9k_cmn_padpos(hdr->frame_control);
1918 padsize = padpos & 3;
1919 if (padsize && skb->len>padpos+padsize) {
1921 * Remove MAC header padding before giving the frame back to
1924 memmove(skb->data + padsize, skb->data, padpos);
1925 skb_pull(skb, padsize);
1928 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1929 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1930 ath_print(common, ATH_DBG_PS,
1931 "Going back to sleep after having "
1932 "received TX status (0x%lx)\n",
1933 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1935 PS_WAIT_FOR_PSPOLL_DATA |
1936 PS_WAIT_FOR_TX_ACK));
1939 if (unlikely(tx_info->pad[0] & ATH_TX_INFO_FRAME_TYPE_INTERNAL))
1940 ath9k_tx_status(hw, skb);
1942 ieee80211_tx_status(hw, skb);
1945 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1946 struct ath_txq *txq, struct list_head *bf_q,
1947 struct ath_tx_status *ts, int txok, int sendbar)
1949 struct sk_buff *skb = bf->bf_mpdu;
1950 unsigned long flags;
1954 tx_flags = ATH_TX_BAR;
1957 tx_flags |= ATH_TX_ERROR;
1959 if (bf_isxretried(bf))
1960 tx_flags |= ATH_TX_XRETRY;
1963 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1964 ath_tx_complete(sc, skb, bf->aphy, tx_flags);
1965 ath_debug_stat_tx(sc, txq, bf, ts);
1968 * Return the list of ath_buf of this mpdu to free queue
1970 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1971 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1972 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1975 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1976 struct ath_tx_status *ts, int txok)
1979 u32 ba[WME_BA_BMP_SIZE >> 5];
1984 if (bf->bf_tx_aborted)
1987 isaggr = bf_isaggr(bf);
1989 seq_st = ts->ts_seqnum;
1990 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
1994 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1995 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
2004 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_tx_status *ts,
2005 int nbad, int txok, bool update_rc)
2007 struct sk_buff *skb = bf->bf_mpdu;
2008 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2009 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2010 struct ieee80211_hw *hw = bf->aphy->hw;
2014 tx_info->status.ack_signal = ts->ts_rssi;
2016 tx_rateindex = ts->ts_rateindex;
2017 WARN_ON(tx_rateindex >= hw->max_rates);
2019 if (ts->ts_status & ATH9K_TXERR_FILT)
2020 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2021 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc)
2022 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2024 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2025 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
2026 if (ieee80211_is_data(hdr->frame_control)) {
2028 (ATH9K_TX_DATA_UNDERRUN | ATH9K_TX_DELIM_UNDERRUN))
2029 tx_info->pad[0] |= ATH_TX_INFO_UNDERRUN;
2030 if ((ts->ts_status & ATH9K_TXERR_XRETRY) ||
2031 (ts->ts_status & ATH9K_TXERR_FIFO))
2032 tx_info->pad[0] |= ATH_TX_INFO_XRETRY;
2033 tx_info->status.ampdu_len = bf->bf_nframes;
2034 tx_info->status.ampdu_ack_len = bf->bf_nframes - nbad;
2038 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2039 tx_info->status.rates[i].count = 0;
2040 tx_info->status.rates[i].idx = -1;
2043 tx_info->status.rates[tx_rateindex].count = bf->bf_retries + 1;
2046 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
2050 spin_lock_bh(&txq->axq_lock);
2052 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
2053 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
2055 ath_mac80211_start_queue(sc, qnum);
2059 spin_unlock_bh(&txq->axq_lock);
2062 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2064 struct ath_hw *ah = sc->sc_ah;
2065 struct ath_common *common = ath9k_hw_common(ah);
2066 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2067 struct list_head bf_head;
2068 struct ath_desc *ds;
2069 struct ath_tx_status ts;
2073 ath_print(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2074 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2078 spin_lock_bh(&txq->axq_lock);
2079 if (list_empty(&txq->axq_q)) {
2080 txq->axq_link = NULL;
2081 spin_unlock_bh(&txq->axq_lock);
2084 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2087 * There is a race condition that a BH gets scheduled
2088 * after sw writes TxE and before hw re-load the last
2089 * descriptor to get the newly chained one.
2090 * Software must keep the last DONE descriptor as a
2091 * holding descriptor - software does so by marking
2092 * it with the STALE flag.
2097 if (list_is_last(&bf_held->list, &txq->axq_q)) {
2098 spin_unlock_bh(&txq->axq_lock);
2101 bf = list_entry(bf_held->list.next,
2102 struct ath_buf, list);
2106 lastbf = bf->bf_lastbf;
2107 ds = lastbf->bf_desc;
2109 memset(&ts, 0, sizeof(ts));
2110 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2111 if (status == -EINPROGRESS) {
2112 spin_unlock_bh(&txq->axq_lock);
2117 * We now know the nullfunc frame has been ACKed so we
2120 if (bf->bf_isnullfunc &&
2121 (ts.ts_status & ATH9K_TX_ACKED)) {
2122 if ((sc->ps_flags & PS_ENABLED))
2123 ath9k_enable_ps(sc);
2125 sc->ps_flags |= PS_NULLFUNC_COMPLETED;
2129 * Remove ath_buf's of the same transmit unit from txq,
2130 * however leave the last descriptor back as the holding
2131 * descriptor for hw.
2133 lastbf->bf_stale = true;
2134 INIT_LIST_HEAD(&bf_head);
2135 if (!list_is_singular(&lastbf->list))
2136 list_cut_position(&bf_head,
2137 &txq->axq_q, lastbf->list.prev);
2140 txok = !(ts.ts_status & ATH9K_TXERR_MASK);
2141 txq->axq_tx_inprogress = false;
2143 list_del(&bf_held->list);
2144 spin_unlock_bh(&txq->axq_lock);
2147 ath_tx_return_buffer(sc, bf_held);
2149 if (!bf_isampdu(bf)) {
2151 * This frame is sent out as a single frame.
2152 * Use hardware retry status for this frame.
2154 bf->bf_retries = ts.ts_longretry;
2155 if (ts.ts_status & ATH9K_TXERR_XRETRY)
2156 bf->bf_state.bf_type |= BUF_XRETRY;
2157 ath_tx_rc_status(bf, &ts, 0, txok, true);
2161 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, txok);
2163 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, txok, 0);
2165 ath_wake_mac80211_queue(sc, txq);
2167 spin_lock_bh(&txq->axq_lock);
2168 if (sc->sc_flags & SC_OP_TXAGGR)
2169 ath_txq_schedule(sc, txq);
2170 spin_unlock_bh(&txq->axq_lock);
2174 static void ath_tx_complete_poll_work(struct work_struct *work)
2176 struct ath_softc *sc = container_of(work, struct ath_softc,
2177 tx_complete_work.work);
2178 struct ath_txq *txq;
2180 bool needreset = false;
2182 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2183 if (ATH_TXQ_SETUP(sc, i)) {
2184 txq = &sc->tx.txq[i];
2185 spin_lock_bh(&txq->axq_lock);
2186 if (txq->axq_depth) {
2187 if (txq->axq_tx_inprogress) {
2189 spin_unlock_bh(&txq->axq_lock);
2192 txq->axq_tx_inprogress = true;
2195 spin_unlock_bh(&txq->axq_lock);
2199 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2200 "tx hung, resetting the chip\n");
2201 ath9k_ps_wakeup(sc);
2202 ath_reset(sc, false);
2203 ath9k_ps_restore(sc);
2206 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2207 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2212 void ath_tx_tasklet(struct ath_softc *sc)
2215 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2217 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2219 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2220 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2221 ath_tx_processq(sc, &sc->tx.txq[i]);
2225 void ath_tx_edma_tasklet(struct ath_softc *sc)
2227 struct ath_tx_status txs;
2228 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2229 struct ath_hw *ah = sc->sc_ah;
2230 struct ath_txq *txq;
2231 struct ath_buf *bf, *lastbf;
2232 struct list_head bf_head;
2237 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&txs);
2238 if (status == -EINPROGRESS)
2240 if (status == -EIO) {
2241 ath_print(common, ATH_DBG_XMIT,
2242 "Error processing tx status\n");
2246 /* Skip beacon completions */
2247 if (txs.qid == sc->beacon.beaconq)
2250 txq = &sc->tx.txq[txs.qid];
2252 spin_lock_bh(&txq->axq_lock);
2253 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2254 spin_unlock_bh(&txq->axq_lock);
2258 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2259 struct ath_buf, list);
2260 lastbf = bf->bf_lastbf;
2262 INIT_LIST_HEAD(&bf_head);
2263 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2265 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2267 txq->axq_tx_inprogress = false;
2268 spin_unlock_bh(&txq->axq_lock);
2270 txok = !(txs.ts_status & ATH9K_TXERR_MASK);
2272 if (!bf_isampdu(bf)) {
2273 bf->bf_retries = txs.ts_longretry;
2274 if (txs.ts_status & ATH9K_TXERR_XRETRY)
2275 bf->bf_state.bf_type |= BUF_XRETRY;
2276 ath_tx_rc_status(bf, &txs, 0, txok, true);
2280 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &txs, txok);
2282 ath_tx_complete_buf(sc, bf, txq, &bf_head,
2285 spin_lock_bh(&txq->axq_lock);
2286 if (!list_empty(&txq->txq_fifo_pending)) {
2287 INIT_LIST_HEAD(&bf_head);
2288 bf = list_first_entry(&txq->txq_fifo_pending,
2289 struct ath_buf, list);
2290 list_cut_position(&bf_head, &txq->txq_fifo_pending,
2291 &bf->bf_lastbf->list);
2292 ath_tx_txqaddbuf(sc, txq, &bf_head);
2293 } else if (sc->sc_flags & SC_OP_TXAGGR)
2294 ath_txq_schedule(sc, txq);
2295 spin_unlock_bh(&txq->axq_lock);
2303 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2305 struct ath_descdma *dd = &sc->txsdma;
2306 u8 txs_len = sc->sc_ah->caps.txs_len;
2308 dd->dd_desc_len = size * txs_len;
2309 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2310 &dd->dd_desc_paddr, GFP_KERNEL);
2317 static int ath_tx_edma_init(struct ath_softc *sc)
2321 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2323 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2324 sc->txsdma.dd_desc_paddr,
2325 ATH_TXSTATUS_RING_SIZE);
2330 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2332 struct ath_descdma *dd = &sc->txsdma;
2334 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2338 int ath_tx_init(struct ath_softc *sc, int nbufs)
2340 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2343 spin_lock_init(&sc->tx.txbuflock);
2345 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2348 ath_print(common, ATH_DBG_FATAL,
2349 "Failed to allocate tx descriptors: %d\n", error);
2353 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2354 "beacon", ATH_BCBUF, 1, 1);
2356 ath_print(common, ATH_DBG_FATAL,
2357 "Failed to allocate beacon descriptors: %d\n", error);
2361 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2363 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2364 error = ath_tx_edma_init(sc);
2376 void ath_tx_cleanup(struct ath_softc *sc)
2378 if (sc->beacon.bdma.dd_desc_len != 0)
2379 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2381 if (sc->tx.txdma.dd_desc_len != 0)
2382 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2384 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2385 ath_tx_edma_cleanup(sc);
2388 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2390 struct ath_atx_tid *tid;
2391 struct ath_atx_ac *ac;
2394 for (tidno = 0, tid = &an->tid[tidno];
2395 tidno < WME_NUM_TID;
2399 tid->seq_start = tid->seq_next = 0;
2400 tid->baw_size = WME_MAX_BA;
2401 tid->baw_head = tid->baw_tail = 0;
2403 tid->paused = false;
2404 tid->state &= ~AGGR_CLEANUP;
2405 INIT_LIST_HEAD(&tid->buf_q);
2406 acno = TID_TO_WME_AC(tidno);
2407 tid->ac = &an->ac[acno];
2408 tid->state &= ~AGGR_ADDBA_COMPLETE;
2409 tid->state &= ~AGGR_ADDBA_PROGRESS;
2412 for (acno = 0, ac = &an->ac[acno];
2413 acno < WME_NUM_AC; acno++, ac++) {
2415 INIT_LIST_HEAD(&ac->tid_q);
2419 ac->qnum = ath_tx_get_qnum(sc,
2420 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2423 ac->qnum = ath_tx_get_qnum(sc,
2424 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2427 ac->qnum = ath_tx_get_qnum(sc,
2428 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2431 ac->qnum = ath_tx_get_qnum(sc,
2432 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2438 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2441 struct ath_atx_ac *ac, *ac_tmp;
2442 struct ath_atx_tid *tid, *tid_tmp;
2443 struct ath_txq *txq;
2445 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2446 if (ATH_TXQ_SETUP(sc, i)) {
2447 txq = &sc->tx.txq[i];
2449 spin_lock_bh(&txq->axq_lock);
2451 list_for_each_entry_safe(ac,
2452 ac_tmp, &txq->axq_acq, list) {
2453 tid = list_first_entry(&ac->tid_q,
2454 struct ath_atx_tid, list);
2455 if (tid && tid->an != an)
2457 list_del(&ac->list);
2460 list_for_each_entry_safe(tid,
2461 tid_tmp, &ac->tid_q, list) {
2462 list_del(&tid->list);
2464 ath_tid_drain(sc, txq, tid);
2465 tid->state &= ~AGGR_ADDBA_COMPLETE;
2466 tid->state &= ~AGGR_CLEANUP;
2470 spin_unlock_bh(&txq->axq_lock);