2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 static u16 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
51 struct ath_atx_tid *tid,
52 struct list_head *bf_head);
53 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
54 struct ath_txq *txq, struct list_head *bf_q,
55 struct ath_tx_status *ts, int txok, int sendbar);
56 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
57 struct list_head *head, bool internal);
58 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len);
59 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
60 struct ath_tx_status *ts, int nframes, int nbad,
61 int txok, bool update_rc);
62 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
72 static int ath_max_4ms_framelen[4][32] = {
74 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
75 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
76 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
77 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
80 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
81 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
82 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
83 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
86 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
87 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
88 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
89 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
92 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
93 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
94 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
95 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
99 /*********************/
100 /* Aggregation logic */
101 /*********************/
103 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
105 struct ath_atx_ac *ac = tid->ac;
114 list_add_tail(&tid->list, &ac->tid_q);
120 list_add_tail(&ac->list, &txq->axq_acq);
123 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
125 struct ath_txq *txq = tid->ac->txq;
127 WARN_ON(!tid->paused);
129 spin_lock_bh(&txq->axq_lock);
132 if (list_empty(&tid->buf_q))
135 ath_tx_queue_tid(txq, tid);
136 ath_txq_schedule(sc, txq);
138 spin_unlock_bh(&txq->axq_lock);
141 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
143 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
144 BUILD_BUG_ON(sizeof(struct ath_frame_info) >
145 sizeof(tx_info->rate_driver_data));
146 return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
149 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
151 struct ath_txq *txq = tid->ac->txq;
153 struct list_head bf_head;
154 struct ath_tx_status ts;
155 struct ath_frame_info *fi;
157 INIT_LIST_HEAD(&bf_head);
159 memset(&ts, 0, sizeof(ts));
160 spin_lock_bh(&txq->axq_lock);
162 while (!list_empty(&tid->buf_q)) {
163 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
164 list_move_tail(&bf->list, &bf_head);
166 spin_unlock_bh(&txq->axq_lock);
167 fi = get_frame_info(bf->bf_mpdu);
169 ath_tx_update_baw(sc, tid, fi->seqno);
170 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 1);
172 ath_tx_send_normal(sc, txq, NULL, &bf_head);
174 spin_lock_bh(&txq->axq_lock);
177 spin_unlock_bh(&txq->axq_lock);
180 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
185 index = ATH_BA_INDEX(tid->seq_start, seqno);
186 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
188 __clear_bit(cindex, tid->tx_buf);
190 while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
191 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
192 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
196 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
201 index = ATH_BA_INDEX(tid->seq_start, seqno);
202 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
203 __set_bit(cindex, tid->tx_buf);
205 if (index >= ((tid->baw_tail - tid->baw_head) &
206 (ATH_TID_MAX_BUFS - 1))) {
207 tid->baw_tail = cindex;
208 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
213 * TODO: For frame(s) that are in the retry state, we will reuse the
214 * sequence number(s) without setting the retry bit. The
215 * alternative is to give up on these and BAR the receiver's window
218 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
219 struct ath_atx_tid *tid)
223 struct list_head bf_head;
224 struct ath_tx_status ts;
225 struct ath_frame_info *fi;
227 memset(&ts, 0, sizeof(ts));
228 INIT_LIST_HEAD(&bf_head);
231 if (list_empty(&tid->buf_q))
234 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
235 list_move_tail(&bf->list, &bf_head);
237 fi = get_frame_info(bf->bf_mpdu);
239 ath_tx_update_baw(sc, tid, fi->seqno);
241 spin_unlock(&txq->axq_lock);
242 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
243 spin_lock(&txq->axq_lock);
246 tid->seq_next = tid->seq_start;
247 tid->baw_tail = tid->baw_head;
250 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
253 struct ath_frame_info *fi = get_frame_info(skb);
254 struct ieee80211_hdr *hdr;
256 TX_STAT_INC(txq->axq_qnum, a_retries);
257 if (fi->retries++ > 0)
260 hdr = (struct ieee80211_hdr *)skb->data;
261 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
264 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
266 struct ath_buf *bf = NULL;
268 spin_lock_bh(&sc->tx.txbuflock);
270 if (unlikely(list_empty(&sc->tx.txbuf))) {
271 spin_unlock_bh(&sc->tx.txbuflock);
275 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
278 spin_unlock_bh(&sc->tx.txbuflock);
283 static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
285 spin_lock_bh(&sc->tx.txbuflock);
286 list_add_tail(&bf->list, &sc->tx.txbuf);
287 spin_unlock_bh(&sc->tx.txbuflock);
290 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
294 tbf = ath_tx_get_buffer(sc);
298 ATH_TXBUF_RESET(tbf);
300 tbf->bf_mpdu = bf->bf_mpdu;
301 tbf->bf_buf_addr = bf->bf_buf_addr;
302 memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
303 tbf->bf_state = bf->bf_state;
308 static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
309 struct ath_tx_status *ts, int txok,
310 int *nframes, int *nbad)
312 struct ath_frame_info *fi;
314 u32 ba[WME_BA_BMP_SIZE >> 5];
321 isaggr = bf_isaggr(bf);
323 seq_st = ts->ts_seqnum;
324 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
328 fi = get_frame_info(bf->bf_mpdu);
329 ba_index = ATH_BA_INDEX(seq_st, fi->seqno);
332 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
340 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
341 struct ath_buf *bf, struct list_head *bf_q,
342 struct ath_tx_status *ts, int txok, bool retry)
344 struct ath_node *an = NULL;
346 struct ieee80211_sta *sta;
347 struct ieee80211_hw *hw = sc->hw;
348 struct ieee80211_hdr *hdr;
349 struct ieee80211_tx_info *tx_info;
350 struct ath_atx_tid *tid = NULL;
351 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
352 struct list_head bf_head, bf_pending;
353 u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0;
354 u32 ba[WME_BA_BMP_SIZE >> 5];
355 int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
356 bool rc_update = true;
357 struct ieee80211_tx_rate rates[4];
358 struct ath_frame_info *fi;
364 hdr = (struct ieee80211_hdr *)skb->data;
366 tx_info = IEEE80211_SKB_CB(skb);
368 memcpy(rates, tx_info->control.rates, sizeof(rates));
372 sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
376 INIT_LIST_HEAD(&bf_head);
378 bf_next = bf->bf_next;
380 bf->bf_state.bf_type |= BUF_XRETRY;
381 if (!bf->bf_stale || bf_next != NULL)
382 list_move_tail(&bf->list, &bf_head);
384 ath_tx_rc_status(sc, bf, ts, 1, 1, 0, false);
385 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
393 an = (struct ath_node *)sta->drv_priv;
394 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
395 tid = ATH_AN_2_TID(an, tidno);
398 * The hardware occasionally sends a tx status for the wrong TID.
399 * In this case, the BA status cannot be considered valid and all
400 * subframes need to be retransmitted
402 if (tidno != ts->tid)
405 isaggr = bf_isaggr(bf);
406 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
408 if (isaggr && txok) {
409 if (ts->ts_flags & ATH9K_TX_BA) {
410 seq_st = ts->ts_seqnum;
411 memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
414 * AR5416 can become deaf/mute when BA
415 * issue happens. Chip needs to be reset.
416 * But AP code may have sychronization issues
417 * when perform internal reset in this routine.
418 * Only enable reset in STA mode for now.
420 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
425 INIT_LIST_HEAD(&bf_pending);
426 INIT_LIST_HEAD(&bf_head);
428 ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
430 txfail = txpending = sendbar = 0;
431 bf_next = bf->bf_next;
434 tx_info = IEEE80211_SKB_CB(skb);
435 fi = get_frame_info(skb);
437 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, fi->seqno))) {
438 /* transmit completion, subframe is
439 * acked by block ack */
441 } else if (!isaggr && txok) {
442 /* transmit completion */
445 if ((tid->state & AGGR_CLEANUP) || !retry) {
447 * cleanup in progress, just fail
448 * the un-acked sub-frames
451 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
452 if (!(ts->ts_status & ATH9K_TXERR_FILT) ||
454 ath_tx_set_retry(sc, txq, bf->bf_mpdu);
459 bf->bf_state.bf_type |= BUF_XRETRY;
467 * Make sure the last desc is reclaimed if it
468 * not a holding desc.
470 if (!bf_last->bf_stale || bf_next != NULL)
471 list_move_tail(&bf->list, &bf_head);
473 INIT_LIST_HEAD(&bf_head);
475 if (!txpending || (tid->state & AGGR_CLEANUP)) {
477 * complete the acked-ones/xretried ones; update
480 spin_lock_bh(&txq->axq_lock);
481 ath_tx_update_baw(sc, tid, fi->seqno);
482 spin_unlock_bh(&txq->axq_lock);
484 if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
485 memcpy(tx_info->control.rates, rates, sizeof(rates));
486 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, true);
489 ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok, false);
492 ath_tx_complete_buf(sc, bf, txq, &bf_head, ts,
495 /* retry the un-acked ones */
496 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, false);
497 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)) {
498 if (bf->bf_next == NULL && bf_last->bf_stale) {
501 tbf = ath_clone_txbuf(sc, bf_last);
503 * Update tx baw and complete the
504 * frame with failed status if we
508 spin_lock_bh(&txq->axq_lock);
509 ath_tx_update_baw(sc, tid, fi->seqno);
510 spin_unlock_bh(&txq->axq_lock);
512 bf->bf_state.bf_type |=
514 ath_tx_rc_status(sc, bf, ts, nframes,
516 ath_tx_complete_buf(sc, bf, txq,
522 ath9k_hw_cleartxdesc(sc->sc_ah,
524 list_add_tail(&tbf->list, &bf_head);
527 * Clear descriptor status words for
530 ath9k_hw_cleartxdesc(sc->sc_ah,
536 * Put this buffer to the temporary pending
537 * queue to retain ordering
539 list_splice_tail_init(&bf_head, &bf_pending);
545 /* prepend un-acked frames to the beginning of the pending frame queue */
546 if (!list_empty(&bf_pending)) {
548 ieee80211_sta_set_tim(sta);
550 spin_lock_bh(&txq->axq_lock);
552 tid->ac->clear_ps_filter = true;
553 list_splice(&bf_pending, &tid->buf_q);
555 ath_tx_queue_tid(txq, tid);
556 spin_unlock_bh(&txq->axq_lock);
559 if (tid->state & AGGR_CLEANUP) {
560 ath_tx_flush_tid(sc, tid);
562 if (tid->baw_head == tid->baw_tail) {
563 tid->state &= ~AGGR_ADDBA_COMPLETE;
564 tid->state &= ~AGGR_CLEANUP;
571 ath_reset(sc, false);
574 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
575 struct ath_atx_tid *tid)
578 struct ieee80211_tx_info *tx_info;
579 struct ieee80211_tx_rate *rates;
580 u32 max_4ms_framelen, frmlen;
581 u16 aggr_limit, legacy = 0;
585 tx_info = IEEE80211_SKB_CB(skb);
586 rates = tx_info->control.rates;
589 * Find the lowest frame length among the rate series that will have a
590 * 4ms transmit duration.
591 * TODO - TXOP limit needs to be considered.
593 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
595 for (i = 0; i < 4; i++) {
596 if (rates[i].count) {
598 if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
603 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
608 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
611 frmlen = ath_max_4ms_framelen[modeidx][rates[i].idx];
612 max_4ms_framelen = min(max_4ms_framelen, frmlen);
617 * limit aggregate size by the minimum rate if rate selected is
618 * not a probe rate, if rate selected is a probe rate then
619 * avoid aggregation of this packet.
621 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
624 if (sc->sc_flags & SC_OP_BT_PRIORITY_DETECTED)
625 aggr_limit = min((max_4ms_framelen * 3) / 8,
626 (u32)ATH_AMPDU_LIMIT_MAX);
628 aggr_limit = min(max_4ms_framelen,
629 (u32)ATH_AMPDU_LIMIT_MAX);
632 * h/w can accept aggregates up to 16 bit lengths (65535).
633 * The IE, however can hold up to 65536, which shows up here
634 * as zero. Ignore 65536 since we are constrained by hw.
636 if (tid->an->maxampdu)
637 aggr_limit = min(aggr_limit, tid->an->maxampdu);
643 * Returns the number of delimiters to be added to
644 * meet the minimum required mpdudensity.
646 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
647 struct ath_buf *bf, u16 frmlen,
650 #define FIRST_DESC_NDELIMS 60
651 struct sk_buff *skb = bf->bf_mpdu;
652 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
653 u32 nsymbits, nsymbols;
656 int width, streams, half_gi, ndelim, mindelim;
657 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
659 /* Select standard number of delimiters based on frame length alone */
660 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
663 * If encryption enabled, hardware requires some more padding between
665 * TODO - this could be improved to be dependent on the rate.
666 * The hardware can keep up at lower rates, but not higher rates
668 if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
669 !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
670 ndelim += ATH_AGGR_ENCRYPTDELIM;
673 * Add delimiter when using RTS/CTS with aggregation
674 * and non enterprise AR9003 card
677 ndelim = max(ndelim, FIRST_DESC_NDELIMS);
680 * Convert desired mpdu density from microeconds to bytes based
681 * on highest rate in rate series (i.e. first rate) to determine
682 * required minimum length for subframe. Take into account
683 * whether high rate is 20 or 40Mhz and half or full GI.
685 * If there is no mpdu density restriction, no further calculation
689 if (tid->an->mpdudensity == 0)
692 rix = tx_info->control.rates[0].idx;
693 flags = tx_info->control.rates[0].flags;
694 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
695 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
698 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
700 nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
705 streams = HT_RC_2_STREAMS(rix);
706 nsymbits = bits_per_symbol[rix % 8][width] * streams;
707 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
709 if (frmlen < minlen) {
710 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
711 ndelim = max(mindelim, ndelim);
717 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
719 struct ath_atx_tid *tid,
720 struct list_head *bf_q,
723 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
724 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
725 int rl = 0, nframes = 0, ndelim, prev_al = 0;
726 u16 aggr_limit = 0, al = 0, bpad = 0,
727 al_delta, h_baw = tid->baw_size / 2;
728 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
729 struct ieee80211_tx_info *tx_info;
730 struct ath_frame_info *fi;
732 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
735 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
736 fi = get_frame_info(bf->bf_mpdu);
738 /* do not step over block-ack window */
739 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno)) {
740 status = ATH_AGGR_BAW_CLOSED;
745 aggr_limit = ath_lookup_rate(sc, bf, tid);
749 /* do not exceed aggregation limit */
750 al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
753 (aggr_limit < (al + bpad + al_delta + prev_al))) {
754 status = ATH_AGGR_LIMITED;
758 tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
759 if (nframes && ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
760 !(tx_info->control.rates[0].flags & IEEE80211_TX_RC_MCS)))
763 /* do not exceed subframe limit */
764 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
765 status = ATH_AGGR_LIMITED;
769 /* add padding for previous frame to aggregation length */
770 al += bpad + al_delta;
773 * Get the delimiters needed to meet the MPDU
774 * density for this node.
776 ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
778 bpad = PADBYTES(al_delta) + (ndelim << 2);
782 ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, 0);
784 /* link buffers of this frame to the aggregate */
786 ath_tx_addto_baw(sc, tid, fi->seqno);
787 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
788 list_move_tail(&bf->list, bf_q);
790 bf_prev->bf_next = bf;
791 ath9k_hw_set_desc_link(sc->sc_ah, bf_prev->bf_desc,
796 } while (!list_empty(&tid->buf_q));
804 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
805 struct ath_atx_tid *tid)
808 enum ATH_AGGR_STATUS status;
809 struct ath_frame_info *fi;
810 struct list_head bf_q;
814 if (list_empty(&tid->buf_q))
817 INIT_LIST_HEAD(&bf_q);
819 status = ath_tx_form_aggr(sc, txq, tid, &bf_q, &aggr_len);
822 * no frames picked up to be aggregated;
823 * block-ack window is not open.
825 if (list_empty(&bf_q))
828 bf = list_first_entry(&bf_q, struct ath_buf, list);
829 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
831 if (tid->ac->clear_ps_filter) {
832 tid->ac->clear_ps_filter = false;
833 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
836 /* if only one frame, send as non-aggregate */
837 if (bf == bf->bf_lastbf) {
838 fi = get_frame_info(bf->bf_mpdu);
840 bf->bf_state.bf_type &= ~BUF_AGGR;
841 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
842 ath_buf_set_rate(sc, bf, fi->framelen);
843 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
847 /* setup first desc of aggregate */
848 bf->bf_state.bf_type |= BUF_AGGR;
849 ath_buf_set_rate(sc, bf, aggr_len);
850 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, aggr_len);
852 /* anchor last desc of aggregate */
853 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
855 ath_tx_txqaddbuf(sc, txq, &bf_q, false);
856 TX_STAT_INC(txq->axq_qnum, a_aggr);
858 } while (txq->axq_ampdu_depth < ATH_AGGR_MIN_QDEPTH &&
859 status != ATH_AGGR_BAW_CLOSED);
862 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
865 struct ath_atx_tid *txtid;
868 an = (struct ath_node *)sta->drv_priv;
869 txtid = ATH_AN_2_TID(an, tid);
871 if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
874 txtid->state |= AGGR_ADDBA_PROGRESS;
875 txtid->paused = true;
876 *ssn = txtid->seq_start = txtid->seq_next;
878 memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
879 txtid->baw_head = txtid->baw_tail = 0;
884 void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
886 struct ath_node *an = (struct ath_node *)sta->drv_priv;
887 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
888 struct ath_txq *txq = txtid->ac->txq;
890 if (txtid->state & AGGR_CLEANUP)
893 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
894 txtid->state &= ~AGGR_ADDBA_PROGRESS;
898 spin_lock_bh(&txq->axq_lock);
899 txtid->paused = true;
902 * If frames are still being transmitted for this TID, they will be
903 * cleaned up during tx completion. To prevent race conditions, this
904 * TID can only be reused after all in-progress subframes have been
907 if (txtid->baw_head != txtid->baw_tail)
908 txtid->state |= AGGR_CLEANUP;
910 txtid->state &= ~AGGR_ADDBA_COMPLETE;
911 spin_unlock_bh(&txq->axq_lock);
913 ath_tx_flush_tid(sc, txtid);
916 bool ath_tx_aggr_sleep(struct ath_softc *sc, struct ath_node *an)
918 struct ath_atx_tid *tid;
919 struct ath_atx_ac *ac;
921 bool buffered = false;
924 for (tidno = 0, tid = &an->tid[tidno];
925 tidno < WME_NUM_TID; tidno++, tid++) {
933 spin_lock_bh(&txq->axq_lock);
935 if (!list_empty(&tid->buf_q))
939 list_del(&tid->list);
946 spin_unlock_bh(&txq->axq_lock);
952 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
954 struct ath_atx_tid *tid;
955 struct ath_atx_ac *ac;
959 for (tidno = 0, tid = &an->tid[tidno];
960 tidno < WME_NUM_TID; tidno++, tid++) {
965 spin_lock_bh(&txq->axq_lock);
966 ac->clear_ps_filter = true;
968 if (!list_empty(&tid->buf_q) && !tid->paused) {
969 ath_tx_queue_tid(txq, tid);
970 ath_txq_schedule(sc, txq);
973 spin_unlock_bh(&txq->axq_lock);
977 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
979 struct ath_atx_tid *txtid;
982 an = (struct ath_node *)sta->drv_priv;
984 if (sc->sc_flags & SC_OP_TXAGGR) {
985 txtid = ATH_AN_2_TID(an, tid);
987 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
988 txtid->state |= AGGR_ADDBA_COMPLETE;
989 txtid->state &= ~AGGR_ADDBA_PROGRESS;
990 ath_tx_resume_tid(sc, txtid);
994 /********************/
995 /* Queue Management */
996 /********************/
998 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1001 struct ath_atx_ac *ac, *ac_tmp;
1002 struct ath_atx_tid *tid, *tid_tmp;
1004 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1005 list_del(&ac->list);
1007 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1008 list_del(&tid->list);
1010 ath_tid_drain(sc, txq, tid);
1015 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1017 struct ath_hw *ah = sc->sc_ah;
1018 struct ath_common *common = ath9k_hw_common(ah);
1019 struct ath9k_tx_queue_info qi;
1020 static const int subtype_txq_to_hwq[] = {
1021 [WME_AC_BE] = ATH_TXQ_AC_BE,
1022 [WME_AC_BK] = ATH_TXQ_AC_BK,
1023 [WME_AC_VI] = ATH_TXQ_AC_VI,
1024 [WME_AC_VO] = ATH_TXQ_AC_VO,
1028 memset(&qi, 0, sizeof(qi));
1029 qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1030 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1031 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1032 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1033 qi.tqi_physCompBuf = 0;
1036 * Enable interrupts only for EOL and DESC conditions.
1037 * We mark tx descriptors to receive a DESC interrupt
1038 * when a tx queue gets deep; otherwise waiting for the
1039 * EOL to reap descriptors. Note that this is done to
1040 * reduce interrupt load and this only defers reaping
1041 * descriptors, never transmitting frames. Aside from
1042 * reducing interrupts this also permits more concurrency.
1043 * The only potential downside is if the tx queue backs
1044 * up in which case the top half of the kernel may backup
1045 * due to a lack of tx descriptors.
1047 * The UAPSD queue is an exception, since we take a desc-
1048 * based intr on the EOSP frames.
1050 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1051 qi.tqi_qflags = TXQ_FLAG_TXOKINT_ENABLE |
1052 TXQ_FLAG_TXERRINT_ENABLE;
1054 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1055 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1057 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1058 TXQ_FLAG_TXDESCINT_ENABLE;
1060 axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1061 if (axq_qnum == -1) {
1063 * NB: don't print a message, this happens
1064 * normally on parts with too few tx queues
1068 if (axq_qnum >= ARRAY_SIZE(sc->tx.txq)) {
1069 ath_err(common, "qnum %u out of range, max %zu!\n",
1070 axq_qnum, ARRAY_SIZE(sc->tx.txq));
1071 ath9k_hw_releasetxqueue(ah, axq_qnum);
1074 if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1075 struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1077 txq->axq_qnum = axq_qnum;
1078 txq->mac80211_qnum = -1;
1079 txq->axq_link = NULL;
1080 INIT_LIST_HEAD(&txq->axq_q);
1081 INIT_LIST_HEAD(&txq->axq_acq);
1082 spin_lock_init(&txq->axq_lock);
1084 txq->axq_ampdu_depth = 0;
1085 txq->axq_tx_inprogress = false;
1086 sc->tx.txqsetup |= 1<<axq_qnum;
1088 txq->txq_headidx = txq->txq_tailidx = 0;
1089 for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1090 INIT_LIST_HEAD(&txq->txq_fifo[i]);
1092 return &sc->tx.txq[axq_qnum];
1095 int ath_txq_update(struct ath_softc *sc, int qnum,
1096 struct ath9k_tx_queue_info *qinfo)
1098 struct ath_hw *ah = sc->sc_ah;
1100 struct ath9k_tx_queue_info qi;
1102 if (qnum == sc->beacon.beaconq) {
1104 * XXX: for beacon queue, we just save the parameter.
1105 * It will be picked up by ath_beaconq_config when
1108 sc->beacon.beacon_qi = *qinfo;
1112 BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1114 ath9k_hw_get_txq_props(ah, qnum, &qi);
1115 qi.tqi_aifs = qinfo->tqi_aifs;
1116 qi.tqi_cwmin = qinfo->tqi_cwmin;
1117 qi.tqi_cwmax = qinfo->tqi_cwmax;
1118 qi.tqi_burstTime = qinfo->tqi_burstTime;
1119 qi.tqi_readyTime = qinfo->tqi_readyTime;
1121 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1122 ath_err(ath9k_hw_common(sc->sc_ah),
1123 "Unable to update hardware queue %u!\n", qnum);
1126 ath9k_hw_resettxqueue(ah, qnum);
1132 int ath_cabq_update(struct ath_softc *sc)
1134 struct ath9k_tx_queue_info qi;
1135 struct ath_beacon_config *cur_conf = &sc->cur_beacon_conf;
1136 int qnum = sc->beacon.cabq->axq_qnum;
1138 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1140 * Ensure the readytime % is within the bounds.
1142 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
1143 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
1144 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
1145 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
1147 qi.tqi_readyTime = (cur_conf->beacon_interval *
1148 sc->config.cabqReadytime) / 100;
1149 ath_txq_update(sc, qnum, &qi);
1154 static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
1156 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
1157 return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1160 static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1161 struct list_head *list, bool retry_tx)
1162 __releases(txq->axq_lock)
1163 __acquires(txq->axq_lock)
1165 struct ath_buf *bf, *lastbf;
1166 struct list_head bf_head;
1167 struct ath_tx_status ts;
1169 memset(&ts, 0, sizeof(ts));
1170 INIT_LIST_HEAD(&bf_head);
1172 while (!list_empty(list)) {
1173 bf = list_first_entry(list, struct ath_buf, list);
1176 list_del(&bf->list);
1178 ath_tx_return_buffer(sc, bf);
1182 lastbf = bf->bf_lastbf;
1183 list_cut_position(&bf_head, list, &lastbf->list);
1186 if (bf_is_ampdu_not_probing(bf))
1187 txq->axq_ampdu_depth--;
1189 spin_unlock_bh(&txq->axq_lock);
1191 ath_tx_complete_aggr(sc, txq, bf, &bf_head, &ts, 0,
1194 ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0, 0);
1195 spin_lock_bh(&txq->axq_lock);
1200 * Drain a given TX queue (could be Beacon or Data)
1202 * This assumes output has been stopped and
1203 * we do not need to block ath_tx_tasklet.
1205 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
1207 spin_lock_bh(&txq->axq_lock);
1208 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1209 int idx = txq->txq_tailidx;
1211 while (!list_empty(&txq->txq_fifo[idx])) {
1212 ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx],
1215 INCR(idx, ATH_TXFIFO_DEPTH);
1217 txq->txq_tailidx = idx;
1220 txq->axq_link = NULL;
1221 txq->axq_tx_inprogress = false;
1222 ath_drain_txq_list(sc, txq, &txq->axq_q, retry_tx);
1224 /* flush any pending frames if aggregation is enabled */
1225 if ((sc->sc_flags & SC_OP_TXAGGR) && !retry_tx)
1226 ath_txq_drain_pending_buffers(sc, txq);
1228 spin_unlock_bh(&txq->axq_lock);
1231 bool ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1233 struct ath_hw *ah = sc->sc_ah;
1234 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1235 struct ath_txq *txq;
1238 if (sc->sc_flags & SC_OP_INVALID)
1241 ath9k_hw_abort_tx_dma(ah);
1243 /* Check if any queue remains active */
1244 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1245 if (!ATH_TXQ_SETUP(sc, i))
1248 npend += ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum);
1252 ath_err(common, "Failed to stop TX DMA!\n");
1254 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1255 if (!ATH_TXQ_SETUP(sc, i))
1259 * The caller will resume queues with ieee80211_wake_queues.
1260 * Mark the queue as not stopped to prevent ath_tx_complete
1261 * from waking the queue too early.
1263 txq = &sc->tx.txq[i];
1264 txq->stopped = false;
1265 ath_draintxq(sc, txq, retry_tx);
1271 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1273 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1274 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1277 /* For each axq_acq entry, for each tid, try to schedule packets
1278 * for transmit until ampdu_depth has reached min Q depth.
1280 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1282 struct ath_atx_ac *ac, *ac_tmp, *last_ac;
1283 struct ath_atx_tid *tid, *last_tid;
1285 if (list_empty(&txq->axq_acq) ||
1286 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1289 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1290 last_ac = list_entry(txq->axq_acq.prev, struct ath_atx_ac, list);
1292 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1293 last_tid = list_entry(ac->tid_q.prev, struct ath_atx_tid, list);
1294 list_del(&ac->list);
1297 while (!list_empty(&ac->tid_q)) {
1298 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid,
1300 list_del(&tid->list);
1306 ath_tx_sched_aggr(sc, txq, tid);
1309 * add tid to round-robin queue if more frames
1310 * are pending for the tid
1312 if (!list_empty(&tid->buf_q))
1313 ath_tx_queue_tid(txq, tid);
1315 if (tid == last_tid ||
1316 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1320 if (!list_empty(&ac->tid_q)) {
1323 list_add_tail(&ac->list, &txq->axq_acq);
1327 if (ac == last_ac ||
1328 txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH)
1338 * Insert a chain of ath_buf (descriptors) on a txq and
1339 * assume the descriptors are already chained together by caller.
1341 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1342 struct list_head *head, bool internal)
1344 struct ath_hw *ah = sc->sc_ah;
1345 struct ath_common *common = ath9k_hw_common(ah);
1346 struct ath_buf *bf, *bf_last;
1347 bool puttxbuf = false;
1351 * Insert the frame on the outbound list and
1352 * pass it on to the hardware.
1355 if (list_empty(head))
1358 edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1359 bf = list_first_entry(head, struct ath_buf, list);
1360 bf_last = list_entry(head->prev, struct ath_buf, list);
1362 ath_dbg(common, ATH_DBG_QUEUE,
1363 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1365 if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
1366 list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
1367 INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
1370 list_splice_tail_init(head, &txq->axq_q);
1372 if (txq->axq_link) {
1373 ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
1374 ath_dbg(common, ATH_DBG_XMIT,
1375 "link[%u] (%p)=%llx (%p)\n",
1376 txq->axq_qnum, txq->axq_link,
1377 ito64(bf->bf_daddr), bf->bf_desc);
1381 txq->axq_link = bf_last->bf_desc;
1385 TX_STAT_INC(txq->axq_qnum, puttxbuf);
1386 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1387 ath_dbg(common, ATH_DBG_XMIT, "TXDP[%u] = %llx (%p)\n",
1388 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1392 TX_STAT_INC(txq->axq_qnum, txstart);
1393 ath9k_hw_txstart(ah, txq->axq_qnum);
1398 if (bf_is_ampdu_not_probing(bf))
1399 txq->axq_ampdu_depth++;
1403 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1404 struct ath_buf *bf, struct ath_tx_control *txctl)
1406 struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1407 struct list_head bf_head;
1409 bf->bf_state.bf_type |= BUF_AMPDU;
1412 * Do not queue to h/w when any of the following conditions is true:
1413 * - there are pending frames in software queue
1414 * - the TID is currently paused for ADDBA/BAR request
1415 * - seqno is not within block-ack window
1416 * - h/w queue depth exceeds low water mark
1418 if (!list_empty(&tid->buf_q) || tid->paused ||
1419 !BAW_WITHIN(tid->seq_start, tid->baw_size, fi->seqno) ||
1420 txctl->txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) {
1422 * Add this frame to software queue for scheduling later
1425 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_sw);
1426 list_add_tail(&bf->list, &tid->buf_q);
1427 if (!txctl->an || !txctl->an->sleeping)
1428 ath_tx_queue_tid(txctl->txq, tid);
1432 INIT_LIST_HEAD(&bf_head);
1433 list_add(&bf->list, &bf_head);
1435 /* Add sub-frame to BAW */
1437 ath_tx_addto_baw(sc, tid, fi->seqno);
1439 /* Queue to h/w without aggregation */
1440 TX_STAT_INC(txctl->txq->axq_qnum, a_queued_hw);
1442 ath_buf_set_rate(sc, bf, fi->framelen);
1443 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head, false);
1446 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1447 struct ath_atx_tid *tid,
1448 struct list_head *bf_head)
1450 struct ath_frame_info *fi;
1453 bf = list_first_entry(bf_head, struct ath_buf, list);
1454 bf->bf_state.bf_type &= ~BUF_AMPDU;
1456 /* update starting sequence number for subsequent ADDBA request */
1458 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1461 fi = get_frame_info(bf->bf_mpdu);
1462 ath_buf_set_rate(sc, bf, fi->framelen);
1463 ath_tx_txqaddbuf(sc, txq, bf_head, false);
1464 TX_STAT_INC(txq->axq_qnum, queued);
1467 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1469 struct ieee80211_hdr *hdr;
1470 enum ath9k_pkt_type htype;
1473 hdr = (struct ieee80211_hdr *)skb->data;
1474 fc = hdr->frame_control;
1476 if (ieee80211_is_beacon(fc))
1477 htype = ATH9K_PKT_TYPE_BEACON;
1478 else if (ieee80211_is_probe_resp(fc))
1479 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1480 else if (ieee80211_is_atim(fc))
1481 htype = ATH9K_PKT_TYPE_ATIM;
1482 else if (ieee80211_is_pspoll(fc))
1483 htype = ATH9K_PKT_TYPE_PSPOLL;
1485 htype = ATH9K_PKT_TYPE_NORMAL;
1490 static void setup_frame_info(struct ieee80211_hw *hw, struct sk_buff *skb,
1493 struct ath_softc *sc = hw->priv;
1494 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1495 struct ieee80211_sta *sta = tx_info->control.sta;
1496 struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
1497 struct ieee80211_hdr *hdr;
1498 struct ath_frame_info *fi = get_frame_info(skb);
1499 struct ath_node *an = NULL;
1500 struct ath_atx_tid *tid;
1501 enum ath9k_key_type keytype;
1505 keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
1508 an = (struct ath_node *) sta->drv_priv;
1510 hdr = (struct ieee80211_hdr *)skb->data;
1511 if (an && ieee80211_is_data_qos(hdr->frame_control) &&
1512 conf_is_ht(&hw->conf) && (sc->sc_flags & SC_OP_TXAGGR)) {
1514 tidno = ieee80211_get_qos_ctl(hdr)[0] & IEEE80211_QOS_CTL_TID_MASK;
1517 * Override seqno set by upper layer with the one
1518 * in tx aggregation state.
1520 tid = ATH_AN_2_TID(an, tidno);
1521 seqno = tid->seq_next;
1522 hdr->seq_ctrl = cpu_to_le16(seqno << IEEE80211_SEQ_SEQ_SHIFT);
1523 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1526 memset(fi, 0, sizeof(*fi));
1528 fi->keyix = hw_key->hw_key_idx;
1529 else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
1530 fi->keyix = an->ps_key;
1532 fi->keyix = ATH9K_TXKEYIX_INVALID;
1533 fi->keytype = keytype;
1534 fi->framelen = framelen;
1538 static int setup_tx_flags(struct sk_buff *skb)
1540 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1543 flags |= ATH9K_TXDESC_INTREQ;
1545 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1546 flags |= ATH9K_TXDESC_NOACK;
1548 if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1549 flags |= ATH9K_TXDESC_LDPC;
1556 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1557 * width - 0 for 20 MHz, 1 for 40 MHz
1558 * half_gi - to use 4us v/s 3.6 us for symbol time
1560 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1561 int width, int half_gi, bool shortPreamble)
1563 u32 nbits, nsymbits, duration, nsymbols;
1566 /* find number of symbols: PLCP + data */
1567 streams = HT_RC_2_STREAMS(rix);
1568 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1569 nsymbits = bits_per_symbol[rix % 8][width] * streams;
1570 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1573 duration = SYMBOL_TIME(nsymbols);
1575 duration = SYMBOL_TIME_HALFGI(nsymbols);
1577 /* addup duration for legacy/ht training and signal fields */
1578 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1583 u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
1585 struct ath_hw *ah = sc->sc_ah;
1586 struct ath9k_channel *curchan = ah->curchan;
1587 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) &&
1588 (curchan->channelFlags & CHANNEL_5GHZ) &&
1589 (chainmask == 0x7) && (rate < 0x90))
1595 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf, int len)
1597 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1598 struct ath9k_11n_rate_series series[4];
1599 struct sk_buff *skb;
1600 struct ieee80211_tx_info *tx_info;
1601 struct ieee80211_tx_rate *rates;
1602 const struct ieee80211_rate *rate;
1603 struct ieee80211_hdr *hdr;
1605 u8 rix = 0, ctsrate = 0;
1608 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1611 tx_info = IEEE80211_SKB_CB(skb);
1612 rates = tx_info->control.rates;
1613 hdr = (struct ieee80211_hdr *)skb->data;
1614 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1617 * We check if Short Preamble is needed for the CTS rate by
1618 * checking the BSS's global flag.
1619 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1621 rate = ieee80211_get_rts_cts_rate(sc->hw, tx_info);
1622 ctsrate = rate->hw_value;
1623 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1624 ctsrate |= rate->hw_value_short;
1626 for (i = 0; i < 4; i++) {
1627 bool is_40, is_sgi, is_sp;
1630 if (!rates[i].count || (rates[i].idx < 0))
1634 series[i].Tries = rates[i].count;
1636 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1637 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1638 flags |= ATH9K_TXDESC_RTSENA;
1639 } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1640 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1641 flags |= ATH9K_TXDESC_CTSENA;
1644 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1645 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1646 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1647 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1649 is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1650 is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1651 is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1653 if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1655 series[i].Rate = rix | 0x80;
1656 series[i].ChSel = ath_txchainmask_reduction(sc,
1657 common->tx_chainmask, series[i].Rate);
1658 series[i].PktDuration = ath_pkt_duration(sc, rix, len,
1659 is_40, is_sgi, is_sp);
1660 if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1661 series[i].RateFlags |= ATH9K_RATESERIES_STBC;
1666 if ((tx_info->band == IEEE80211_BAND_2GHZ) &&
1667 !(rate->flags & IEEE80211_RATE_ERP_G))
1668 phy = WLAN_RC_PHY_CCK;
1670 phy = WLAN_RC_PHY_OFDM;
1672 rate = &sc->sbands[tx_info->band].bitrates[rates[i].idx];
1673 series[i].Rate = rate->hw_value;
1674 if (rate->hw_value_short) {
1675 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1676 series[i].Rate |= rate->hw_value_short;
1681 if (bf->bf_state.bfs_paprd)
1682 series[i].ChSel = common->tx_chainmask;
1684 series[i].ChSel = ath_txchainmask_reduction(sc,
1685 common->tx_chainmask, series[i].Rate);
1687 series[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1688 phy, rate->bitrate * 100, len, rix, is_sp);
1691 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1692 if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1693 flags &= ~ATH9K_TXDESC_RTSENA;
1695 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1696 if (flags & ATH9K_TXDESC_RTSENA)
1697 flags &= ~ATH9K_TXDESC_CTSENA;
1699 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1700 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1701 bf->bf_lastbf->bf_desc,
1702 !is_pspoll, ctsrate,
1703 0, series, 4, flags);
1707 static struct ath_buf *ath_tx_setup_buffer(struct ieee80211_hw *hw,
1708 struct ath_txq *txq,
1709 struct sk_buff *skb)
1711 struct ath_softc *sc = hw->priv;
1712 struct ath_hw *ah = sc->sc_ah;
1713 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1714 struct ath_frame_info *fi = get_frame_info(skb);
1716 struct ath_desc *ds;
1719 bf = ath_tx_get_buffer(sc);
1721 ath_dbg(common, ATH_DBG_XMIT, "TX buffers are full\n");
1725 ATH_TXBUF_RESET(bf);
1727 bf->bf_flags = setup_tx_flags(skb);
1730 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
1731 skb->len, DMA_TO_DEVICE);
1732 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
1734 bf->bf_buf_addr = 0;
1735 ath_err(ath9k_hw_common(sc->sc_ah),
1736 "dma_mapping_error() on TX\n");
1737 ath_tx_return_buffer(sc, bf);
1741 frm_type = get_hw_packet_type(skb);
1744 ath9k_hw_set_desc_link(ah, ds, 0);
1746 ath9k_hw_set11n_txdesc(ah, ds, fi->framelen, frm_type, MAX_RATE_POWER,
1747 fi->keyix, fi->keytype, bf->bf_flags);
1749 ath9k_hw_filltxdesc(ah, ds,
1750 skb->len, /* segment length */
1751 true, /* first segment */
1752 true, /* last segment */
1753 ds, /* first descriptor */
1761 /* FIXME: tx power */
1762 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1763 struct ath_tx_control *txctl)
1765 struct sk_buff *skb = bf->bf_mpdu;
1766 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1767 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1768 struct list_head bf_head;
1769 struct ath_atx_tid *tid = NULL;
1772 spin_lock_bh(&txctl->txq->axq_lock);
1773 if ((sc->sc_flags & SC_OP_TXAGGR) && txctl->an &&
1774 ieee80211_is_data_qos(hdr->frame_control)) {
1775 tidno = ieee80211_get_qos_ctl(hdr)[0] &
1776 IEEE80211_QOS_CTL_TID_MASK;
1777 tid = ATH_AN_2_TID(txctl->an, tidno);
1779 WARN_ON(tid->ac->txq != txctl->txq);
1782 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && tid) {
1784 * Try aggregation if it's a unicast data frame
1785 * and the destination is HT capable.
1787 ath_tx_send_ampdu(sc, tid, bf, txctl);
1789 INIT_LIST_HEAD(&bf_head);
1790 list_add_tail(&bf->list, &bf_head);
1792 bf->bf_state.bfs_paprd = txctl->paprd;
1794 if (bf->bf_state.bfs_paprd)
1795 ar9003_hw_set_paprd_txdesc(sc->sc_ah, bf->bf_desc,
1796 bf->bf_state.bfs_paprd);
1799 bf->bf_state.bfs_paprd_timestamp = jiffies;
1801 if (tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT)
1802 ath9k_hw_set_clrdmask(sc->sc_ah, bf->bf_desc, true);
1804 ath_tx_send_normal(sc, txctl->txq, tid, &bf_head);
1807 spin_unlock_bh(&txctl->txq->axq_lock);
1810 /* Upon failure caller should free skb */
1811 int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1812 struct ath_tx_control *txctl)
1814 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1815 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1816 struct ieee80211_sta *sta = info->control.sta;
1817 struct ieee80211_vif *vif = info->control.vif;
1818 struct ath_softc *sc = hw->priv;
1819 struct ath_txq *txq = txctl->txq;
1821 int padpos, padsize;
1822 int frmlen = skb->len + FCS_LEN;
1825 /* NOTE: sta can be NULL according to net/mac80211.h */
1827 txctl->an = (struct ath_node *)sta->drv_priv;
1829 if (info->control.hw_key)
1830 frmlen += info->control.hw_key->icv_len;
1833 * As a temporary workaround, assign seq# here; this will likely need
1834 * to be cleaned up to work better with Beacon transmission and virtual
1837 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1838 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1839 sc->tx.seq_no += 0x10;
1840 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1841 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1844 /* Add the padding after the header if this is not already done */
1845 padpos = ath9k_cmn_padpos(hdr->frame_control);
1846 padsize = padpos & 3;
1847 if (padsize && skb->len > padpos) {
1848 if (skb_headroom(skb) < padsize)
1851 skb_push(skb, padsize);
1852 memmove(skb->data, skb->data + padsize, padpos);
1855 if ((vif && vif->type != NL80211_IFTYPE_AP &&
1856 vif->type != NL80211_IFTYPE_AP_VLAN) ||
1857 !ieee80211_is_data(hdr->frame_control))
1858 info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1860 setup_frame_info(hw, skb, frmlen);
1863 * At this point, the vif, hw_key and sta pointers in the tx control
1864 * info are no longer valid (overwritten by the ath_frame_info data.
1867 bf = ath_tx_setup_buffer(hw, txctl->txq, skb);
1871 q = skb_get_queue_mapping(skb);
1872 spin_lock_bh(&txq->axq_lock);
1873 if (txq == sc->tx.txq_map[q] &&
1874 ++txq->pending_frames > ATH_MAX_QDEPTH && !txq->stopped) {
1875 ieee80211_stop_queue(sc->hw, q);
1878 spin_unlock_bh(&txq->axq_lock);
1880 ath_tx_start_dma(sc, bf, txctl);
1889 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1890 int tx_flags, struct ath_txq *txq)
1892 struct ieee80211_hw *hw = sc->hw;
1893 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1894 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1895 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1896 int q, padpos, padsize;
1898 ath_dbg(common, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1900 if (tx_flags & ATH_TX_BAR)
1901 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1903 if (!(tx_flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1904 /* Frame was ACKed */
1905 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1908 padpos = ath9k_cmn_padpos(hdr->frame_control);
1909 padsize = padpos & 3;
1910 if (padsize && skb->len>padpos+padsize) {
1912 * Remove MAC header padding before giving the frame back to
1915 memmove(skb->data + padsize, skb->data, padpos);
1916 skb_pull(skb, padsize);
1919 if (sc->ps_flags & PS_WAIT_FOR_TX_ACK) {
1920 sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
1921 ath_dbg(common, ATH_DBG_PS,
1922 "Going back to sleep after having received TX status (0x%lx)\n",
1923 sc->ps_flags & (PS_WAIT_FOR_BEACON |
1925 PS_WAIT_FOR_PSPOLL_DATA |
1926 PS_WAIT_FOR_TX_ACK));
1929 q = skb_get_queue_mapping(skb);
1930 if (txq == sc->tx.txq_map[q]) {
1931 spin_lock_bh(&txq->axq_lock);
1932 if (WARN_ON(--txq->pending_frames < 0))
1933 txq->pending_frames = 0;
1935 if (txq->stopped && txq->pending_frames < ATH_MAX_QDEPTH) {
1936 ieee80211_wake_queue(sc->hw, q);
1939 spin_unlock_bh(&txq->axq_lock);
1942 ieee80211_tx_status(hw, skb);
1945 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1946 struct ath_txq *txq, struct list_head *bf_q,
1947 struct ath_tx_status *ts, int txok, int sendbar)
1949 struct sk_buff *skb = bf->bf_mpdu;
1950 unsigned long flags;
1954 tx_flags = ATH_TX_BAR;
1957 tx_flags |= ATH_TX_ERROR;
1959 if (bf_isxretried(bf))
1960 tx_flags |= ATH_TX_XRETRY;
1963 dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
1964 bf->bf_buf_addr = 0;
1966 if (bf->bf_state.bfs_paprd) {
1967 if (time_after(jiffies,
1968 bf->bf_state.bfs_paprd_timestamp +
1969 msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
1970 dev_kfree_skb_any(skb);
1972 complete(&sc->paprd_complete);
1974 ath_debug_stat_tx(sc, bf, ts, txq);
1975 ath_tx_complete(sc, skb, tx_flags, txq);
1977 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
1978 * accidentally reference it later.
1983 * Return the list of ath_buf of this mpdu to free queue
1985 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1986 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1987 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1990 static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
1991 struct ath_tx_status *ts, int nframes, int nbad,
1992 int txok, bool update_rc)
1994 struct sk_buff *skb = bf->bf_mpdu;
1995 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1996 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1997 struct ieee80211_hw *hw = sc->hw;
1998 struct ath_hw *ah = sc->sc_ah;
2002 tx_info->status.ack_signal = ts->ts_rssi;
2004 tx_rateindex = ts->ts_rateindex;
2005 WARN_ON(tx_rateindex >= hw->max_rates);
2007 if (ts->ts_status & ATH9K_TXERR_FILT)
2008 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2009 if ((tx_info->flags & IEEE80211_TX_CTL_AMPDU) && update_rc) {
2010 tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2012 BUG_ON(nbad > nframes);
2014 tx_info->status.ampdu_len = nframes;
2015 tx_info->status.ampdu_ack_len = nframes - nbad;
2018 if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2019 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0 && update_rc) {
2021 * If an underrun error is seen assume it as an excessive
2022 * retry only if max frame trigger level has been reached
2023 * (2 KB for single stream, and 4 KB for dual stream).
2024 * Adjust the long retry as if the frame was tried
2025 * hw->max_rate_tries times to affect how rate control updates
2026 * PER for the failed rate.
2027 * In case of congestion on the bus penalizing this type of
2028 * underruns should help hardware actually transmit new frames
2029 * successfully by eventually preferring slower rates.
2030 * This itself should also alleviate congestion on the bus.
2032 if (ieee80211_is_data(hdr->frame_control) &&
2033 (ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2034 ATH9K_TX_DELIM_UNDERRUN)) &&
2035 ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2036 tx_info->status.rates[tx_rateindex].count =
2040 for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2041 tx_info->status.rates[i].count = 0;
2042 tx_info->status.rates[i].idx = -1;
2045 tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2048 static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
2049 struct ath_tx_status *ts, struct ath_buf *bf,
2050 struct list_head *bf_head)
2051 __releases(txq->axq_lock)
2052 __acquires(txq->axq_lock)
2057 txok = !(ts->ts_status & ATH9K_TXERR_MASK);
2058 txq->axq_tx_inprogress = false;
2059 if (bf_is_ampdu_not_probing(bf))
2060 txq->axq_ampdu_depth--;
2062 spin_unlock_bh(&txq->axq_lock);
2064 if (!bf_isampdu(bf)) {
2066 * This frame is sent out as a single frame.
2067 * Use hardware retry status for this frame.
2069 if (ts->ts_status & ATH9K_TXERR_XRETRY)
2070 bf->bf_state.bf_type |= BUF_XRETRY;
2071 ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok, true);
2072 ath_tx_complete_buf(sc, bf, txq, bf_head, ts, txok, 0);
2074 ath_tx_complete_aggr(sc, txq, bf, bf_head, ts, txok, true);
2076 spin_lock_bh(&txq->axq_lock);
2078 if (sc->sc_flags & SC_OP_TXAGGR)
2079 ath_txq_schedule(sc, txq);
2082 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2084 struct ath_hw *ah = sc->sc_ah;
2085 struct ath_common *common = ath9k_hw_common(ah);
2086 struct ath_buf *bf, *lastbf, *bf_held = NULL;
2087 struct list_head bf_head;
2088 struct ath_desc *ds;
2089 struct ath_tx_status ts;
2092 ath_dbg(common, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
2093 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2096 spin_lock_bh(&txq->axq_lock);
2098 if (list_empty(&txq->axq_q)) {
2099 txq->axq_link = NULL;
2100 if (sc->sc_flags & SC_OP_TXAGGR)
2101 ath_txq_schedule(sc, txq);
2104 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2107 * There is a race condition that a BH gets scheduled
2108 * after sw writes TxE and before hw re-load the last
2109 * descriptor to get the newly chained one.
2110 * Software must keep the last DONE descriptor as a
2111 * holding descriptor - software does so by marking
2112 * it with the STALE flag.
2117 if (list_is_last(&bf_held->list, &txq->axq_q))
2120 bf = list_entry(bf_held->list.next, struct ath_buf,
2124 lastbf = bf->bf_lastbf;
2125 ds = lastbf->bf_desc;
2127 memset(&ts, 0, sizeof(ts));
2128 status = ath9k_hw_txprocdesc(ah, ds, &ts);
2129 if (status == -EINPROGRESS)
2132 TX_STAT_INC(txq->axq_qnum, txprocdesc);
2135 * Remove ath_buf's of the same transmit unit from txq,
2136 * however leave the last descriptor back as the holding
2137 * descriptor for hw.
2139 lastbf->bf_stale = true;
2140 INIT_LIST_HEAD(&bf_head);
2141 if (!list_is_singular(&lastbf->list))
2142 list_cut_position(&bf_head,
2143 &txq->axq_q, lastbf->list.prev);
2146 list_del(&bf_held->list);
2147 ath_tx_return_buffer(sc, bf_held);
2150 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2152 spin_unlock_bh(&txq->axq_lock);
2155 static void ath_tx_complete_poll_work(struct work_struct *work)
2157 struct ath_softc *sc = container_of(work, struct ath_softc,
2158 tx_complete_work.work);
2159 struct ath_txq *txq;
2161 bool needreset = false;
2162 #ifdef CONFIG_ATH9K_DEBUGFS
2163 sc->tx_complete_poll_work_seen++;
2166 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
2167 if (ATH_TXQ_SETUP(sc, i)) {
2168 txq = &sc->tx.txq[i];
2169 spin_lock_bh(&txq->axq_lock);
2170 if (txq->axq_depth) {
2171 if (txq->axq_tx_inprogress) {
2173 spin_unlock_bh(&txq->axq_lock);
2176 txq->axq_tx_inprogress = true;
2179 spin_unlock_bh(&txq->axq_lock);
2183 ath_dbg(ath9k_hw_common(sc->sc_ah), ATH_DBG_RESET,
2184 "tx hung, resetting the chip\n");
2185 spin_lock_bh(&sc->sc_pcu_lock);
2186 ath_reset(sc, true);
2187 spin_unlock_bh(&sc->sc_pcu_lock);
2190 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2191 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT));
2196 void ath_tx_tasklet(struct ath_softc *sc)
2199 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2201 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2203 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2204 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2205 ath_tx_processq(sc, &sc->tx.txq[i]);
2209 void ath_tx_edma_tasklet(struct ath_softc *sc)
2211 struct ath_tx_status ts;
2212 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2213 struct ath_hw *ah = sc->sc_ah;
2214 struct ath_txq *txq;
2215 struct ath_buf *bf, *lastbf;
2216 struct list_head bf_head;
2220 status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2221 if (status == -EINPROGRESS)
2223 if (status == -EIO) {
2224 ath_dbg(common, ATH_DBG_XMIT,
2225 "Error processing tx status\n");
2229 /* Skip beacon completions */
2230 if (ts.qid == sc->beacon.beaconq)
2233 txq = &sc->tx.txq[ts.qid];
2235 spin_lock_bh(&txq->axq_lock);
2237 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2238 spin_unlock_bh(&txq->axq_lock);
2242 bf = list_first_entry(&txq->txq_fifo[txq->txq_tailidx],
2243 struct ath_buf, list);
2244 lastbf = bf->bf_lastbf;
2246 INIT_LIST_HEAD(&bf_head);
2247 list_cut_position(&bf_head, &txq->txq_fifo[txq->txq_tailidx],
2250 if (list_empty(&txq->txq_fifo[txq->txq_tailidx])) {
2251 INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2253 if (!list_empty(&txq->axq_q)) {
2254 struct list_head bf_q;
2256 INIT_LIST_HEAD(&bf_q);
2257 txq->axq_link = NULL;
2258 list_splice_tail_init(&txq->axq_q, &bf_q);
2259 ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2263 ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2264 spin_unlock_bh(&txq->axq_lock);
2272 static int ath_txstatus_setup(struct ath_softc *sc, int size)
2274 struct ath_descdma *dd = &sc->txsdma;
2275 u8 txs_len = sc->sc_ah->caps.txs_len;
2277 dd->dd_desc_len = size * txs_len;
2278 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2279 &dd->dd_desc_paddr, GFP_KERNEL);
2286 static int ath_tx_edma_init(struct ath_softc *sc)
2290 err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2292 ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2293 sc->txsdma.dd_desc_paddr,
2294 ATH_TXSTATUS_RING_SIZE);
2299 static void ath_tx_edma_cleanup(struct ath_softc *sc)
2301 struct ath_descdma *dd = &sc->txsdma;
2303 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2307 int ath_tx_init(struct ath_softc *sc, int nbufs)
2309 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2312 spin_lock_init(&sc->tx.txbuflock);
2314 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2318 "Failed to allocate tx descriptors: %d\n", error);
2322 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2323 "beacon", ATH_BCBUF, 1, 1);
2326 "Failed to allocate beacon descriptors: %d\n", error);
2330 INIT_DELAYED_WORK(&sc->tx_complete_work, ath_tx_complete_poll_work);
2332 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
2333 error = ath_tx_edma_init(sc);
2345 void ath_tx_cleanup(struct ath_softc *sc)
2347 if (sc->beacon.bdma.dd_desc_len != 0)
2348 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2350 if (sc->tx.txdma.dd_desc_len != 0)
2351 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2353 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2354 ath_tx_edma_cleanup(sc);
2357 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2359 struct ath_atx_tid *tid;
2360 struct ath_atx_ac *ac;
2363 for (tidno = 0, tid = &an->tid[tidno];
2364 tidno < WME_NUM_TID;
2368 tid->seq_start = tid->seq_next = 0;
2369 tid->baw_size = WME_MAX_BA;
2370 tid->baw_head = tid->baw_tail = 0;
2372 tid->paused = false;
2373 tid->state &= ~AGGR_CLEANUP;
2374 INIT_LIST_HEAD(&tid->buf_q);
2375 acno = TID_TO_WME_AC(tidno);
2376 tid->ac = &an->ac[acno];
2377 tid->state &= ~AGGR_ADDBA_COMPLETE;
2378 tid->state &= ~AGGR_ADDBA_PROGRESS;
2381 for (acno = 0, ac = &an->ac[acno];
2382 acno < WME_NUM_AC; acno++, ac++) {
2384 ac->txq = sc->tx.txq_map[acno];
2385 INIT_LIST_HEAD(&ac->tid_q);
2389 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2391 struct ath_atx_ac *ac;
2392 struct ath_atx_tid *tid;
2393 struct ath_txq *txq;
2396 for (tidno = 0, tid = &an->tid[tidno];
2397 tidno < WME_NUM_TID; tidno++, tid++) {
2402 spin_lock_bh(&txq->axq_lock);
2405 list_del(&tid->list);
2410 list_del(&ac->list);
2411 tid->ac->sched = false;
2414 ath_tid_drain(sc, txq, tid);
2415 tid->state &= ~AGGR_ADDBA_COMPLETE;
2416 tid->state &= ~AGGR_CLEANUP;
2418 spin_unlock_bh(&txq->axq_lock);