2 i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware
4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
7 Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Supports the following Intel I/O Controller Hubs (ICH):
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 Tolapai 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
47 Features supported by this driver:
51 Block process call transaction no
52 I2C block read transaction yes (doesn't use the block buffer)
54 See the file Documentation/i2c/busses/i2c-i801 for details.
57 /* Note: we assume there can only be one I801, with one SMBus interface */
59 #include <linux/module.h>
60 #include <linux/pci.h>
61 #include <linux/kernel.h>
62 #include <linux/stddef.h>
63 #include <linux/delay.h>
64 #include <linux/ioport.h>
65 #include <linux/init.h>
66 #include <linux/i2c.h>
67 #include <linux/acpi.h>
70 /* I801 SMBus address offsets */
71 #define SMBHSTSTS (0 + i801_smba)
72 #define SMBHSTCNT (2 + i801_smba)
73 #define SMBHSTCMD (3 + i801_smba)
74 #define SMBHSTADD (4 + i801_smba)
75 #define SMBHSTDAT0 (5 + i801_smba)
76 #define SMBHSTDAT1 (6 + i801_smba)
77 #define SMBBLKDAT (7 + i801_smba)
78 #define SMBPEC (8 + i801_smba) /* ICH3 and later */
79 #define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */
80 #define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */
82 /* PCI Address Constants */
84 #define SMBHSTCFG 0x040
86 /* Host configuration bits for SMBHSTCFG */
87 #define SMBHSTCFG_HST_EN 1
88 #define SMBHSTCFG_SMB_SMI_EN 2
89 #define SMBHSTCFG_I2C_EN 4
91 /* Auxillary control register bits, ICH4+ only */
92 #define SMBAUXCTL_CRC 1
93 #define SMBAUXCTL_E32B 2
95 /* kill bit for SMBHSTCNT */
96 #define SMBHSTCNT_KILL 2
99 #define MAX_TIMEOUT 100
100 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
102 /* I801 command constants */
103 #define I801_QUICK 0x00
104 #define I801_BYTE 0x04
105 #define I801_BYTE_DATA 0x08
106 #define I801_WORD_DATA 0x0C
107 #define I801_PROC_CALL 0x10 /* unimplemented */
108 #define I801_BLOCK_DATA 0x14
109 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
110 #define I801_BLOCK_LAST 0x34
111 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
112 #define I801_START 0x40
113 #define I801_PEC_EN 0x80 /* ICH3 and later */
115 /* I801 Hosts Status register bits */
116 #define SMBHSTSTS_BYTE_DONE 0x80
117 #define SMBHSTSTS_INUSE_STS 0x40
118 #define SMBHSTSTS_SMBALERT_STS 0x20
119 #define SMBHSTSTS_FAILED 0x10
120 #define SMBHSTSTS_BUS_ERR 0x08
121 #define SMBHSTSTS_DEV_ERR 0x04
122 #define SMBHSTSTS_INTR 0x02
123 #define SMBHSTSTS_HOST_BUSY 0x01
125 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
126 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
129 static unsigned long i801_smba;
130 static unsigned char i801_original_hstcfg;
131 static struct pci_driver i801_driver;
132 static struct pci_dev *I801_dev;
134 #define FEATURE_SMBUS_PEC (1 << 0)
135 #define FEATURE_BLOCK_BUFFER (1 << 1)
136 #define FEATURE_BLOCK_PROC (1 << 2)
137 #define FEATURE_I2C_BLOCK_READ (1 << 3)
138 static unsigned int i801_features;
140 /* Make sure the SMBus host is ready to start transmitting.
141 Return 0 if it is, -EBUSY if it is not. */
142 static int i801_check_pre(void)
146 status = inb_p(SMBHSTSTS);
147 if (status & SMBHSTSTS_HOST_BUSY) {
148 dev_err(&I801_dev->dev, "SMBus is busy, can't use it!\n");
152 status &= STATUS_FLAGS;
154 dev_dbg(&I801_dev->dev, "Clearing status flags (%02x)\n",
156 outb_p(status, SMBHSTSTS);
157 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
159 dev_err(&I801_dev->dev,
160 "Failed clearing status flags (%02x)\n",
169 /* Convert the status register to an error code, and clear it. */
170 static int i801_check_post(int status, int timeout)
174 /* If the SMBus is still busy, we give up */
176 dev_err(&I801_dev->dev, "Transaction timeout\n");
177 /* try to stop the current command */
178 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
179 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
181 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
183 /* Check if it worked */
184 status = inb_p(SMBHSTSTS);
185 if ((status & SMBHSTSTS_HOST_BUSY) ||
186 !(status & SMBHSTSTS_FAILED))
187 dev_err(&I801_dev->dev,
188 "Failed terminating the transaction\n");
189 outb_p(STATUS_FLAGS, SMBHSTSTS);
193 if (status & SMBHSTSTS_FAILED) {
195 dev_err(&I801_dev->dev, "Transaction failed\n");
197 if (status & SMBHSTSTS_DEV_ERR) {
199 dev_dbg(&I801_dev->dev, "No response\n");
201 if (status & SMBHSTSTS_BUS_ERR) {
203 dev_dbg(&I801_dev->dev, "Lost arbitration\n");
207 /* Clear error flags */
208 outb_p(status & STATUS_FLAGS, SMBHSTSTS);
209 status = inb_p(SMBHSTSTS) & STATUS_FLAGS;
211 dev_warn(&I801_dev->dev, "Failed clearing status "
212 "flags at end of transaction (%02x)\n",
220 static int i801_transaction(int xact)
226 result = i801_check_pre();
230 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
231 * INTREN, SMBSCMD are passed in xact */
232 outb_p(xact | I801_START, SMBHSTCNT);
234 /* We will always wait for a fraction of a second! */
237 status = inb_p(SMBHSTSTS);
238 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
240 result = i801_check_post(status, timeout >= MAX_TIMEOUT);
244 outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
248 /* wait for INTR bit as advised by Intel */
249 static void i801_wait_hwpec(void)
256 status = inb_p(SMBHSTSTS);
257 } while ((!(status & SMBHSTSTS_INTR))
258 && (timeout++ < MAX_TIMEOUT));
260 if (timeout >= MAX_TIMEOUT) {
261 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
263 outb_p(status, SMBHSTSTS);
266 static int i801_block_transaction_by_block(union i2c_smbus_data *data,
267 char read_write, int hwpec)
272 inb_p(SMBHSTCNT); /* reset the data buffer index */
274 /* Use 32-byte buffer to process this transaction */
275 if (read_write == I2C_SMBUS_WRITE) {
276 len = data->block[0];
277 outb_p(len, SMBHSTDAT0);
278 for (i = 0; i < len; i++)
279 outb_p(data->block[i+1], SMBBLKDAT);
282 status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
283 I801_PEC_EN * hwpec);
287 if (read_write == I2C_SMBUS_READ) {
288 len = inb_p(SMBHSTDAT0);
289 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
292 data->block[0] = len;
293 for (i = 0; i < len; i++)
294 data->block[i + 1] = inb_p(SMBBLKDAT);
299 static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
300 char read_write, int command,
309 result = i801_check_pre();
313 len = data->block[0];
315 if (read_write == I2C_SMBUS_WRITE) {
316 outb_p(len, SMBHSTDAT0);
317 outb_p(data->block[1], SMBBLKDAT);
320 for (i = 1; i <= len; i++) {
321 if (i == len && read_write == I2C_SMBUS_READ) {
322 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
323 smbcmd = I801_I2C_BLOCK_LAST;
325 smbcmd = I801_BLOCK_LAST;
327 if (command == I2C_SMBUS_I2C_BLOCK_DATA
328 && read_write == I2C_SMBUS_READ)
329 smbcmd = I801_I2C_BLOCK_DATA;
331 smbcmd = I801_BLOCK_DATA;
333 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
336 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
338 /* We will always wait for a fraction of a second! */
342 status = inb_p(SMBHSTSTS);
344 while ((!(status & SMBHSTSTS_BYTE_DONE))
345 && (timeout++ < MAX_TIMEOUT));
347 result = i801_check_post(status, timeout >= MAX_TIMEOUT);
351 if (i == 1 && read_write == I2C_SMBUS_READ
352 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
353 len = inb_p(SMBHSTDAT0);
354 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
355 dev_err(&I801_dev->dev,
356 "Illegal SMBus block read size %d\n",
359 while (inb_p(SMBHSTSTS) & SMBHSTSTS_HOST_BUSY)
360 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS);
361 outb_p(SMBHSTSTS_INTR, SMBHSTSTS);
364 data->block[0] = len;
367 /* Retrieve/store value in SMBBLKDAT */
368 if (read_write == I2C_SMBUS_READ)
369 data->block[i] = inb_p(SMBBLKDAT);
370 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
371 outb_p(data->block[i+1], SMBBLKDAT);
373 /* signals SMBBLKDAT ready */
374 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS);
380 static int i801_set_block_buffer_mode(void)
382 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
383 if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
388 /* Block transaction function */
389 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
390 int command, int hwpec)
395 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
396 if (read_write == I2C_SMBUS_WRITE) {
397 /* set I2C_EN bit in configuration register */
398 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
399 pci_write_config_byte(I801_dev, SMBHSTCFG,
400 hostc | SMBHSTCFG_I2C_EN);
401 } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
402 dev_err(&I801_dev->dev,
403 "I2C block read is unsupported!\n");
408 if (read_write == I2C_SMBUS_WRITE
409 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
410 if (data->block[0] < 1)
412 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
413 data->block[0] = I2C_SMBUS_BLOCK_MAX;
415 data->block[0] = 32; /* max for SMBus block reads */
418 if ((i801_features & FEATURE_BLOCK_BUFFER)
419 && !(command == I2C_SMBUS_I2C_BLOCK_DATA
420 && read_write == I2C_SMBUS_READ)
421 && i801_set_block_buffer_mode() == 0)
422 result = i801_block_transaction_by_block(data, read_write,
425 result = i801_block_transaction_byte_by_byte(data, read_write,
428 if (result == 0 && hwpec)
431 if (command == I2C_SMBUS_I2C_BLOCK_DATA
432 && read_write == I2C_SMBUS_WRITE) {
433 /* restore saved configuration register value */
434 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
439 /* Return negative errno on error. */
440 static s32 i801_access(struct i2c_adapter * adap, u16 addr,
441 unsigned short flags, char read_write, u8 command,
442 int size, union i2c_smbus_data * data)
448 hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
449 && size != I2C_SMBUS_QUICK
450 && size != I2C_SMBUS_I2C_BLOCK_DATA;
453 case I2C_SMBUS_QUICK:
454 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
459 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
461 if (read_write == I2C_SMBUS_WRITE)
462 outb_p(command, SMBHSTCMD);
465 case I2C_SMBUS_BYTE_DATA:
466 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
468 outb_p(command, SMBHSTCMD);
469 if (read_write == I2C_SMBUS_WRITE)
470 outb_p(data->byte, SMBHSTDAT0);
471 xact = I801_BYTE_DATA;
473 case I2C_SMBUS_WORD_DATA:
474 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
476 outb_p(command, SMBHSTCMD);
477 if (read_write == I2C_SMBUS_WRITE) {
478 outb_p(data->word & 0xff, SMBHSTDAT0);
479 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
481 xact = I801_WORD_DATA;
483 case I2C_SMBUS_BLOCK_DATA:
484 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
486 outb_p(command, SMBHSTCMD);
489 case I2C_SMBUS_I2C_BLOCK_DATA:
490 /* NB: page 240 of ICH5 datasheet shows that the R/#W
491 * bit should be cleared here, even when reading */
492 outb_p((addr & 0x7f) << 1, SMBHSTADD);
493 if (read_write == I2C_SMBUS_READ) {
494 /* NB: page 240 of ICH5 datasheet also shows
495 * that DATA1 is the cmd field when reading */
496 outb_p(command, SMBHSTDAT1);
498 outb_p(command, SMBHSTCMD);
502 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
506 if (hwpec) /* enable/disable hardware PEC */
507 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
509 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
512 ret = i801_block_transaction(data, read_write, size, hwpec);
514 ret = i801_transaction(xact | ENABLE_INT9);
516 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
517 time, so we forcibly disable it after every transaction. Turn off
518 E32B for the same reason. */
520 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
527 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
530 switch (xact & 0x7f) {
531 case I801_BYTE: /* Result put in SMBHSTDAT0 */
533 data->byte = inb_p(SMBHSTDAT0);
536 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
543 static u32 i801_func(struct i2c_adapter *adapter)
545 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
546 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
547 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
548 ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
549 ((i801_features & FEATURE_I2C_BLOCK_READ) ?
550 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
553 static const struct i2c_algorithm smbus_algorithm = {
554 .smbus_xfer = i801_access,
555 .functionality = i801_func,
558 static struct i2c_adapter i801_adapter = {
559 .owner = THIS_MODULE,
560 .id = I2C_HW_SMBUS_I801,
561 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
562 .algo = &smbus_algorithm,
565 static struct pci_device_id i801_ids[] = {
566 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
567 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
568 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
569 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
570 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
571 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
572 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
573 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
574 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
575 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
576 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
577 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
578 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) },
579 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
580 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
584 MODULE_DEVICE_TABLE (pci, i801_ids);
586 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
593 switch (dev->device) {
594 case PCI_DEVICE_ID_INTEL_82801EB_3:
595 case PCI_DEVICE_ID_INTEL_ESB_4:
596 case PCI_DEVICE_ID_INTEL_ICH6_16:
597 case PCI_DEVICE_ID_INTEL_ICH7_17:
598 case PCI_DEVICE_ID_INTEL_ESB2_17:
599 case PCI_DEVICE_ID_INTEL_ICH8_5:
600 case PCI_DEVICE_ID_INTEL_ICH9_6:
601 case PCI_DEVICE_ID_INTEL_TOLAPAI_1:
602 case PCI_DEVICE_ID_INTEL_ICH10_4:
603 case PCI_DEVICE_ID_INTEL_ICH10_5:
604 i801_features |= FEATURE_I2C_BLOCK_READ;
606 case PCI_DEVICE_ID_INTEL_82801DB_3:
607 i801_features |= FEATURE_SMBUS_PEC;
608 i801_features |= FEATURE_BLOCK_BUFFER;
612 err = pci_enable_device(dev);
614 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
619 /* Determine the address of the SMBus area */
620 i801_smba = pci_resource_start(dev, SMBBAR);
622 dev_err(&dev->dev, "SMBus base address uninitialized, "
628 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
632 err = pci_request_region(dev, SMBBAR, i801_driver.name);
634 dev_err(&dev->dev, "Failed to request SMBus region "
635 "0x%lx-0x%Lx\n", i801_smba,
636 (unsigned long long)pci_resource_end(dev, SMBBAR));
640 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
641 i801_original_hstcfg = temp;
642 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
643 if (!(temp & SMBHSTCFG_HST_EN)) {
644 dev_info(&dev->dev, "Enabling SMBus device\n");
645 temp |= SMBHSTCFG_HST_EN;
647 pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
649 if (temp & SMBHSTCFG_SMB_SMI_EN)
650 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
652 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
654 /* Clear special mode bits */
655 if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
656 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
659 /* set up the sysfs linkage to our parent device */
660 i801_adapter.dev.parent = &dev->dev;
662 snprintf(i801_adapter.name, sizeof(i801_adapter.name),
663 "SMBus I801 adapter at %04lx", i801_smba);
664 err = i2c_add_adapter(&i801_adapter);
666 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
672 pci_release_region(dev, SMBBAR);
677 static void __devexit i801_remove(struct pci_dev *dev)
679 i2c_del_adapter(&i801_adapter);
680 pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
681 pci_release_region(dev, SMBBAR);
683 * do not call pci_disable_device(dev) since it can cause hard hangs on
684 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
689 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
692 pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
693 pci_set_power_state(dev, pci_choose_state(dev, mesg));
697 static int i801_resume(struct pci_dev *dev)
699 pci_set_power_state(dev, PCI_D0);
700 pci_restore_state(dev);
701 return pci_enable_device(dev);
704 #define i801_suspend NULL
705 #define i801_resume NULL
708 static struct pci_driver i801_driver = {
709 .name = "i801_smbus",
710 .id_table = i801_ids,
712 .remove = __devexit_p(i801_remove),
713 .suspend = i801_suspend,
714 .resume = i801_resume,
717 static int __init i2c_i801_init(void)
719 return pci_register_driver(&i801_driver);
722 static void __exit i2c_i801_exit(void)
724 pci_unregister_driver(&i801_driver);
727 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
728 "Jean Delvare <khali@linux-fr.org>");
729 MODULE_DESCRIPTION("I801 SMBus driver");
730 MODULE_LICENSE("GPL");
732 module_init(i2c_i801_init);
733 module_exit(i2c_i801_exit);