2 i801.c - Part of lm_sensors, Linux kernel modules for hardware
4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 SUPPORTED DEVICES PCI ID
29 82801DB 24C3 (HW PEC supported, 32 byte buffer not supported)
30 82801EB 24D3 (HW PEC supported, 32 byte buffer not supported)
36 This driver supports several versions of Intel's I/O Controller Hubs (ICH).
37 For SMBus support, they are similar to the PIIX4 and are part
38 of Intel's '810' and other chipsets.
39 See the doc/busses/i2c-i801 file for details.
40 I2C Block Read and Process Call are not supported.
43 /* Note: we assume there can only be one I801, with one SMBus interface */
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/kernel.h>
48 #include <linux/stddef.h>
49 #include <linux/delay.h>
50 #include <linux/sched.h>
51 #include <linux/ioport.h>
52 #include <linux/init.h>
53 #include <linux/i2c.h>
56 /* I801 SMBus address offsets */
57 #define SMBHSTSTS (0 + i801_smba)
58 #define SMBHSTCNT (2 + i801_smba)
59 #define SMBHSTCMD (3 + i801_smba)
60 #define SMBHSTADD (4 + i801_smba)
61 #define SMBHSTDAT0 (5 + i801_smba)
62 #define SMBHSTDAT1 (6 + i801_smba)
63 #define SMBBLKDAT (7 + i801_smba)
64 #define SMBPEC (8 + i801_smba) /* ICH4 only */
65 #define SMBAUXSTS (12 + i801_smba) /* ICH4 only */
66 #define SMBAUXCTL (13 + i801_smba) /* ICH4 only */
68 /* PCI Address Constants */
70 #define SMBHSTCFG 0x040
73 /* Host configuration bits for SMBHSTCFG */
74 #define SMBHSTCFG_HST_EN 1
75 #define SMBHSTCFG_SMB_SMI_EN 2
76 #define SMBHSTCFG_I2C_EN 4
79 #define MAX_TIMEOUT 100
80 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
82 /* I801 command constants */
83 #define I801_QUICK 0x00
84 #define I801_BYTE 0x04
85 #define I801_BYTE_DATA 0x08
86 #define I801_WORD_DATA 0x0C
87 #define I801_PROC_CALL 0x10 /* later chips only, unimplemented */
88 #define I801_BLOCK_DATA 0x14
89 #define I801_I2C_BLOCK_DATA 0x18 /* unimplemented */
90 #define I801_BLOCK_LAST 0x34
91 #define I801_I2C_BLOCK_LAST 0x38 /* unimplemented */
92 #define I801_START 0x40
93 #define I801_PEC_EN 0x80 /* ICH4 only */
96 static int i801_transaction(void);
97 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
98 int command, int hwpec);
100 static unsigned short i801_smba;
101 static struct pci_driver i801_driver;
102 static struct pci_dev *I801_dev;
105 static int i801_setup(struct pci_dev *dev)
107 int error_return = 0;
111 if ((dev->device == PCI_DEVICE_ID_INTEL_82801DB_3) ||
112 (dev->device == PCI_DEVICE_ID_INTEL_82801EB_3) ||
113 (dev->device == PCI_DEVICE_ID_INTEL_ESB_4))
118 /* Determine the address of the SMBus areas */
119 pci_read_config_word(I801_dev, SMBBA, &i801_smba);
122 dev_err(&dev->dev, "SMBus base address uninitialized, "
127 if (!request_region(i801_smba, (isich4 ? 16 : 8), i801_driver.name)) {
128 dev_err(&dev->dev, "I801_smb region 0x%x already in use!\n",
130 error_return = -EBUSY;
134 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
135 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
136 pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
139 pci_write_config_byte(I801_dev, SMBHSTCFG, temp | 1);
140 dev_warn(&dev->dev, "enabling SMBus device\n");
144 dev_dbg(&dev->dev, "I801 using Interrupt SMI# for SMBus.\n");
146 dev_dbg(&dev->dev, "I801 using PCI Interrupt for SMBus.\n");
148 pci_read_config_byte(I801_dev, SMBREV, &temp);
149 dev_dbg(&dev->dev, "SMBREV = 0x%X\n", temp);
150 dev_dbg(&dev->dev, "I801_smba = 0x%X\n", i801_smba);
156 static int i801_transaction(void)
162 dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
163 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
164 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
167 /* Make sure the SMBus host is ready to start transmitting */
168 /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
169 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
170 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n",
172 outb_p(temp, SMBHSTSTS);
173 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
174 dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
177 dev_dbg(&I801_dev->dev, "Successfull!\n");
181 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
183 /* We will always wait for a fraction of a second! */
186 temp = inb_p(SMBHSTSTS);
187 } while ((temp & 0x01) && (timeout++ < MAX_TIMEOUT));
189 /* If the SMBus is still busy, we give up */
190 if (timeout >= MAX_TIMEOUT) {
191 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
197 dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
202 dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
203 "until next hard reset. (sorry!)\n");
204 /* Clock stops and slave is stuck in mid-transmission */
209 dev_dbg(&I801_dev->dev, "Error: no response!\n");
212 if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
213 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
215 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
216 dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
219 dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
220 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
221 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
226 /* All-inclusive block transaction function */
227 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
228 int command, int hwpec)
235 unsigned char hostc, errmask;
237 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
238 if (read_write == I2C_SMBUS_WRITE) {
239 /* set I2C_EN bit in configuration register */
240 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
241 pci_write_config_byte(I801_dev, SMBHSTCFG,
242 hostc | SMBHSTCFG_I2C_EN);
244 dev_err(&I801_dev->dev,
245 "I2C_SMBUS_I2C_BLOCK_READ not DB!\n");
250 if (read_write == I2C_SMBUS_WRITE) {
251 len = data->block[0];
256 outb_p(len, SMBHSTDAT0);
257 outb_p(data->block[1], SMBBLKDAT);
259 len = 32; /* max for reads */
262 if(isich4 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
263 /* set 32 byte buffer */
266 for (i = 1; i <= len; i++) {
267 if (i == len && read_write == I2C_SMBUS_READ)
268 smbcmd = I801_BLOCK_LAST;
270 smbcmd = I801_BLOCK_DATA;
271 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
273 dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
274 "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
275 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
276 inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
278 /* Make sure the SMBus host is ready to start transmitting */
279 temp = inb_p(SMBHSTSTS);
281 /* Erronenous conditions before transaction:
282 * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
285 /* Erronenous conditions during transaction:
286 * Failed, Bus_Err, Dev_Err, Intr */
289 if (temp & errmask) {
290 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
291 "Resetting...\n", temp);
292 outb_p(temp, SMBHSTSTS);
293 if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
294 dev_err(&I801_dev->dev,
295 "Reset failed! (%02x)\n", temp);
300 /* if die in middle of block transaction, fail */
307 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
309 /* We will always wait for a fraction of a second! */
313 temp = inb_p(SMBHSTSTS);
315 while ((!(temp & 0x80))
316 && (timeout++ < MAX_TIMEOUT));
318 /* If the SMBus is still busy, we give up */
319 if (timeout >= MAX_TIMEOUT) {
321 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
326 dev_dbg(&I801_dev->dev,
327 "Error: Failed bus transaction\n");
328 } else if (temp & 0x08) {
330 dev_err(&I801_dev->dev, "Bus collision!\n");
331 } else if (temp & 0x04) {
333 dev_dbg(&I801_dev->dev, "Error: no response!\n");
336 if (i == 1 && read_write == I2C_SMBUS_READ) {
337 len = inb_p(SMBHSTDAT0);
342 data->block[0] = len;
345 /* Retrieve/store value in SMBBLKDAT */
346 if (read_write == I2C_SMBUS_READ)
347 data->block[i] = inb_p(SMBBLKDAT);
348 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
349 outb_p(data->block[i+1], SMBBLKDAT);
350 if ((temp & 0x9e) != 0x00)
351 outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
353 if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
354 dev_dbg(&I801_dev->dev,
355 "Bad status (%02x) at end of transaction\n",
358 dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
359 "ADD=%02x, DAT0=%02x, BLKDAT=%02x\n", i,
360 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
361 inb_p(SMBHSTDAT0), inb_p(SMBBLKDAT));
368 /* wait for INTR bit as advised by Intel */
372 temp = inb_p(SMBHSTSTS);
373 } while ((!(temp & 0x02))
374 && (timeout++ < MAX_TIMEOUT));
376 if (timeout >= MAX_TIMEOUT) {
377 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
379 outb_p(temp, SMBHSTSTS);
383 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
384 /* restore saved configuration register value */
385 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
390 /* Return -1 on error. */
391 static s32 i801_access(struct i2c_adapter * adap, u16 addr,
392 unsigned short flags, char read_write, u8 command,
393 int size, union i2c_smbus_data * data)
399 hwpec = isich4 && (flags & I2C_CLIENT_PEC)
400 && size != I2C_SMBUS_QUICK
401 && size != I2C_SMBUS_I2C_BLOCK_DATA;
404 case I2C_SMBUS_QUICK:
405 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
410 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
412 if (read_write == I2C_SMBUS_WRITE)
413 outb_p(command, SMBHSTCMD);
416 case I2C_SMBUS_BYTE_DATA:
417 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
419 outb_p(command, SMBHSTCMD);
420 if (read_write == I2C_SMBUS_WRITE)
421 outb_p(data->byte, SMBHSTDAT0);
422 xact = I801_BYTE_DATA;
424 case I2C_SMBUS_WORD_DATA:
425 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
427 outb_p(command, SMBHSTCMD);
428 if (read_write == I2C_SMBUS_WRITE) {
429 outb_p(data->word & 0xff, SMBHSTDAT0);
430 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
432 xact = I801_WORD_DATA;
434 case I2C_SMBUS_BLOCK_DATA:
435 case I2C_SMBUS_I2C_BLOCK_DATA:
436 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
438 outb_p(command, SMBHSTCMD);
441 case I2C_SMBUS_PROC_CALL:
443 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
447 outb_p(hwpec, SMBAUXCTL); /* enable/disable hardware PEC */
450 ret = i801_block_transaction(data, read_write, size, hwpec);
452 outb_p(xact | ENABLE_INT9, SMBHSTCNT);
453 ret = i801_transaction();
456 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
457 time, so we forcibly disable it after every transaction. */
459 outb_p(0, SMBAUXCTL);
465 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
468 switch (xact & 0x7f) {
469 case I801_BYTE: /* Result put in SMBHSTDAT0 */
471 data->byte = inb_p(SMBHSTDAT0);
474 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
481 static u32 i801_func(struct i2c_adapter *adapter)
483 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
484 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
485 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK
486 | (isich4 ? I2C_FUNC_SMBUS_HWPEC_CALC : 0);
489 static struct i2c_algorithm smbus_algorithm = {
490 .smbus_xfer = i801_access,
491 .functionality = i801_func,
494 static struct i2c_adapter i801_adapter = {
495 .owner = THIS_MODULE,
496 .class = I2C_CLASS_HWMON,
497 .algo = &smbus_algorithm,
500 static struct pci_device_id i801_ids[] = {
501 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
502 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
503 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
504 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
505 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
506 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
507 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
508 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
509 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
510 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
511 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
515 MODULE_DEVICE_TABLE (pci, i801_ids);
517 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
520 if (i801_setup(dev)) {
522 "I801 not detected, module not inserted.\n");
526 /* set up the driverfs linkage to our parent device */
527 i801_adapter.dev.parent = &dev->dev;
529 snprintf(i801_adapter.name, I2C_NAME_SIZE,
530 "SMBus I801 adapter at %04x", i801_smba);
531 return i2c_add_adapter(&i801_adapter);
534 static void __devexit i801_remove(struct pci_dev *dev)
536 i2c_del_adapter(&i801_adapter);
537 release_region(i801_smba, (isich4 ? 16 : 8));
540 static struct pci_driver i801_driver = {
541 .name = "i801_smbus",
542 .id_table = i801_ids,
544 .remove = __devexit_p(i801_remove),
547 static int __init i2c_i801_init(void)
549 return pci_register_driver(&i801_driver);
552 static void __exit i2c_i801_exit(void)
554 pci_unregister_driver(&i801_driver);
557 MODULE_AUTHOR ("Frodo Looijaard <frodol@dds.nl>, "
558 "Philip Edelbrock <phil@netroedge.com>, "
559 "and Mark D. Studebaker <mdsxyz123@yahoo.com>");
560 MODULE_DESCRIPTION("I801 SMBus driver");
561 MODULE_LICENSE("GPL");
563 module_init(i2c_i801_init);
564 module_exit(i2c_i801_exit);