2 * Permission is hereby granted, free of charge, to any person obtaining a
3 * copy of this software and associated documentation files (the "Software"),
4 * to deal in the Software without restriction, including without limitation
5 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
6 * and/or sell copies of the Software, and to permit persons to whom the
7 * Software is furnished to do so, subject to the following conditions:
9 * The above copyright notice and this permission notice shall be included in
10 * all copies or substantial portions of the Software.
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
18 * OTHER DEALINGS IN THE SOFTWARE.
20 * Authors: Rafał Miłecki <zajec5@gmail.com>
21 * Alex Deucher <alexdeucher@gmail.com>
28 #include <linux/acpi.h>
30 #include <linux/power_supply.h>
31 #include <linux/hwmon.h>
32 #include <linux/hwmon-sysfs.h>
34 #define RADEON_IDLE_LOOP_MS 100
35 #define RADEON_RECLOCK_DELAY_MS 200
36 #define RADEON_WAIT_VBLANK_TIMEOUT 200
37 #define RADEON_WAIT_IDLE_TIMEOUT 200
39 static const char *radeon_pm_state_type_name[5] = {
47 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
48 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
49 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
50 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
51 static void radeon_pm_update_profile(struct radeon_device *rdev);
52 static void radeon_pm_set_clocks(struct radeon_device *rdev);
54 #define ACPI_AC_CLASS "ac_adapter"
57 static int radeon_acpi_event(struct notifier_block *nb,
61 struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
62 struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
64 if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
65 if (power_supply_is_system_supplied() > 0)
66 DRM_DEBUG_DRIVER("pm: AC\n");
68 DRM_DEBUG_DRIVER("pm: DC\n");
70 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
71 if (rdev->pm.profile == PM_PROFILE_AUTO) {
72 mutex_lock(&rdev->pm.mutex);
73 radeon_pm_update_profile(rdev);
74 radeon_pm_set_clocks(rdev);
75 mutex_unlock(&rdev->pm.mutex);
84 static void radeon_pm_update_profile(struct radeon_device *rdev)
86 switch (rdev->pm.profile) {
87 case PM_PROFILE_DEFAULT:
88 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
91 if (power_supply_is_system_supplied() > 0) {
92 if (rdev->pm.active_crtc_count > 1)
93 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
95 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
97 if (rdev->pm.active_crtc_count > 1)
98 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
100 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
104 if (rdev->pm.active_crtc_count > 1)
105 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
107 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
110 if (rdev->pm.active_crtc_count > 1)
111 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
113 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
115 case PM_PROFILE_HIGH:
116 if (rdev->pm.active_crtc_count > 1)
117 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
119 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
123 if (rdev->pm.active_crtc_count == 0) {
124 rdev->pm.requested_power_state_index =
125 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
126 rdev->pm.requested_clock_mode_index =
127 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
129 rdev->pm.requested_power_state_index =
130 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
131 rdev->pm.requested_clock_mode_index =
132 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
136 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
138 struct radeon_bo *bo, *n;
140 if (list_empty(&rdev->gem.objects))
143 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
144 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
145 ttm_bo_unmap_virtual(&bo->tbo);
149 static void radeon_sync_with_vblank(struct radeon_device *rdev)
151 if (rdev->pm.active_crtcs) {
152 rdev->pm.vblank_sync = false;
154 rdev->irq.vblank_queue, rdev->pm.vblank_sync,
155 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
159 static void radeon_set_power_state(struct radeon_device *rdev)
162 bool misc_after = false;
164 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
165 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
168 if (radeon_gui_idle(rdev)) {
169 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
170 clock_info[rdev->pm.requested_clock_mode_index].sclk;
171 if (sclk > rdev->pm.default_sclk)
172 sclk = rdev->pm.default_sclk;
174 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
175 clock_info[rdev->pm.requested_clock_mode_index].mclk;
176 if (mclk > rdev->pm.default_mclk)
177 mclk = rdev->pm.default_mclk;
179 /* upvolt before raising clocks, downvolt after lowering clocks */
180 if (sclk < rdev->pm.current_sclk)
183 radeon_sync_with_vblank(rdev);
185 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
186 if (!radeon_pm_in_vbl(rdev))
190 radeon_pm_prepare(rdev);
193 /* voltage, pcie lanes, etc.*/
194 radeon_pm_misc(rdev);
196 /* set engine clock */
197 if (sclk != rdev->pm.current_sclk) {
198 radeon_pm_debug_check_in_vbl(rdev, false);
199 radeon_set_engine_clock(rdev, sclk);
200 radeon_pm_debug_check_in_vbl(rdev, true);
201 rdev->pm.current_sclk = sclk;
202 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
205 /* set memory clock */
206 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
207 radeon_pm_debug_check_in_vbl(rdev, false);
208 radeon_set_memory_clock(rdev, mclk);
209 radeon_pm_debug_check_in_vbl(rdev, true);
210 rdev->pm.current_mclk = mclk;
211 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
215 /* voltage, pcie lanes, etc.*/
216 radeon_pm_misc(rdev);
218 radeon_pm_finish(rdev);
220 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
221 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
223 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
226 static void radeon_pm_set_clocks(struct radeon_device *rdev)
230 /* no need to take locks, etc. if nothing's going to change */
231 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
232 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
235 mutex_lock(&rdev->ddev->struct_mutex);
236 mutex_lock(&rdev->vram_mutex);
237 mutex_lock(&rdev->cp.mutex);
239 /* gui idle int has issues on older chips it seems */
240 if (rdev->family >= CHIP_R600) {
241 if (rdev->irq.installed) {
242 /* wait for GPU idle */
243 rdev->pm.gui_idle = false;
244 rdev->irq.gui_idle = true;
245 radeon_irq_set(rdev);
246 wait_event_interruptible_timeout(
247 rdev->irq.idle_queue, rdev->pm.gui_idle,
248 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
249 rdev->irq.gui_idle = false;
250 radeon_irq_set(rdev);
253 if (rdev->cp.ready) {
254 struct radeon_fence *fence;
255 radeon_ring_alloc(rdev, 64);
256 radeon_fence_create(rdev, &fence);
257 radeon_fence_emit(rdev, fence);
258 radeon_ring_commit(rdev);
259 radeon_fence_wait(fence, false);
260 radeon_fence_unref(&fence);
263 radeon_unmap_vram_bos(rdev);
265 if (rdev->irq.installed) {
266 for (i = 0; i < rdev->num_crtc; i++) {
267 if (rdev->pm.active_crtcs & (1 << i)) {
268 rdev->pm.req_vblank |= (1 << i);
269 drm_vblank_get(rdev->ddev, i);
274 radeon_set_power_state(rdev);
276 if (rdev->irq.installed) {
277 for (i = 0; i < rdev->num_crtc; i++) {
278 if (rdev->pm.req_vblank & (1 << i)) {
279 rdev->pm.req_vblank &= ~(1 << i);
280 drm_vblank_put(rdev->ddev, i);
285 /* update display watermarks based on new power state */
286 radeon_update_bandwidth_info(rdev);
287 if (rdev->pm.active_crtc_count)
288 radeon_bandwidth_update(rdev);
290 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
292 mutex_unlock(&rdev->cp.mutex);
293 mutex_unlock(&rdev->vram_mutex);
294 mutex_unlock(&rdev->ddev->struct_mutex);
297 static void radeon_pm_print_states(struct radeon_device *rdev)
300 struct radeon_power_state *power_state;
301 struct radeon_pm_clock_info *clock_info;
303 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
304 for (i = 0; i < rdev->pm.num_power_states; i++) {
305 power_state = &rdev->pm.power_state[i];
306 DRM_DEBUG_DRIVER("State %d: %s\n", i,
307 radeon_pm_state_type_name[power_state->type]);
308 if (i == rdev->pm.default_power_state_index)
309 DRM_DEBUG_DRIVER("\tDefault");
310 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
311 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
312 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
313 DRM_DEBUG_DRIVER("\tSingle display only\n");
314 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
315 for (j = 0; j < power_state->num_clock_modes; j++) {
316 clock_info = &(power_state->clock_info[j]);
317 if (rdev->flags & RADEON_IS_IGP)
318 DRM_DEBUG_DRIVER("\t\t%d e: %d%s\n",
320 clock_info->sclk * 10,
321 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
323 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d%s\n",
325 clock_info->sclk * 10,
326 clock_info->mclk * 10,
327 clock_info->voltage.voltage,
328 clock_info->flags & RADEON_PM_MODE_NO_DISPLAY ? "\tNo display only" : "");
333 static ssize_t radeon_get_pm_profile(struct device *dev,
334 struct device_attribute *attr,
337 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
338 struct radeon_device *rdev = ddev->dev_private;
339 int cp = rdev->pm.profile;
341 return snprintf(buf, PAGE_SIZE, "%s\n",
342 (cp == PM_PROFILE_AUTO) ? "auto" :
343 (cp == PM_PROFILE_LOW) ? "low" :
344 (cp == PM_PROFILE_MID) ? "mid" :
345 (cp == PM_PROFILE_HIGH) ? "high" : "default");
348 static ssize_t radeon_set_pm_profile(struct device *dev,
349 struct device_attribute *attr,
353 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
354 struct radeon_device *rdev = ddev->dev_private;
356 mutex_lock(&rdev->pm.mutex);
357 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
358 if (strncmp("default", buf, strlen("default")) == 0)
359 rdev->pm.profile = PM_PROFILE_DEFAULT;
360 else if (strncmp("auto", buf, strlen("auto")) == 0)
361 rdev->pm.profile = PM_PROFILE_AUTO;
362 else if (strncmp("low", buf, strlen("low")) == 0)
363 rdev->pm.profile = PM_PROFILE_LOW;
364 else if (strncmp("mid", buf, strlen("mid")) == 0)
365 rdev->pm.profile = PM_PROFILE_MID;
366 else if (strncmp("high", buf, strlen("high")) == 0)
367 rdev->pm.profile = PM_PROFILE_HIGH;
372 radeon_pm_update_profile(rdev);
373 radeon_pm_set_clocks(rdev);
378 mutex_unlock(&rdev->pm.mutex);
383 static ssize_t radeon_get_pm_method(struct device *dev,
384 struct device_attribute *attr,
387 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
388 struct radeon_device *rdev = ddev->dev_private;
389 int pm = rdev->pm.pm_method;
391 return snprintf(buf, PAGE_SIZE, "%s\n",
392 (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
395 static ssize_t radeon_set_pm_method(struct device *dev,
396 struct device_attribute *attr,
400 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
401 struct radeon_device *rdev = ddev->dev_private;
404 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
405 mutex_lock(&rdev->pm.mutex);
406 rdev->pm.pm_method = PM_METHOD_DYNPM;
407 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
408 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
409 mutex_unlock(&rdev->pm.mutex);
410 } else if (strncmp("profile", buf, strlen("profile")) == 0) {
411 mutex_lock(&rdev->pm.mutex);
413 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
414 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
415 rdev->pm.pm_method = PM_METHOD_PROFILE;
416 mutex_unlock(&rdev->pm.mutex);
417 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
422 radeon_pm_compute_clocks(rdev);
427 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
428 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
430 static ssize_t radeon_hwmon_show_temp(struct device *dev,
431 struct device_attribute *attr,
434 struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
435 struct radeon_device *rdev = ddev->dev_private;
438 switch (rdev->pm.int_thermal_type) {
439 case THERMAL_TYPE_RV6XX:
440 temp = rv6xx_get_temp(rdev);
442 case THERMAL_TYPE_RV770:
443 temp = rv770_get_temp(rdev);
445 case THERMAL_TYPE_EVERGREEN:
446 case THERMAL_TYPE_NI:
447 temp = evergreen_get_temp(rdev);
449 case THERMAL_TYPE_SUMO:
450 temp = sumo_get_temp(rdev);
457 return snprintf(buf, PAGE_SIZE, "%d\n", temp);
460 static ssize_t radeon_hwmon_show_name(struct device *dev,
461 struct device_attribute *attr,
464 return sprintf(buf, "radeon\n");
467 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
468 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
470 static struct attribute *hwmon_attributes[] = {
471 &sensor_dev_attr_temp1_input.dev_attr.attr,
472 &sensor_dev_attr_name.dev_attr.attr,
476 static const struct attribute_group hwmon_attrgroup = {
477 .attrs = hwmon_attributes,
480 static int radeon_hwmon_init(struct radeon_device *rdev)
484 rdev->pm.int_hwmon_dev = NULL;
486 switch (rdev->pm.int_thermal_type) {
487 case THERMAL_TYPE_RV6XX:
488 case THERMAL_TYPE_RV770:
489 case THERMAL_TYPE_EVERGREEN:
490 case THERMAL_TYPE_SUMO:
491 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
492 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
493 err = PTR_ERR(rdev->pm.int_hwmon_dev);
495 "Unable to register hwmon device: %d\n", err);
498 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
499 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
503 "Unable to create hwmon sysfs file: %d\n", err);
504 hwmon_device_unregister(rdev->dev);
514 static void radeon_hwmon_fini(struct radeon_device *rdev)
516 if (rdev->pm.int_hwmon_dev) {
517 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
518 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
522 void radeon_pm_suspend(struct radeon_device *rdev)
524 mutex_lock(&rdev->pm.mutex);
525 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
526 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
527 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
529 mutex_unlock(&rdev->pm.mutex);
531 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
534 void radeon_pm_resume(struct radeon_device *rdev)
536 /* set up the default clocks if the MC ucode is loaded */
537 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
538 if (rdev->pm.default_vddc)
539 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
540 SET_VOLTAGE_TYPE_ASIC_VDDC);
541 if (rdev->pm.default_vddci)
542 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
543 SET_VOLTAGE_TYPE_ASIC_VDDCI);
544 if (rdev->pm.default_sclk)
545 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
546 if (rdev->pm.default_mclk)
547 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
549 /* asic init will reset the default power state */
550 mutex_lock(&rdev->pm.mutex);
551 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
552 rdev->pm.current_clock_mode_index = 0;
553 rdev->pm.current_sclk = rdev->pm.default_sclk;
554 rdev->pm.current_mclk = rdev->pm.default_mclk;
555 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
556 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
557 if (rdev->pm.pm_method == PM_METHOD_DYNPM
558 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
559 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
560 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
561 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
563 mutex_unlock(&rdev->pm.mutex);
564 radeon_pm_compute_clocks(rdev);
567 int radeon_pm_init(struct radeon_device *rdev)
571 /* default to profile method */
572 rdev->pm.pm_method = PM_METHOD_PROFILE;
573 rdev->pm.profile = PM_PROFILE_DEFAULT;
574 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
575 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
576 rdev->pm.dynpm_can_upclock = true;
577 rdev->pm.dynpm_can_downclock = true;
578 rdev->pm.default_sclk = rdev->clock.default_sclk;
579 rdev->pm.default_mclk = rdev->clock.default_mclk;
580 rdev->pm.current_sclk = rdev->clock.default_sclk;
581 rdev->pm.current_mclk = rdev->clock.default_mclk;
582 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
585 if (rdev->is_atom_bios)
586 radeon_atombios_get_power_modes(rdev);
588 radeon_combios_get_power_modes(rdev);
589 radeon_pm_print_states(rdev);
590 radeon_pm_init_profile(rdev);
591 /* set up the default clocks if the MC ucode is loaded */
592 if (ASIC_IS_DCE5(rdev) && rdev->mc_fw) {
593 if (rdev->pm.default_vddc)
594 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
595 SET_VOLTAGE_TYPE_ASIC_VDDC);
596 if (rdev->pm.default_sclk)
597 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
598 if (rdev->pm.default_mclk)
599 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
603 /* set up the internal thermal sensor if applicable */
604 ret = radeon_hwmon_init(rdev);
608 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
610 if (rdev->pm.num_power_states > 1) {
611 /* where's the best place to put these? */
612 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
614 DRM_ERROR("failed to create device file for power profile\n");
615 ret = device_create_file(rdev->dev, &dev_attr_power_method);
617 DRM_ERROR("failed to create device file for power method\n");
620 rdev->acpi_nb.notifier_call = radeon_acpi_event;
621 register_acpi_notifier(&rdev->acpi_nb);
623 if (radeon_debugfs_pm_init(rdev)) {
624 DRM_ERROR("Failed to register debugfs file for PM!\n");
627 DRM_INFO("radeon: power management initialized\n");
633 void radeon_pm_fini(struct radeon_device *rdev)
635 if (rdev->pm.num_power_states > 1) {
636 mutex_lock(&rdev->pm.mutex);
637 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
638 rdev->pm.profile = PM_PROFILE_DEFAULT;
639 radeon_pm_update_profile(rdev);
640 radeon_pm_set_clocks(rdev);
641 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
642 /* reset default clocks */
643 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
644 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
645 radeon_pm_set_clocks(rdev);
647 mutex_unlock(&rdev->pm.mutex);
649 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
651 device_remove_file(rdev->dev, &dev_attr_power_profile);
652 device_remove_file(rdev->dev, &dev_attr_power_method);
654 unregister_acpi_notifier(&rdev->acpi_nb);
658 if (rdev->pm.power_state)
659 kfree(rdev->pm.power_state);
661 radeon_hwmon_fini(rdev);
664 void radeon_pm_compute_clocks(struct radeon_device *rdev)
666 struct drm_device *ddev = rdev->ddev;
667 struct drm_crtc *crtc;
668 struct radeon_crtc *radeon_crtc;
670 if (rdev->pm.num_power_states < 2)
673 mutex_lock(&rdev->pm.mutex);
675 rdev->pm.active_crtcs = 0;
676 rdev->pm.active_crtc_count = 0;
677 list_for_each_entry(crtc,
678 &ddev->mode_config.crtc_list, head) {
679 radeon_crtc = to_radeon_crtc(crtc);
680 if (radeon_crtc->enabled) {
681 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
682 rdev->pm.active_crtc_count++;
686 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
687 radeon_pm_update_profile(rdev);
688 radeon_pm_set_clocks(rdev);
689 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
690 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
691 if (rdev->pm.active_crtc_count > 1) {
692 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
693 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
695 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
696 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
697 radeon_pm_get_dynpm_state(rdev);
698 radeon_pm_set_clocks(rdev);
700 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
702 } else if (rdev->pm.active_crtc_count == 1) {
703 /* TODO: Increase clocks if needed for current mode */
705 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
706 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
707 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
708 radeon_pm_get_dynpm_state(rdev);
709 radeon_pm_set_clocks(rdev);
711 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
712 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
713 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
714 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
715 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
716 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
717 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
719 } else { /* count == 0 */
720 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
721 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
723 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
724 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
725 radeon_pm_get_dynpm_state(rdev);
726 radeon_pm_set_clocks(rdev);
732 mutex_unlock(&rdev->pm.mutex);
735 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
737 int crtc, vpos, hpos, vbl_status;
740 /* Iterate over all active crtc's. All crtc's must be in vblank,
741 * otherwise return in_vbl == false.
743 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
744 if (rdev->pm.active_crtcs & (1 << crtc)) {
745 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
746 if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
747 !(vbl_status & DRM_SCANOUTPOS_INVBL))
755 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
758 bool in_vbl = radeon_pm_in_vbl(rdev);
761 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
762 finish ? "exit" : "entry");
766 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
768 struct radeon_device *rdev;
770 rdev = container_of(work, struct radeon_device,
771 pm.dynpm_idle_work.work);
773 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
774 mutex_lock(&rdev->pm.mutex);
775 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
776 unsigned long irq_flags;
777 int not_processed = 0;
779 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
780 if (!list_empty(&rdev->fence_drv.emited)) {
781 struct list_head *ptr;
782 list_for_each(ptr, &rdev->fence_drv.emited) {
783 /* count up to 3, that's enought info */
784 if (++not_processed >= 3)
788 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
790 if (not_processed >= 3) { /* should upclock */
791 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
792 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
793 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
794 rdev->pm.dynpm_can_upclock) {
795 rdev->pm.dynpm_planned_action =
796 DYNPM_ACTION_UPCLOCK;
797 rdev->pm.dynpm_action_timeout = jiffies +
798 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
800 } else if (not_processed == 0) { /* should downclock */
801 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
802 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
803 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
804 rdev->pm.dynpm_can_downclock) {
805 rdev->pm.dynpm_planned_action =
806 DYNPM_ACTION_DOWNCLOCK;
807 rdev->pm.dynpm_action_timeout = jiffies +
808 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
812 /* Note, radeon_pm_set_clocks is called with static_switch set
813 * to false since we want to wait for vbl to avoid flicker.
815 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
816 jiffies > rdev->pm.dynpm_action_timeout) {
817 radeon_pm_get_dynpm_state(rdev);
818 radeon_pm_set_clocks(rdev);
821 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
822 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
824 mutex_unlock(&rdev->pm.mutex);
825 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
831 #if defined(CONFIG_DEBUG_FS)
833 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
835 struct drm_info_node *node = (struct drm_info_node *) m->private;
836 struct drm_device *dev = node->minor->dev;
837 struct radeon_device *rdev = dev->dev_private;
839 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
840 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
841 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
842 if (rdev->asic->get_memory_clock)
843 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
844 if (rdev->pm.current_vddc)
845 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
846 if (rdev->asic->get_pcie_lanes)
847 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
852 static struct drm_info_list radeon_pm_info_list[] = {
853 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
857 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
859 #if defined(CONFIG_DEBUG_FS)
860 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));