drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include <drm/drmP.h>
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #include "atom.h"
  27 #include <linux/power_supply.h>
  28 #include <linux/hwmon.h>
  29 #include <linux/hwmon-sysfs.h>
  30
  31 #define RADEON_IDLE_LOOP_MS 100
  32 #define RADEON_RECLOCK_DELAY_MS 200
  33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  34
  35 static const char *radeon_pm_state_type_name[5] = {
  36         "",
  37         "Powersave",
  38         "Battery",
  39         "Balanced",
  40         "Performance",
  41 };
  42
  43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  47 static void radeon_pm_update_profile(struct radeon_device *rdev);
  48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  49
  50 int radeon_pm_get_type_index(struct radeon_device *rdev,
  51                              enum radeon_pm_state_type ps_type,
  52                              int instance)
  53 {
  54         int i;
  55         int found_instance = -1;
  56
  57         for (i = 0; i < rdev->pm.num_power_states; i++) {
  58                 if (rdev->pm.power_state[i].type == ps_type) {
  59                         found_instance++;
  60                         if (found_instance == instance)
  61                                 return i;
  62                 }
  63         }
  64         /* return default if no match */
  65         return rdev->pm.default_power_state_index;
  66 }
  67
  68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
  69 {
  70         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  71                 if (rdev->pm.profile == PM_PROFILE_AUTO) {
  72                         mutex_lock(&rdev->pm.mutex);
  73                         radeon_pm_update_profile(rdev);
  74                         radeon_pm_set_clocks(rdev);
  75                         mutex_unlock(&rdev->pm.mutex);
  76                 }
  77         }
  78 }
  79
  80 static void radeon_pm_update_profile(struct radeon_device *rdev)
  81 {
  82         switch (rdev->pm.profile) {
  83         case PM_PROFILE_DEFAULT:
  84                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  85                 break;
  86         case PM_PROFILE_AUTO:
  87                 if (power_supply_is_system_supplied() > 0) {
  88                         if (rdev->pm.active_crtc_count > 1)
  89                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  90                         else
  91                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  92                 } else {
  93                         if (rdev->pm.active_crtc_count > 1)
  94                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
  95                         else
  96                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
  97                 }
  98                 break;
  99         case PM_PROFILE_LOW:
 100                 if (rdev->pm.active_crtc_count > 1)
 101                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 102                 else
 103                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 104                 break;
 105         case PM_PROFILE_MID:
 106                 if (rdev->pm.active_crtc_count > 1)
 107                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 108                 else
 109                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 110                 break;
 111         case PM_PROFILE_HIGH:
 112                 if (rdev->pm.active_crtc_count > 1)
 113                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 114                 else
 115                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 116                 break;
 117         }
 118
 119         if (rdev->pm.active_crtc_count == 0) {
 120                 rdev->pm.requested_power_state_index =
 121                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 122                 rdev->pm.requested_clock_mode_index =
 123                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 124         } else {
 125                 rdev->pm.requested_power_state_index =
 126                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 127                 rdev->pm.requested_clock_mode_index =
 128                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 129         }
 130 }
 131
 132 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 133 {
 134         struct radeon_bo *bo, *n;
 135
 136         if (list_empty(&rdev->gem.objects))
 137                 return;
 138
 139         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 140                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 141                         ttm_bo_unmap_virtual(&bo->tbo);
 142         }
 143 }
 144
 145 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 146 {
 147         if (rdev->pm.active_crtcs) {
 148                 rdev->pm.vblank_sync = false;
 149                 wait_event_timeout(
 150                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 151                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 152         }
 153 }
 154
 155 static void radeon_set_power_state(struct radeon_device *rdev)
 156 {
 157         u32 sclk, mclk;
 158         bool misc_after = false;
 159
 160         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 161             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 162                 return;
 163
 164         if (radeon_gui_idle(rdev)) {
 165                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 166                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 167                 if (sclk > rdev->pm.default_sclk)
 168                         sclk = rdev->pm.default_sclk;
 169
 170                 /* starting with BTC, there is one state that is used for both
 171                  * MH and SH.  Difference is that we always use the high clock index for
 172                  * mclk.
 173                  */
 174                 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
 175                     (rdev->family >= CHIP_BARTS) &&
 176                     rdev->pm.active_crtc_count &&
 177                     ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
 178                      (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
 179                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 180                                 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
 181                 else
 182                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 183                                 clock_info[rdev->pm.requested_clock_mode_index].mclk;
 184
 185                 if (mclk > rdev->pm.default_mclk)
 186                         mclk = rdev->pm.default_mclk;
 187
 188                 /* upvolt before raising clocks, downvolt after lowering clocks */
 189                 if (sclk < rdev->pm.current_sclk)
 190                         misc_after = true;
 191
 192                 radeon_sync_with_vblank(rdev);
 193
 194                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 195                         if (!radeon_pm_in_vbl(rdev))
 196                                 return;
 197                 }
 198
 199                 radeon_pm_prepare(rdev);
 200
 201                 if (!misc_after)
 202                         /* voltage, pcie lanes, etc.*/
 203                         radeon_pm_misc(rdev);
 204
 205                 /* set engine clock */
 206                 if (sclk != rdev->pm.current_sclk) {
 207                         radeon_pm_debug_check_in_vbl(rdev, false);
 208                         radeon_set_engine_clock(rdev, sclk);
 209                         radeon_pm_debug_check_in_vbl(rdev, true);
 210                         rdev->pm.current_sclk = sclk;
 211                         DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
 212                 }
 213
 214                 /* set memory clock */
 215                 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 216                         radeon_pm_debug_check_in_vbl(rdev, false);
 217                         radeon_set_memory_clock(rdev, mclk);
 218                         radeon_pm_debug_check_in_vbl(rdev, true);
 219                         rdev->pm.current_mclk = mclk;
 220                         DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
 221                 }
 222
 223                 if (misc_after)
 224                         /* voltage, pcie lanes, etc.*/
 225                         radeon_pm_misc(rdev);
 226
 227                 radeon_pm_finish(rdev);
 228
 229                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 230                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 231         } else
 232                 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 233 }
 234
 235 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 236 {
 237         int i;
 238
 239         /* no need to take locks, etc. if nothing's going to change */
 240         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 241             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 242                 return;
 243
 244         mutex_lock(&rdev->ddev->struct_mutex);
 245         down_write(&rdev->pm.mclk_lock);
 246         mutex_lock(&rdev->ring_lock);
 247
 248         /* wait for the rings to drain */
 249         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 250                 struct radeon_ring *ring = &rdev->ring[i];
 251                 if (ring->ready)
 252                         radeon_fence_wait_empty_locked(rdev, i);
 253         }
 254
 255         radeon_unmap_vram_bos(rdev);
 256
 257         if (rdev->irq.installed) {
 258                 for (i = 0; i < rdev->num_crtc; i++) {
 259                         if (rdev->pm.active_crtcs & (1 << i)) {
 260                                 rdev->pm.req_vblank |= (1 << i);
 261                                 drm_vblank_get(rdev->ddev, i);
 262                         }
 263                 }
 264         }
 265
 266         radeon_set_power_state(rdev);
 267
 268         if (rdev->irq.installed) {
 269                 for (i = 0; i < rdev->num_crtc; i++) {
 270                         if (rdev->pm.req_vblank & (1 << i)) {
 271                                 rdev->pm.req_vblank &= ~(1 << i);
 272                                 drm_vblank_put(rdev->ddev, i);
 273                         }
 274                 }
 275         }
 276
 277         /* update display watermarks based on new power state */
 278         radeon_update_bandwidth_info(rdev);
 279         if (rdev->pm.active_crtc_count)
 280                 radeon_bandwidth_update(rdev);
 281
 282         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 283
 284         mutex_unlock(&rdev->ring_lock);
 285         up_write(&rdev->pm.mclk_lock);
 286         mutex_unlock(&rdev->ddev->struct_mutex);
 287 }
 288
 289 static void radeon_pm_print_states(struct radeon_device *rdev)
 290 {
 291         int i, j;
 292         struct radeon_power_state *power_state;
 293         struct radeon_pm_clock_info *clock_info;
 294
 295         DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
 296         for (i = 0; i < rdev->pm.num_power_states; i++) {
 297                 power_state = &rdev->pm.power_state[i];
 298                 DRM_DEBUG_DRIVER("State %d: %s\n", i,
 299                         radeon_pm_state_type_name[power_state->type]);
 300                 if (i == rdev->pm.default_power_state_index)
 301                         DRM_DEBUG_DRIVER("\tDefault");
 302                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 303                         DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 304                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 305                         DRM_DEBUG_DRIVER("\tSingle display only\n");
 306                 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 307                 for (j = 0; j < power_state->num_clock_modes; j++) {
 308                         clock_info = &(power_state->clock_info[j]);
 309                         if (rdev->flags & RADEON_IS_IGP)
 310                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
 311                                                  j,
 312                                                  clock_info->sclk * 10);
 313                         else
 314                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
 315                                                  j,
 316                                                  clock_info->sclk * 10,
 317                                                  clock_info->mclk * 10,
 318                                                  clock_info->voltage.voltage);
 319                 }
 320         }
 321 }
 322
 323 static ssize_t radeon_get_pm_profile(struct device *dev,
 324                                      struct device_attribute *attr,
 325                                      char *buf)
 326 {
 327         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 328         struct radeon_device *rdev = ddev->dev_private;
 329         int cp = rdev->pm.profile;
 330
 331         return snprintf(buf, PAGE_SIZE, "%s\n",
 332                         (cp == PM_PROFILE_AUTO) ? "auto" :
 333                         (cp == PM_PROFILE_LOW) ? "low" :
 334                         (cp == PM_PROFILE_MID) ? "mid" :
 335                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 336 }
 337
 338 static ssize_t radeon_set_pm_profile(struct device *dev,
 339                                      struct device_attribute *attr,
 340                                      const char *buf,
 341                                      size_t count)
 342 {
 343         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 344         struct radeon_device *rdev = ddev->dev_private;
 345
 346         mutex_lock(&rdev->pm.mutex);
 347         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 348                 if (strncmp("default", buf, strlen("default")) == 0)
 349                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 350                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 351                         rdev->pm.profile = PM_PROFILE_AUTO;
 352                 else if (strncmp("low", buf, strlen("low")) == 0)
 353                         rdev->pm.profile = PM_PROFILE_LOW;
 354                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 355                         rdev->pm.profile = PM_PROFILE_MID;
 356                 else if (strncmp("high", buf, strlen("high")) == 0)
 357                         rdev->pm.profile = PM_PROFILE_HIGH;
 358                 else {
 359                         count = -EINVAL;
 360                         goto fail;
 361                 }
 362                 radeon_pm_update_profile(rdev);
 363                 radeon_pm_set_clocks(rdev);
 364         } else
 365                 count = -EINVAL;
 366
 367 fail:
 368         mutex_unlock(&rdev->pm.mutex);
 369
 370         return count;
 371 }
 372
 373 static ssize_t radeon_get_pm_method(struct device *dev,
 374                                     struct device_attribute *attr,
 375                                     char *buf)
 376 {
 377         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 378         struct radeon_device *rdev = ddev->dev_private;
 379         int pm = rdev->pm.pm_method;
 380
 381         return snprintf(buf, PAGE_SIZE, "%s\n",
 382                         (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
 383 }
 384
 385 static ssize_t radeon_set_pm_method(struct device *dev,
 386                                     struct device_attribute *attr,
 387                                     const char *buf,
 388                                     size_t count)
 389 {
 390         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 391         struct radeon_device *rdev = ddev->dev_private;
 392
 393
 394         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 395                 mutex_lock(&rdev->pm.mutex);
 396                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 397                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 398                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 399                 mutex_unlock(&rdev->pm.mutex);
 400         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 401                 mutex_lock(&rdev->pm.mutex);
 402                 /* disable dynpm */
 403                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 404                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 405                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 406                 mutex_unlock(&rdev->pm.mutex);
 407                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 408         } else {
 409                 count = -EINVAL;
 410                 goto fail;
 411         }
 412         radeon_pm_compute_clocks(rdev);
 413 fail:
 414         return count;
 415 }
 416
 417 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 418 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 419
 420 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 421                                       struct device_attribute *attr,
 422                                       char *buf)
 423 {
 424         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 425         struct radeon_device *rdev = ddev->dev_private;
 426         int temp;
 427
 428         switch (rdev->pm.int_thermal_type) {
 429         case THERMAL_TYPE_RV6XX:
 430                 temp = rv6xx_get_temp(rdev);
 431                 break;
 432         case THERMAL_TYPE_RV770:
 433                 temp = rv770_get_temp(rdev);
 434                 break;
 435         case THERMAL_TYPE_EVERGREEN:
 436         case THERMAL_TYPE_NI:
 437                 temp = evergreen_get_temp(rdev);
 438                 break;
 439         case THERMAL_TYPE_SUMO:
 440                 temp = sumo_get_temp(rdev);
 441                 break;
 442         case THERMAL_TYPE_SI:
 443                 temp = si_get_temp(rdev);
 444                 break;
 445         default:
 446                 temp = 0;
 447                 break;
 448         }
 449
 450         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 451 }
 452
 453 static ssize_t radeon_hwmon_show_name(struct device *dev,
 454                                       struct device_attribute *attr,
 455                                       char *buf)
 456 {
 457         return sprintf(buf, "radeon\n");
 458 }
 459
 460 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 461 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
 462
 463 static struct attribute *hwmon_attributes[] = {
 464         &sensor_dev_attr_temp1_input.dev_attr.attr,
 465         &sensor_dev_attr_name.dev_attr.attr,
 466         NULL
 467 };
 468
 469 static const struct attribute_group hwmon_attrgroup = {
 470         .attrs = hwmon_attributes,
 471 };
 472
 473 static int radeon_hwmon_init(struct radeon_device *rdev)
 474 {
 475         int err = 0;
 476
 477         rdev->pm.int_hwmon_dev = NULL;
 478
 479         switch (rdev->pm.int_thermal_type) {
 480         case THERMAL_TYPE_RV6XX:
 481         case THERMAL_TYPE_RV770:
 482         case THERMAL_TYPE_EVERGREEN:
 483         case THERMAL_TYPE_NI:
 484         case THERMAL_TYPE_SUMO:
 485         case THERMAL_TYPE_SI:
 486                 /* No support for TN yet */
 487                 if (rdev->family == CHIP_ARUBA)
 488                         return err;
 489                 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
 490                 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
 491                         err = PTR_ERR(rdev->pm.int_hwmon_dev);
 492                         dev_err(rdev->dev,
 493                                 "Unable to register hwmon device: %d\n", err);
 494                         break;
 495                 }
 496                 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
 497                 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
 498                                          &hwmon_attrgroup);
 499                 if (err) {
 500                         dev_err(rdev->dev,
 501                                 "Unable to create hwmon sysfs file: %d\n", err);
 502                         hwmon_device_unregister(rdev->dev);
 503                 }
 504                 break;
 505         default:
 506                 break;
 507         }
 508
 509         return err;
 510 }
 511
 512 static void radeon_hwmon_fini(struct radeon_device *rdev)
 513 {
 514         if (rdev->pm.int_hwmon_dev) {
 515                 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
 516                 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
 517         }
 518 }
 519
 520 void radeon_pm_suspend(struct radeon_device *rdev)
 521 {
 522         mutex_lock(&rdev->pm.mutex);
 523         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 524                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
 525                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
 526         }
 527         mutex_unlock(&rdev->pm.mutex);
 528
 529         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 530 }
 531
 532 void radeon_pm_resume(struct radeon_device *rdev)
 533 {
 534         /* set up the default clocks if the MC ucode is loaded */
 535         if ((rdev->family >= CHIP_BARTS) &&
 536             (rdev->family <= CHIP_CAYMAN) &&
 537             rdev->mc_fw) {
 538                 if (rdev->pm.default_vddc)
 539                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 540                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
 541                 if (rdev->pm.default_vddci)
 542                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 543                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
 544                 if (rdev->pm.default_sclk)
 545                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 546                 if (rdev->pm.default_mclk)
 547                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 548         }
 549         /* asic init will reset the default power state */
 550         mutex_lock(&rdev->pm.mutex);
 551         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 552         rdev->pm.current_clock_mode_index = 0;
 553         rdev->pm.current_sclk = rdev->pm.default_sclk;
 554         rdev->pm.current_mclk = rdev->pm.default_mclk;
 555         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
 556         rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
 557         if (rdev->pm.pm_method == PM_METHOD_DYNPM
 558             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
 559                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 560                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 561                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 562         }
 563         mutex_unlock(&rdev->pm.mutex);
 564         radeon_pm_compute_clocks(rdev);
 565 }
 566
 567 int radeon_pm_init(struct radeon_device *rdev)
 568 {
 569         int ret;
 570
 571         /* default to profile method */
 572         rdev->pm.pm_method = PM_METHOD_PROFILE;
 573         rdev->pm.profile = PM_PROFILE_DEFAULT;
 574         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 575         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 576         rdev->pm.dynpm_can_upclock = true;
 577         rdev->pm.dynpm_can_downclock = true;
 578         rdev->pm.default_sclk = rdev->clock.default_sclk;
 579         rdev->pm.default_mclk = rdev->clock.default_mclk;
 580         rdev->pm.current_sclk = rdev->clock.default_sclk;
 581         rdev->pm.current_mclk = rdev->clock.default_mclk;
 582         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
 583
 584         if (rdev->bios) {
 585                 if (rdev->is_atom_bios)
 586                         radeon_atombios_get_power_modes(rdev);
 587                 else
 588                         radeon_combios_get_power_modes(rdev);
 589                 radeon_pm_print_states(rdev);
 590                 radeon_pm_init_profile(rdev);
 591                 /* set up the default clocks if the MC ucode is loaded */
 592                 if ((rdev->family >= CHIP_BARTS) &&
 593                     (rdev->family <= CHIP_CAYMAN) &&
 594                     rdev->mc_fw) {
 595                         if (rdev->pm.default_vddc)
 596                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 597                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
 598                         if (rdev->pm.default_vddci)
 599                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 600                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
 601                         if (rdev->pm.default_sclk)
 602                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 603                         if (rdev->pm.default_mclk)
 604                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 605                 }
 606         }
 607
 608         /* set up the internal thermal sensor if applicable */
 609         ret = radeon_hwmon_init(rdev);
 610         if (ret)
 611                 return ret;
 612
 613         INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
 614
 615         if (rdev->pm.num_power_states > 1) {
 616                 /* where's the best place to put these? */
 617                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
 618                 if (ret)
 619                         DRM_ERROR("failed to create device file for power profile\n");
 620                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
 621                 if (ret)
 622                         DRM_ERROR("failed to create device file for power method\n");
 623
 624                 if (radeon_debugfs_pm_init(rdev)) {
 625                         DRM_ERROR("Failed to register debugfs file for PM!\n");
 626                 }
 627
 628                 DRM_INFO("radeon: power management initialized\n");
 629         }
 630
 631         return 0;
 632 }
 633
 634 void radeon_pm_fini(struct radeon_device *rdev)
 635 {
 636         if (rdev->pm.num_power_states > 1) {
 637                 mutex_lock(&rdev->pm.mutex);
 638                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 639                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 640                         radeon_pm_update_profile(rdev);
 641                         radeon_pm_set_clocks(rdev);
 642                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 643                         /* reset default clocks */
 644                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 645                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 646                         radeon_pm_set_clocks(rdev);
 647                 }
 648                 mutex_unlock(&rdev->pm.mutex);
 649
 650                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 651
 652                 device_remove_file(rdev->dev, &dev_attr_power_profile);
 653                 device_remove_file(rdev->dev, &dev_attr_power_method);
 654         }
 655
 656         if (rdev->pm.power_state)
 657                 kfree(rdev->pm.power_state);
 658
 659         radeon_hwmon_fini(rdev);
 660 }
 661
 662 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 663 {
 664         struct drm_device *ddev = rdev->ddev;
 665         struct drm_crtc *crtc;
 666         struct radeon_crtc *radeon_crtc;
 667
 668         if (rdev->pm.num_power_states < 2)
 669                 return;
 670
 671         mutex_lock(&rdev->pm.mutex);
 672
 673         rdev->pm.active_crtcs = 0;
 674         rdev->pm.active_crtc_count = 0;
 675         list_for_each_entry(crtc,
 676                 &ddev->mode_config.crtc_list, head) {
 677                 radeon_crtc = to_radeon_crtc(crtc);
 678                 if (radeon_crtc->enabled) {
 679                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 680                         rdev->pm.active_crtc_count++;
 681                 }
 682         }
 683
 684         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 685                 radeon_pm_update_profile(rdev);
 686                 radeon_pm_set_clocks(rdev);
 687         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 688                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
 689                         if (rdev->pm.active_crtc_count > 1) {
 690                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 691                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 692
 693                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 694                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 695                                         radeon_pm_get_dynpm_state(rdev);
 696                                         radeon_pm_set_clocks(rdev);
 697
 698                                         DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
 699                                 }
 700                         } else if (rdev->pm.active_crtc_count == 1) {
 701                                 /* TODO: Increase clocks if needed for current mode */
 702
 703                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
 704                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 705                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
 706                                         radeon_pm_get_dynpm_state(rdev);
 707                                         radeon_pm_set_clocks(rdev);
 708
 709                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 710                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 711                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
 712                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 713                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 714                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 715                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
 716                                 }
 717                         } else { /* count == 0 */
 718                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
 719                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 720
 721                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
 722                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
 723                                         radeon_pm_get_dynpm_state(rdev);
 724                                         radeon_pm_set_clocks(rdev);
 725                                 }
 726                         }
 727                 }
 728         }
 729
 730         mutex_unlock(&rdev->pm.mutex);
 731 }
 732
 733 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
 734 {
 735         int  crtc, vpos, hpos, vbl_status;
 736         bool in_vbl = true;
 737
 738         /* Iterate over all active crtc's. All crtc's must be in vblank,
 739          * otherwise return in_vbl == false.
 740          */
 741         for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
 742                 if (rdev->pm.active_crtcs & (1 << crtc)) {
 743                         vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
 744                         if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
 745                             !(vbl_status & DRM_SCANOUTPOS_INVBL))
 746                                 in_vbl = false;
 747                 }
 748         }
 749
 750         return in_vbl;
 751 }
 752
 753 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 754 {
 755         u32 stat_crtc = 0;
 756         bool in_vbl = radeon_pm_in_vbl(rdev);
 757
 758         if (in_vbl == false)
 759                 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
 760                          finish ? "exit" : "entry");
 761         return in_vbl;
 762 }
 763
 764 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
 765 {
 766         struct radeon_device *rdev;
 767         int resched;
 768         rdev = container_of(work, struct radeon_device,
 769                                 pm.dynpm_idle_work.work);
 770
 771         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 772         mutex_lock(&rdev->pm.mutex);
 773         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 774                 int not_processed = 0;
 775                 int i;
 776
 777                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 778                         struct radeon_ring *ring = &rdev->ring[i];
 779
 780                         if (ring->ready) {
 781                                 not_processed += radeon_fence_count_emitted(rdev, i);
 782                                 if (not_processed >= 3)
 783                                         break;
 784                         }
 785                 }
 786
 787                 if (not_processed >= 3) { /* should upclock */
 788                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
 789                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 790                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 791                                    rdev->pm.dynpm_can_upclock) {
 792                                 rdev->pm.dynpm_planned_action =
 793                                         DYNPM_ACTION_UPCLOCK;
 794                                 rdev->pm.dynpm_action_timeout = jiffies +
 795                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 796                         }
 797                 } else if (not_processed == 0) { /* should downclock */
 798                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
 799                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 800                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 801                                    rdev->pm.dynpm_can_downclock) {
 802                                 rdev->pm.dynpm_planned_action =
 803                                         DYNPM_ACTION_DOWNCLOCK;
 804                                 rdev->pm.dynpm_action_timeout = jiffies +
 805                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 806                         }
 807                 }
 808
 809                 /* Note, radeon_pm_set_clocks is called with static_switch set
 810                  * to false since we want to wait for vbl to avoid flicker.
 811                  */
 812                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
 813                     jiffies > rdev->pm.dynpm_action_timeout) {
 814                         radeon_pm_get_dynpm_state(rdev);
 815                         radeon_pm_set_clocks(rdev);
 816                 }
 817
 818                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 819                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 820         }
 821         mutex_unlock(&rdev->pm.mutex);
 822         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 823 }
 824
 825 /*
 826  * Debugfs info
 827  */
 828 #if defined(CONFIG_DEBUG_FS)
 829
 830 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 831 {
 832         struct drm_info_node *node = (struct drm_info_node *) m->private;
 833         struct drm_device *dev = node->minor->dev;
 834         struct radeon_device *rdev = dev->dev_private;
 835
 836         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
 837         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 838         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
 839         if (rdev->asic->pm.get_memory_clock)
 840                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 841         if (rdev->pm.current_vddc)
 842                 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
 843         if (rdev->asic->pm.get_pcie_lanes)
 844                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 845
 846         return 0;
 847 }
 848
 849 static struct drm_info_list radeon_pm_info_list[] = {
 850         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 851 };
 852 #endif
 853
 854 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 855 {
 856 #if defined(CONFIG_DEBUG_FS)
 857         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 858 #else
 859         return 0;
 860 #endif
 861 }