drivers/gpu/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon.h"
  30 #include <drm/radeon_drm.h>
  31 #include "radeon_asic.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35 #include <linux/pm_runtime.h>
  36
  37 #if defined(CONFIG_VGA_SWITCHEROO)
  38 bool radeon_has_atpx(void);
  39 #else
  40 static inline bool radeon_has_atpx(void) { return false; }
  41 #endif
  42
  43 /**
  44  * radeon_driver_unload_kms - Main unload function for KMS.
  45  *
  46  * @dev: drm dev pointer
  47  *
  48  * This is the main unload function for KMS (all asics).
  49  * It calls radeon_modeset_fini() to tear down the
  50  * displays, and radeon_device_fini() to tear down
  51  * the rest of the device (CP, writeback, etc.).
  52  * Returns 0 on success.
  53  */
  54 int radeon_driver_unload_kms(struct drm_device *dev)
  55 {
  56         struct radeon_device *rdev = dev->dev_private;
  57
  58         if (rdev == NULL)
  59                 return 0;
  60
  61         if (rdev->rmmio == NULL)
  62                 goto done_free;
  63
  64         pm_runtime_get_sync(dev->dev);
  65
  66         radeon_acpi_fini(rdev);
  67
  68         radeon_modeset_fini(rdev);
  69         radeon_device_fini(rdev);
  70
  71 done_free:
  72         kfree(rdev);
  73         dev->dev_private = NULL;
  74         return 0;
  75 }
  76
  77 /**
  78  * radeon_driver_load_kms - Main load function for KMS.
  79  *
  80  * @dev: drm dev pointer
  81  * @flags: device flags
  82  *
  83  * This is the main load function for KMS (all asics).
  84  * It calls radeon_device_init() to set up the non-display
  85  * parts of the chip (asic init, CP, writeback, etc.), and
  86  * radeon_modeset_init() to set up the display parts
  87  * (crtcs, encoders, hotplug detect, etc.).
  88  * Returns 0 on success, error on failure.
  89  */
  90 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  91 {
  92         struct radeon_device *rdev;
  93         int r, acpi_status;
  94
  95         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  96         if (rdev == NULL) {
  97                 return -ENOMEM;
  98         }
  99         dev->dev_private = (void *)rdev;
 100
 101         /* update BUS flag */
 102         if (drm_pci_device_is_agp(dev)) {
 103                 flags |= RADEON_IS_AGP;
 104         } else if (pci_is_pcie(dev->pdev)) {
 105                 flags |= RADEON_IS_PCIE;
 106         } else {
 107                 flags |= RADEON_IS_PCI;
 108         }
 109
 110         if ((radeon_runtime_pm != 0) &&
 111             radeon_has_atpx() &&
 112             ((flags & RADEON_IS_IGP) == 0))
 113                 flags |= RADEON_IS_PX;
 114
 115         /* radeon_device_init should report only fatal error
 116          * like memory allocation failure or iomapping failure,
 117          * or memory manager initialization failure, it must
 118          * properly initialize the GPU MC controller and permit
 119          * VRAM allocation
 120          */
 121         r = radeon_device_init(rdev, dev, dev->pdev, flags);
 122         if (r) {
 123                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 124                 goto out;
 125         }
 126
 127         /* Again modeset_init should fail only on fatal error
 128          * otherwise it should provide enough functionalities
 129          * for shadowfb to run
 130          */
 131         r = radeon_modeset_init(rdev);
 132         if (r)
 133                 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
 134
 135         /* Call ACPI methods: require modeset init
 136          * but failure is not fatal
 137          */
 138         if (!r) {
 139                 acpi_status = radeon_acpi_init(rdev);
 140                 if (acpi_status)
 141                 dev_dbg(&dev->pdev->dev,
 142                                 "Error during ACPI methods call\n");
 143         }
 144
 145         if (radeon_is_px(dev)) {
 146                 pm_runtime_use_autosuspend(dev->dev);
 147                 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
 148                 pm_runtime_set_active(dev->dev);
 149                 pm_runtime_allow(dev->dev);
 150                 pm_runtime_mark_last_busy(dev->dev);
 151                 pm_runtime_put_autosuspend(dev->dev);
 152         }
 153
 154 out:
 155         if (r)
 156                 radeon_driver_unload_kms(dev);
 157
 158
 159         return r;
 160 }
 161
 162 /**
 163  * radeon_set_filp_rights - Set filp right.
 164  *
 165  * @dev: drm dev pointer
 166  * @owner: drm file
 167  * @applier: drm file
 168  * @value: value
 169  *
 170  * Sets the filp rights for the device (all asics).
 171  */
 172 static void radeon_set_filp_rights(struct drm_device *dev,
 173                                    struct drm_file **owner,
 174                                    struct drm_file *applier,
 175                                    uint32_t *value)
 176 {
 177         mutex_lock(&dev->struct_mutex);
 178         if (*value == 1) {
 179                 /* wants rights */
 180                 if (!*owner)
 181                         *owner = applier;
 182         } else if (*value == 0) {
 183                 /* revokes rights */
 184                 if (*owner == applier)
 185                         *owner = NULL;
 186         }
 187         *value = *owner == applier ? 1 : 0;
 188         mutex_unlock(&dev->struct_mutex);
 189 }
 190
 191 /*
 192  * Userspace get information ioctl
 193  */
 194 /**
 195  * radeon_info_ioctl - answer a device specific request.
 196  *
 197  * @rdev: radeon device pointer
 198  * @data: request object
 199  * @filp: drm filp
 200  *
 201  * This function is used to pass device specific parameters to the userspace
 202  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 203  * etc. (all asics).
 204  * Returns 0 on success, -EINVAL on failure.
 205  */
 206 static int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 207 {
 208         struct radeon_device *rdev = dev->dev_private;
 209         struct drm_radeon_info *info = data;
 210         struct radeon_mode_info *minfo = &rdev->mode_info;
 211         uint32_t *value, value_tmp, *value_ptr, value_size;
 212         uint64_t value64;
 213         struct drm_crtc *crtc;
 214         int i, found;
 215
 216         value_ptr = (uint32_t *)((unsigned long)info->value);
 217         value = &value_tmp;
 218         value_size = sizeof(uint32_t);
 219
 220         switch (info->request) {
 221         case RADEON_INFO_DEVICE_ID:
 222                 *value = dev->pdev->device;
 223                 break;
 224         case RADEON_INFO_NUM_GB_PIPES:
 225                 *value = rdev->num_gb_pipes;
 226                 break;
 227         case RADEON_INFO_NUM_Z_PIPES:
 228                 *value = rdev->num_z_pipes;
 229                 break;
 230         case RADEON_INFO_ACCEL_WORKING:
 231                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
 232                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
 233                         *value = false;
 234                 else
 235                         *value = rdev->accel_working;
 236                 break;
 237         case RADEON_INFO_CRTC_FROM_ID:
 238                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 239                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 240                         return -EFAULT;
 241                 }
 242                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
 243                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 244                         if (crtc && crtc->base.id == *value) {
 245                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 246                                 *value = radeon_crtc->crtc_id;
 247                                 found = 1;
 248                                 break;
 249                         }
 250                 }
 251                 if (!found) {
 252                         DRM_DEBUG_KMS("unknown crtc id %d\n", *value);
 253                         return -EINVAL;
 254                 }
 255                 break;
 256         case RADEON_INFO_ACCEL_WORKING2:
 257                 *value = rdev->accel_working;
 258                 break;
 259         case RADEON_INFO_TILING_CONFIG:
 260                 if (rdev->family >= CHIP_BONAIRE)
 261                         *value = rdev->config.cik.tile_config;
 262                 else if (rdev->family >= CHIP_TAHITI)
 263                         *value = rdev->config.si.tile_config;
 264                 else if (rdev->family >= CHIP_CAYMAN)
 265                         *value = rdev->config.cayman.tile_config;
 266                 else if (rdev->family >= CHIP_CEDAR)
 267                         *value = rdev->config.evergreen.tile_config;
 268                 else if (rdev->family >= CHIP_RV770)
 269                         *value = rdev->config.rv770.tile_config;
 270                 else if (rdev->family >= CHIP_R600)
 271                         *value = rdev->config.r600.tile_config;
 272                 else {
 273                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
 274                         return -EINVAL;
 275                 }
 276                 break;
 277         case RADEON_INFO_WANT_HYPERZ:
 278                 /* The "value" here is both an input and output parameter.
 279                  * If the input value is 1, filp requests hyper-z access.
 280                  * If the input value is 0, filp revokes its hyper-z access.
 281                  *
 282                  * When returning, the value is 1 if filp owns hyper-z access,
 283                  * 0 otherwise. */
 284                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 285                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 286                         return -EFAULT;
 287                 }
 288                 if (*value >= 2) {
 289                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", *value);
 290                         return -EINVAL;
 291                 }
 292                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, value);
 293                 break;
 294         case RADEON_INFO_WANT_CMASK:
 295                 /* The same logic as Hyper-Z. */
 296                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 297                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 298                         return -EFAULT;
 299                 }
 300                 if (*value >= 2) {
 301                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", *value);
 302                         return -EINVAL;
 303                 }
 304                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, value);
 305                 break;
 306         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
 307                 /* return clock value in KHz */
 308                 if (rdev->asic->get_xclk)
 309                         *value = radeon_get_xclk(rdev) * 10;
 310                 else
 311                         *value = rdev->clock.spll.reference_freq * 10;
 312                 break;
 313         case RADEON_INFO_NUM_BACKENDS:
 314                 if (rdev->family >= CHIP_BONAIRE)
 315                         *value = rdev->config.cik.max_backends_per_se *
 316                                 rdev->config.cik.max_shader_engines;
 317                 else if (rdev->family >= CHIP_TAHITI)
 318                         *value = rdev->config.si.max_backends_per_se *
 319                                 rdev->config.si.max_shader_engines;
 320                 else if (rdev->family >= CHIP_CAYMAN)
 321                         *value = rdev->config.cayman.max_backends_per_se *
 322                                 rdev->config.cayman.max_shader_engines;
 323                 else if (rdev->family >= CHIP_CEDAR)
 324                         *value = rdev->config.evergreen.max_backends;
 325                 else if (rdev->family >= CHIP_RV770)
 326                         *value = rdev->config.rv770.max_backends;
 327                 else if (rdev->family >= CHIP_R600)
 328                         *value = rdev->config.r600.max_backends;
 329                 else {
 330                         return -EINVAL;
 331                 }
 332                 break;
 333         case RADEON_INFO_NUM_TILE_PIPES:
 334                 if (rdev->family >= CHIP_BONAIRE)
 335                         *value = rdev->config.cik.max_tile_pipes;
 336                 else if (rdev->family >= CHIP_TAHITI)
 337                         *value = rdev->config.si.max_tile_pipes;
 338                 else if (rdev->family >= CHIP_CAYMAN)
 339                         *value = rdev->config.cayman.max_tile_pipes;
 340                 else if (rdev->family >= CHIP_CEDAR)
 341                         *value = rdev->config.evergreen.max_tile_pipes;
 342                 else if (rdev->family >= CHIP_RV770)
 343                         *value = rdev->config.rv770.max_tile_pipes;
 344                 else if (rdev->family >= CHIP_R600)
 345                         *value = rdev->config.r600.max_tile_pipes;
 346                 else {
 347                         return -EINVAL;
 348                 }
 349                 break;
 350         case RADEON_INFO_FUSION_GART_WORKING:
 351                 *value = 1;
 352                 break;
 353         case RADEON_INFO_BACKEND_MAP:
 354                 if (rdev->family >= CHIP_BONAIRE)
 355                         *value = rdev->config.cik.backend_map;
 356                 else if (rdev->family >= CHIP_TAHITI)
 357                         *value = rdev->config.si.backend_map;
 358                 else if (rdev->family >= CHIP_CAYMAN)
 359                         *value = rdev->config.cayman.backend_map;
 360                 else if (rdev->family >= CHIP_CEDAR)
 361                         *value = rdev->config.evergreen.backend_map;
 362                 else if (rdev->family >= CHIP_RV770)
 363                         *value = rdev->config.rv770.backend_map;
 364                 else if (rdev->family >= CHIP_R600)
 365                         *value = rdev->config.r600.backend_map;
 366                 else {
 367                         return -EINVAL;
 368                 }
 369                 break;
 370         case RADEON_INFO_VA_START:
 371                 /* this is where we report if vm is supported or not */
 372                 if (rdev->family < CHIP_CAYMAN)
 373                         return -EINVAL;
 374                 *value = RADEON_VA_RESERVED_SIZE;
 375                 break;
 376         case RADEON_INFO_IB_VM_MAX_SIZE:
 377                 /* this is where we report if vm is supported or not */
 378                 if (rdev->family < CHIP_CAYMAN)
 379                         return -EINVAL;
 380                 *value = RADEON_IB_VM_MAX_SIZE;
 381                 break;
 382         case RADEON_INFO_MAX_PIPES:
 383                 if (rdev->family >= CHIP_BONAIRE)
 384                         *value = rdev->config.cik.max_cu_per_sh;
 385                 else if (rdev->family >= CHIP_TAHITI)
 386                         *value = rdev->config.si.max_cu_per_sh;
 387                 else if (rdev->family >= CHIP_CAYMAN)
 388                         *value = rdev->config.cayman.max_pipes_per_simd;
 389                 else if (rdev->family >= CHIP_CEDAR)
 390                         *value = rdev->config.evergreen.max_pipes;
 391                 else if (rdev->family >= CHIP_RV770)
 392                         *value = rdev->config.rv770.max_pipes;
 393                 else if (rdev->family >= CHIP_R600)
 394                         *value = rdev->config.r600.max_pipes;
 395                 else {
 396                         return -EINVAL;
 397                 }
 398                 break;
 399         case RADEON_INFO_TIMESTAMP:
 400                 if (rdev->family < CHIP_R600) {
 401                         DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
 402                         return -EINVAL;
 403                 }
 404                 value = (uint32_t*)&value64;
 405                 value_size = sizeof(uint64_t);
 406                 value64 = radeon_get_gpu_clock_counter(rdev);
 407                 break;
 408         case RADEON_INFO_MAX_SE:
 409                 if (rdev->family >= CHIP_BONAIRE)
 410                         *value = rdev->config.cik.max_shader_engines;
 411                 else if (rdev->family >= CHIP_TAHITI)
 412                         *value = rdev->config.si.max_shader_engines;
 413                 else if (rdev->family >= CHIP_CAYMAN)
 414                         *value = rdev->config.cayman.max_shader_engines;
 415                 else if (rdev->family >= CHIP_CEDAR)
 416                         *value = rdev->config.evergreen.num_ses;
 417                 else
 418                         *value = 1;
 419                 break;
 420         case RADEON_INFO_MAX_SH_PER_SE:
 421                 if (rdev->family >= CHIP_BONAIRE)
 422                         *value = rdev->config.cik.max_sh_per_se;
 423                 else if (rdev->family >= CHIP_TAHITI)
 424                         *value = rdev->config.si.max_sh_per_se;
 425                 else
 426                         return -EINVAL;
 427                 break;
 428         case RADEON_INFO_FASTFB_WORKING:
 429                 *value = rdev->fastfb_working;
 430                 break;
 431         case RADEON_INFO_RING_WORKING:
 432                 if (copy_from_user(value, value_ptr, sizeof(uint32_t))) {
 433                         DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 434                         return -EFAULT;
 435                 }
 436                 switch (*value) {
 437                 case RADEON_CS_RING_GFX:
 438                 case RADEON_CS_RING_COMPUTE:
 439                         *value = rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready;
 440                         break;
 441                 case RADEON_CS_RING_DMA:
 442                         *value = rdev->ring[R600_RING_TYPE_DMA_INDEX].ready;
 443                         *value |= rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready;
 444                         break;
 445                 case RADEON_CS_RING_UVD:
 446                         *value = rdev->ring[R600_RING_TYPE_UVD_INDEX].ready;
 447                         break;
 448                 case RADEON_CS_RING_VCE:
 449                         *value = rdev->ring[TN_RING_TYPE_VCE1_INDEX].ready;
 450                         break;
 451                 default:
 452                         return -EINVAL;
 453                 }
 454                 break;
 455         case RADEON_INFO_SI_TILE_MODE_ARRAY:
 456                 if (rdev->family >= CHIP_BONAIRE) {
 457                         value = rdev->config.cik.tile_mode_array;
 458                         value_size = sizeof(uint32_t)*32;
 459                 } else if (rdev->family >= CHIP_TAHITI) {
 460                         value = rdev->config.si.tile_mode_array;
 461                         value_size = sizeof(uint32_t)*32;
 462                 } else {
 463                         DRM_DEBUG_KMS("tile mode array is si+ only!\n");
 464                         return -EINVAL;
 465                 }
 466                 break;
 467         case RADEON_INFO_CIK_MACROTILE_MODE_ARRAY:
 468                 if (rdev->family >= CHIP_BONAIRE) {
 469                         value = rdev->config.cik.macrotile_mode_array;
 470                         value_size = sizeof(uint32_t)*16;
 471                 } else {
 472                         DRM_DEBUG_KMS("macrotile mode array is cik+ only!\n");
 473                         return -EINVAL;
 474                 }
 475                 break;
 476         case RADEON_INFO_SI_CP_DMA_COMPUTE:
 477                 *value = 1;
 478                 break;
 479         case RADEON_INFO_SI_BACKEND_ENABLED_MASK:
 480                 if (rdev->family >= CHIP_BONAIRE) {
 481                         *value = rdev->config.cik.backend_enable_mask;
 482                 } else if (rdev->family >= CHIP_TAHITI) {
 483                         *value = rdev->config.si.backend_enable_mask;
 484                 } else {
 485                         DRM_DEBUG_KMS("BACKEND_ENABLED_MASK is si+ only!\n");
 486                 }
 487                 break;
 488         case RADEON_INFO_MAX_SCLK:
 489                 if ((rdev->pm.pm_method == PM_METHOD_DPM) &&
 490                     rdev->pm.dpm_enabled)
 491                         *value = rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10;
 492                 else
 493                         *value = rdev->pm.default_sclk * 10;
 494                 break;
 495         case RADEON_INFO_VCE_FW_VERSION:
 496                 *value = rdev->vce.fw_version;
 497                 break;
 498         case RADEON_INFO_VCE_FB_VERSION:
 499                 *value = rdev->vce.fb_version;
 500                 break;
 501         case RADEON_INFO_NUM_BYTES_MOVED:
 502                 value = (uint32_t*)&value64;
 503                 value_size = sizeof(uint64_t);
 504                 value64 = atomic64_read(&rdev->num_bytes_moved);
 505                 break;
 506         case RADEON_INFO_VRAM_USAGE:
 507                 value = (uint32_t*)&value64;
 508                 value_size = sizeof(uint64_t);
 509                 value64 = atomic64_read(&rdev->vram_usage);
 510                 break;
 511         case RADEON_INFO_GTT_USAGE:
 512                 value = (uint32_t*)&value64;
 513                 value_size = sizeof(uint64_t);
 514                 value64 = atomic64_read(&rdev->gtt_usage);
 515                 break;
 516         default:
 517                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
 518                 return -EINVAL;
 519         }
 520         if (copy_to_user(value_ptr, (char*)value, value_size)) {
 521                 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
 522                 return -EFAULT;
 523         }
 524         return 0;
 525 }
 526
 527
 528 /*
 529  * Outdated mess for old drm with Xorg being in charge (void function now).
 530  */
 531 /**
 532  * radeon_driver_firstopen_kms - drm callback for last close
 533  *
 534  * @dev: drm dev pointer
 535  *
 536  * Switch vga switcheroo state after last close (all asics).
 537  */
 538 void radeon_driver_lastclose_kms(struct drm_device *dev)
 539 {
 540         vga_switcheroo_process_delayed_switch();
 541 }
 542
 543 /**
 544  * radeon_driver_open_kms - drm callback for open
 545  *
 546  * @dev: drm dev pointer
 547  * @file_priv: drm file
 548  *
 549  * On device open, init vm on cayman+ (all asics).
 550  * Returns 0 on success, error on failure.
 551  */
 552 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 553 {
 554         struct radeon_device *rdev = dev->dev_private;
 555         int r;
 556
 557         file_priv->driver_priv = NULL;
 558
 559         r = pm_runtime_get_sync(dev->dev);
 560         if (r < 0)
 561                 return r;
 562
 563         /* new gpu have virtual address space support */
 564         if (rdev->family >= CHIP_CAYMAN) {
 565                 struct radeon_fpriv *fpriv;
 566                 struct radeon_bo_va *bo_va;
 567                 int r;
 568
 569                 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 570                 if (unlikely(!fpriv)) {
 571                         return -ENOMEM;
 572                 }
 573
 574                 r = radeon_vm_init(rdev, &fpriv->vm);
 575                 if (r) {
 576                         kfree(fpriv);
 577                         return r;
 578                 }
 579
 580                 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 581                 if (r) {
 582                         radeon_vm_fini(rdev, &fpriv->vm);
 583                         kfree(fpriv);
 584                         return r;
 585                 }
 586
 587                 /* map the ib pool buffer read only into
 588                  * virtual address space */
 589                 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
 590                                          rdev->ring_tmp_bo.bo);
 591                 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
 592                                           RADEON_VM_PAGE_READABLE |
 593                                           RADEON_VM_PAGE_SNOOPED);
 594
 595                 radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
 596                 if (r) {
 597                         radeon_vm_fini(rdev, &fpriv->vm);
 598                         kfree(fpriv);
 599                         return r;
 600                 }
 601
 602                 file_priv->driver_priv = fpriv;
 603         }
 604
 605         pm_runtime_mark_last_busy(dev->dev);
 606         pm_runtime_put_autosuspend(dev->dev);
 607         return 0;
 608 }
 609
 610 /**
 611  * radeon_driver_postclose_kms - drm callback for post close
 612  *
 613  * @dev: drm dev pointer
 614  * @file_priv: drm file
 615  *
 616  * On device post close, tear down vm on cayman+ (all asics).
 617  */
 618 void radeon_driver_postclose_kms(struct drm_device *dev,
 619                                  struct drm_file *file_priv)
 620 {
 621         struct radeon_device *rdev = dev->dev_private;
 622
 623         /* new gpu have virtual address space support */
 624         if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
 625                 struct radeon_fpriv *fpriv = file_priv->driver_priv;
 626                 struct radeon_bo_va *bo_va;
 627                 int r;
 628
 629                 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 630                 if (!r) {
 631                         bo_va = radeon_vm_bo_find(&fpriv->vm,
 632                                                   rdev->ring_tmp_bo.bo);
 633                         if (bo_va)
 634                                 radeon_vm_bo_rmv(rdev, bo_va);
 635                         radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
 636                 }
 637
 638                 radeon_vm_fini(rdev, &fpriv->vm);
 639                 kfree(fpriv);
 640                 file_priv->driver_priv = NULL;
 641         }
 642 }
 643
 644 /**
 645  * radeon_driver_preclose_kms - drm callback for pre close
 646  *
 647  * @dev: drm dev pointer
 648  * @file_priv: drm file
 649  *
 650  * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
 651  * (all asics).
 652  */
 653 void radeon_driver_preclose_kms(struct drm_device *dev,
 654                                 struct drm_file *file_priv)
 655 {
 656         struct radeon_device *rdev = dev->dev_private;
 657         if (rdev->hyperz_filp == file_priv)
 658                 rdev->hyperz_filp = NULL;
 659         if (rdev->cmask_filp == file_priv)
 660                 rdev->cmask_filp = NULL;
 661         radeon_uvd_free_handles(rdev, file_priv);
 662         radeon_vce_free_handles(rdev, file_priv);
 663 }
 664
 665 /*
 666  * VBlank related functions.
 667  */
 668 /**
 669  * radeon_get_vblank_counter_kms - get frame count
 670  *
 671  * @dev: drm dev pointer
 672  * @crtc: crtc to get the frame count from
 673  *
 674  * Gets the frame count on the requested crtc (all asics).
 675  * Returns frame count on success, -EINVAL on failure.
 676  */
 677 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
 678 {
 679         struct radeon_device *rdev = dev->dev_private;
 680
 681         if (crtc < 0 || crtc >= rdev->num_crtc) {
 682                 DRM_ERROR("Invalid crtc %d\n", crtc);
 683                 return -EINVAL;
 684         }
 685
 686         return radeon_get_vblank_counter(rdev, crtc);
 687 }
 688
 689 /**
 690  * radeon_enable_vblank_kms - enable vblank interrupt
 691  *
 692  * @dev: drm dev pointer
 693  * @crtc: crtc to enable vblank interrupt for
 694  *
 695  * Enable the interrupt on the requested crtc (all asics).
 696  * Returns 0 on success, -EINVAL on failure.
 697  */
 698 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 699 {
 700         struct radeon_device *rdev = dev->dev_private;
 701         unsigned long irqflags;
 702         int r;
 703
 704         if (crtc < 0 || crtc >= rdev->num_crtc) {
 705                 DRM_ERROR("Invalid crtc %d\n", crtc);
 706                 return -EINVAL;
 707         }
 708
 709         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 710         rdev->irq.crtc_vblank_int[crtc] = true;
 711         r = radeon_irq_set(rdev);
 712         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 713         return r;
 714 }
 715
 716 /**
 717  * radeon_disable_vblank_kms - disable vblank interrupt
 718  *
 719  * @dev: drm dev pointer
 720  * @crtc: crtc to disable vblank interrupt for
 721  *
 722  * Disable the interrupt on the requested crtc (all asics).
 723  */
 724 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 725 {
 726         struct radeon_device *rdev = dev->dev_private;
 727         unsigned long irqflags;
 728
 729         if (crtc < 0 || crtc >= rdev->num_crtc) {
 730                 DRM_ERROR("Invalid crtc %d\n", crtc);
 731                 return;
 732         }
 733
 734         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 735         rdev->irq.crtc_vblank_int[crtc] = false;
 736         radeon_irq_set(rdev);
 737         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 738 }
 739
 740 /**
 741  * radeon_get_vblank_timestamp_kms - get vblank timestamp
 742  *
 743  * @dev: drm dev pointer
 744  * @crtc: crtc to get the timestamp for
 745  * @max_error: max error
 746  * @vblank_time: time value
 747  * @flags: flags passed to the driver
 748  *
 749  * Gets the timestamp on the requested crtc based on the
 750  * scanout position.  (all asics).
 751  * Returns postive status flags on success, negative error on failure.
 752  */
 753 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
 754                                     int *max_error,
 755                                     struct timeval *vblank_time,
 756                                     unsigned flags)
 757 {
 758         struct drm_crtc *drmcrtc;
 759         struct radeon_device *rdev = dev->dev_private;
 760
 761         if (crtc < 0 || crtc >= dev->num_crtcs) {
 762                 DRM_ERROR("Invalid crtc %d\n", crtc);
 763                 return -EINVAL;
 764         }
 765
 766         /* Get associated drm_crtc: */
 767         drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
 768
 769         /* Helper routine in DRM core does all the work: */
 770         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
 771                                                      vblank_time, flags,
 772                                                      drmcrtc, &drmcrtc->hwmode);
 773 }
 774
 775 #define KMS_INVALID_IOCTL(name)                                         \
 776 static int name(struct drm_device *dev, void *data, struct drm_file     \
 777                 *file_priv)                                             \
 778 {                                                                       \
 779         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
 780         return -EINVAL;                                                 \
 781 }
 782
 783 /*
 784  * All these ioctls are invalid in kms world.
 785  */
 786 KMS_INVALID_IOCTL(radeon_cp_init_kms)
 787 KMS_INVALID_IOCTL(radeon_cp_start_kms)
 788 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
 789 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
 790 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
 791 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
 792 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
 793 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
 794 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
 795 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
 796 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
 797 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
 798 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
 799 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
 800 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
 801 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
 802 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
 803 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
 804 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
 805 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
 806 KMS_INVALID_IOCTL(radeon_mem_free_kms)
 807 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
 808 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
 809 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
 810 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
 811 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
 812 KMS_INVALID_IOCTL(radeon_surface_free_kms)
 813
 814
 815 const struct drm_ioctl_desc radeon_ioctls_kms[] = {
 816         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 817         DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 818         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 819         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 820         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
 821         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
 822         DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
 823         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
 824         DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
 825         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
 826         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
 827         DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
 828         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
 829         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
 830         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 831         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
 832         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
 833         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
 834         DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
 835         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
 836         DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
 837         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 838         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
 839         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
 840         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
 841         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
 842         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
 843         /* KMS */
 844         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 845         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 846         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 847         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 848         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
 849         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
 850         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 851         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 852         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 853         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 854         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 855         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 856         DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 857         DRM_IOCTL_DEF_DRV(RADEON_GEM_OP, radeon_gem_op_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
 858 };
 859 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);