drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "atom.h"
  31 #include <linux/backlight.h>
  32
  33 extern int atom_debug;
  34
  35 static u8
  36 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  37 {
  38         u8 backlight_level;
  39         u32 bios_2_scratch;
  40
  41         if (rdev->family >= CHIP_R600)
  42                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  43         else
  44                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  45
  46         backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  47                            ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  48
  49         return backlight_level;
  50 }
  51
  52 static void
  53 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  54                                        u8 backlight_level)
  55 {
  56         u32 bios_2_scratch;
  57
  58         if (rdev->family >= CHIP_R600)
  59                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  60         else
  61                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  62
  63         bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  64         bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  65                            ATOM_S2_CURRENT_BL_LEVEL_MASK);
  66
  67         if (rdev->family >= CHIP_R600)
  68                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  69         else
  70                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  71 }
  72
  73 u8
  74 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  75 {
  76         struct drm_device *dev = radeon_encoder->base.dev;
  77         struct radeon_device *rdev = dev->dev_private;
  78
  79         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  80                 return 0;
  81
  82         return radeon_atom_get_backlight_level_from_reg(rdev);
  83 }
  84
  85 void
  86 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  87 {
  88         struct drm_encoder *encoder = &radeon_encoder->base;
  89         struct drm_device *dev = radeon_encoder->base.dev;
  90         struct radeon_device *rdev = dev->dev_private;
  91         struct radeon_encoder_atom_dig *dig;
  92         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  93         int index;
  94
  95         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  96                 return;
  97
  98         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
  99             radeon_encoder->enc_priv) {
 100                 dig = radeon_encoder->enc_priv;
 101                 dig->backlight_level = level;
 102                 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 103
 104                 switch (radeon_encoder->encoder_id) {
 105                 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 106                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 107                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 108                         if (dig->backlight_level == 0) {
 109                                 args.ucAction = ATOM_LCD_BLOFF;
 110                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 111                         } else {
 112                                 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 113                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 114                                 args.ucAction = ATOM_LCD_BLON;
 115                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 116                         }
 117                         break;
 118                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 119                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 120                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 121                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 122                         if (dig->backlight_level == 0)
 123                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 124                         else {
 125                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 126                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 127                         }
 128                         break;
 129                 default:
 130                         break;
 131                 }
 132         }
 133 }
 134
 135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 136
 137 static u8 radeon_atom_bl_level(struct backlight_device *bd)
 138 {
 139         u8 level;
 140
 141         /* Convert brightness to hardware level */
 142         if (bd->props.brightness < 0)
 143                 level = 0;
 144         else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 145                 level = RADEON_MAX_BL_LEVEL;
 146         else
 147                 level = bd->props.brightness;
 148
 149         return level;
 150 }
 151
 152 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 153 {
 154         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 155         struct radeon_encoder *radeon_encoder = pdata->encoder;
 156
 157         atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 158
 159         return 0;
 160 }
 161
 162 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 163 {
 164         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 165         struct radeon_encoder *radeon_encoder = pdata->encoder;
 166         struct drm_device *dev = radeon_encoder->base.dev;
 167         struct radeon_device *rdev = dev->dev_private;
 168
 169         return radeon_atom_get_backlight_level_from_reg(rdev);
 170 }
 171
 172 static const struct backlight_ops radeon_atom_backlight_ops = {
 173         .get_brightness = radeon_atom_backlight_get_brightness,
 174         .update_status  = radeon_atom_backlight_update_status,
 175 };
 176
 177 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 178                                 struct drm_connector *drm_connector)
 179 {
 180         struct drm_device *dev = radeon_encoder->base.dev;
 181         struct radeon_device *rdev = dev->dev_private;
 182         struct backlight_device *bd;
 183         struct backlight_properties props;
 184         struct radeon_backlight_privdata *pdata;
 185         struct radeon_encoder_atom_dig *dig;
 186         u8 backlight_level;
 187
 188         if (!radeon_encoder->enc_priv)
 189                 return;
 190
 191         if (!rdev->is_atom_bios)
 192                 return;
 193
 194         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 195                 return;
 196
 197         pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 198         if (!pdata) {
 199                 DRM_ERROR("Memory allocation failed\n");
 200                 goto error;
 201         }
 202
 203         memset(&props, 0, sizeof(props));
 204         props.max_brightness = RADEON_MAX_BL_LEVEL;
 205         props.type = BACKLIGHT_RAW;
 206         bd = backlight_device_register("radeon_bl", &drm_connector->kdev,
 207                                        pdata, &radeon_atom_backlight_ops, &props);
 208         if (IS_ERR(bd)) {
 209                 DRM_ERROR("Backlight registration failed\n");
 210                 goto error;
 211         }
 212
 213         pdata->encoder = radeon_encoder;
 214
 215         backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
 216
 217         dig = radeon_encoder->enc_priv;
 218         dig->bl_dev = bd;
 219
 220         bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 221         bd->props.power = FB_BLANK_UNBLANK;
 222         backlight_update_status(bd);
 223
 224         DRM_INFO("radeon atom DIG backlight initialized\n");
 225
 226         return;
 227
 228 error:
 229         kfree(pdata);
 230         return;
 231 }
 232
 233 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 234 {
 235         struct drm_device *dev = radeon_encoder->base.dev;
 236         struct radeon_device *rdev = dev->dev_private;
 237         struct backlight_device *bd = NULL;
 238         struct radeon_encoder_atom_dig *dig;
 239
 240         if (!radeon_encoder->enc_priv)
 241                 return;
 242
 243         if (!rdev->is_atom_bios)
 244                 return;
 245
 246         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 247                 return;
 248
 249         dig = radeon_encoder->enc_priv;
 250         bd = dig->bl_dev;
 251         dig->bl_dev = NULL;
 252
 253         if (bd) {
 254                 struct radeon_legacy_backlight_privdata *pdata;
 255
 256                 pdata = bl_get_data(bd);
 257                 backlight_device_unregister(bd);
 258                 kfree(pdata);
 259
 260                 DRM_INFO("radeon atom LVDS backlight unloaded\n");
 261         }
 262 }
 263
 264 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 265
 266 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
 267 {
 268 }
 269
 270 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 271 {
 272 }
 273
 274 #endif
 275
 276 /* evil but including atombios.h is much worse */
 277 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
 278                                 struct drm_display_mode *mode);
 279
 280
 281 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 282 {
 283         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 284         switch (radeon_encoder->encoder_id) {
 285         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 286         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 287         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 288         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 289         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 290         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 291         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 292         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 293         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 294         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 295         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 296                 return true;
 297         default:
 298                 return false;
 299         }
 300 }
 301
 302 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 303                                    const struct drm_display_mode *mode,
 304                                    struct drm_display_mode *adjusted_mode)
 305 {
 306         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 307         struct drm_device *dev = encoder->dev;
 308         struct radeon_device *rdev = dev->dev_private;
 309
 310         /* set the active encoder to connector routing */
 311         radeon_encoder_set_active_device(encoder);
 312         drm_mode_set_crtcinfo(adjusted_mode, 0);
 313
 314         /* hw bug */
 315         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 316             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 317                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 318
 319         /* get the native mode for LVDS */
 320         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 321                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 322
 323         /* get the native mode for TV */
 324         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 325                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 326                 if (tv_dac) {
 327                         if (tv_dac->tv_std == TV_STD_NTSC ||
 328                             tv_dac->tv_std == TV_STD_NTSC_J ||
 329                             tv_dac->tv_std == TV_STD_PAL_M)
 330                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 331                         else
 332                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 333                 }
 334         }
 335
 336         if (ASIC_IS_DCE3(rdev) &&
 337             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 338              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 339                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 340                 radeon_dp_set_link_config(connector, mode);
 341         }
 342
 343         return true;
 344 }
 345
 346 static void
 347 atombios_dac_setup(struct drm_encoder *encoder, int action)
 348 {
 349         struct drm_device *dev = encoder->dev;
 350         struct radeon_device *rdev = dev->dev_private;
 351         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 352         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 353         int index = 0;
 354         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 355
 356         memset(&args, 0, sizeof(args));
 357
 358         switch (radeon_encoder->encoder_id) {
 359         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 360         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 361                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 362                 break;
 363         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 364         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 365                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 366                 break;
 367         }
 368
 369         args.ucAction = action;
 370
 371         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 372                 args.ucDacStandard = ATOM_DAC1_PS2;
 373         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 374                 args.ucDacStandard = ATOM_DAC1_CV;
 375         else {
 376                 switch (dac_info->tv_std) {
 377                 case TV_STD_PAL:
 378                 case TV_STD_PAL_M:
 379                 case TV_STD_SCART_PAL:
 380                 case TV_STD_SECAM:
 381                 case TV_STD_PAL_CN:
 382                         args.ucDacStandard = ATOM_DAC1_PAL;
 383                         break;
 384                 case TV_STD_NTSC:
 385                 case TV_STD_NTSC_J:
 386                 case TV_STD_PAL_60:
 387                 default:
 388                         args.ucDacStandard = ATOM_DAC1_NTSC;
 389                         break;
 390                 }
 391         }
 392         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 393
 394         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 395
 396 }
 397
 398 static void
 399 atombios_tv_setup(struct drm_encoder *encoder, int action)
 400 {
 401         struct drm_device *dev = encoder->dev;
 402         struct radeon_device *rdev = dev->dev_private;
 403         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 404         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 405         int index = 0;
 406         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 407
 408         memset(&args, 0, sizeof(args));
 409
 410         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 411
 412         args.sTVEncoder.ucAction = action;
 413
 414         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 415                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 416         else {
 417                 switch (dac_info->tv_std) {
 418                 case TV_STD_NTSC:
 419                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 420                         break;
 421                 case TV_STD_PAL:
 422                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 423                         break;
 424                 case TV_STD_PAL_M:
 425                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 426                         break;
 427                 case TV_STD_PAL_60:
 428                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 429                         break;
 430                 case TV_STD_NTSC_J:
 431                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 432                         break;
 433                 case TV_STD_SCART_PAL:
 434                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 435                         break;
 436                 case TV_STD_SECAM:
 437                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 438                         break;
 439                 case TV_STD_PAL_CN:
 440                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 441                         break;
 442                 default:
 443                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 444                         break;
 445                 }
 446         }
 447
 448         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 449
 450         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 451
 452 }
 453
 454 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 455 {
 456         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 457         int bpc = 8;
 458
 459         if (connector)
 460                 bpc = radeon_get_monitor_bpc(connector);
 461
 462         switch (bpc) {
 463         case 0:
 464                 return PANEL_BPC_UNDEFINE;
 465         case 6:
 466                 return PANEL_6BIT_PER_COLOR;
 467         case 8:
 468         default:
 469                 return PANEL_8BIT_PER_COLOR;
 470         case 10:
 471                 return PANEL_10BIT_PER_COLOR;
 472         case 12:
 473                 return PANEL_12BIT_PER_COLOR;
 474         case 16:
 475                 return PANEL_16BIT_PER_COLOR;
 476         }
 477 }
 478
 479
 480 union dvo_encoder_control {
 481         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 482         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 483         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 484 };
 485
 486 void
 487 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 488 {
 489         struct drm_device *dev = encoder->dev;
 490         struct radeon_device *rdev = dev->dev_private;
 491         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 492         union dvo_encoder_control args;
 493         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 494         uint8_t frev, crev;
 495
 496         memset(&args, 0, sizeof(args));
 497
 498         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 499                 return;
 500
 501         /* some R4xx chips have the wrong frev */
 502         if (rdev->family <= CHIP_RV410)
 503                 frev = 1;
 504
 505         switch (frev) {
 506         case 1:
 507                 switch (crev) {
 508                 case 1:
 509                         /* R4xx, R5xx */
 510                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 511
 512                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 513                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 514
 515                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 516                         break;
 517                 case 2:
 518                         /* RS600/690/740 */
 519                         args.dvo.sDVOEncoder.ucAction = action;
 520                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 521                         /* DFP1, CRT1, TV1 depending on the type of port */
 522                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 523
 524                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 525                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 526                         break;
 527                 case 3:
 528                         /* R6xx */
 529                         args.dvo_v3.ucAction = action;
 530                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 531                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 532                         break;
 533                 default:
 534                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 535                         break;
 536                 }
 537                 break;
 538         default:
 539                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 540                 break;
 541         }
 542
 543         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 544 }
 545
 546 union lvds_encoder_control {
 547         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 548         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 549 };
 550
 551 void
 552 atombios_digital_setup(struct drm_encoder *encoder, int action)
 553 {
 554         struct drm_device *dev = encoder->dev;
 555         struct radeon_device *rdev = dev->dev_private;
 556         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 557         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 558         union lvds_encoder_control args;
 559         int index = 0;
 560         int hdmi_detected = 0;
 561         uint8_t frev, crev;
 562
 563         if (!dig)
 564                 return;
 565
 566         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 567                 hdmi_detected = 1;
 568
 569         memset(&args, 0, sizeof(args));
 570
 571         switch (radeon_encoder->encoder_id) {
 572         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 573                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 574                 break;
 575         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 576         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 577                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 578                 break;
 579         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 580                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 581                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 582                 else
 583                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 584                 break;
 585         }
 586
 587         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 588                 return;
 589
 590         switch (frev) {
 591         case 1:
 592         case 2:
 593                 switch (crev) {
 594                 case 1:
 595                         args.v1.ucMisc = 0;
 596                         args.v1.ucAction = action;
 597                         if (hdmi_detected)
 598                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 599                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 600                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 601                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 602                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 603                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 604                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 605                         } else {
 606                                 if (dig->linkb)
 607                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 608                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 609                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 610                                 /*if (pScrn->rgbBits == 8) */
 611                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 612                         }
 613                         break;
 614                 case 2:
 615                 case 3:
 616                         args.v2.ucMisc = 0;
 617                         args.v2.ucAction = action;
 618                         if (crev == 3) {
 619                                 if (dig->coherent_mode)
 620                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 621                         }
 622                         if (hdmi_detected)
 623                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 624                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 625                         args.v2.ucTruncate = 0;
 626                         args.v2.ucSpatial = 0;
 627                         args.v2.ucTemporal = 0;
 628                         args.v2.ucFRC = 0;
 629                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 630                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 631                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 632                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 633                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 634                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 635                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 636                                 }
 637                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 638                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 639                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 640                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 641                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 642                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 643                                 }
 644                         } else {
 645                                 if (dig->linkb)
 646                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 647                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 648                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 649                         }
 650                         break;
 651                 default:
 652                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 653                         break;
 654                 }
 655                 break;
 656         default:
 657                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 658                 break;
 659         }
 660
 661         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 662 }
 663
 664 int
 665 atombios_get_encoder_mode(struct drm_encoder *encoder)
 666 {
 667         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 668         struct drm_connector *connector;
 669         struct radeon_connector *radeon_connector;
 670         struct radeon_connector_atom_dig *dig_connector;
 671
 672         /* dp bridges are always DP */
 673         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 674                 return ATOM_ENCODER_MODE_DP;
 675
 676         /* DVO is always DVO */
 677         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 678             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 679                 return ATOM_ENCODER_MODE_DVO;
 680
 681         connector = radeon_get_connector_for_encoder(encoder);
 682         /* if we don't have an active device yet, just use one of
 683          * the connectors tied to the encoder.
 684          */
 685         if (!connector)
 686                 connector = radeon_get_connector_for_encoder_init(encoder);
 687         radeon_connector = to_radeon_connector(connector);
 688
 689         switch (connector->connector_type) {
 690         case DRM_MODE_CONNECTOR_DVII:
 691         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 692                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 693                     radeon_audio)
 694                         return ATOM_ENCODER_MODE_HDMI;
 695                 else if (radeon_connector->use_digital)
 696                         return ATOM_ENCODER_MODE_DVI;
 697                 else
 698                         return ATOM_ENCODER_MODE_CRT;
 699                 break;
 700         case DRM_MODE_CONNECTOR_DVID:
 701         case DRM_MODE_CONNECTOR_HDMIA:
 702         default:
 703                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 704                     radeon_audio)
 705                         return ATOM_ENCODER_MODE_HDMI;
 706                 else
 707                         return ATOM_ENCODER_MODE_DVI;
 708                 break;
 709         case DRM_MODE_CONNECTOR_LVDS:
 710                 return ATOM_ENCODER_MODE_LVDS;
 711                 break;
 712         case DRM_MODE_CONNECTOR_DisplayPort:
 713                 dig_connector = radeon_connector->con_priv;
 714                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 715                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
 716                         return ATOM_ENCODER_MODE_DP;
 717                 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 718                          radeon_audio)
 719                         return ATOM_ENCODER_MODE_HDMI;
 720                 else
 721                         return ATOM_ENCODER_MODE_DVI;
 722                 break;
 723         case DRM_MODE_CONNECTOR_eDP:
 724                 return ATOM_ENCODER_MODE_DP;
 725         case DRM_MODE_CONNECTOR_DVIA:
 726         case DRM_MODE_CONNECTOR_VGA:
 727                 return ATOM_ENCODER_MODE_CRT;
 728                 break;
 729         case DRM_MODE_CONNECTOR_Composite:
 730         case DRM_MODE_CONNECTOR_SVIDEO:
 731         case DRM_MODE_CONNECTOR_9PinDIN:
 732                 /* fix me */
 733                 return ATOM_ENCODER_MODE_TV;
 734                 /*return ATOM_ENCODER_MODE_CV;*/
 735                 break;
 736         }
 737 }
 738
 739 /*
 740  * DIG Encoder/Transmitter Setup
 741  *
 742  * DCE 3.0/3.1
 743  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 744  * Supports up to 3 digital outputs
 745  * - 2 DIG encoder blocks.
 746  * DIG1 can drive UNIPHY link A or link B
 747  * DIG2 can drive UNIPHY link B or LVTMA
 748  *
 749  * DCE 3.2
 750  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 751  * Supports up to 5 digital outputs
 752  * - 2 DIG encoder blocks.
 753  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 754  *
 755  * DCE 4.0/5.0/6.0
 756  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 757  * Supports up to 6 digital outputs
 758  * - 6 DIG encoder blocks.
 759  * - DIG to PHY mapping is hardcoded
 760  * DIG1 drives UNIPHY0 link A, A+B
 761  * DIG2 drives UNIPHY0 link B
 762  * DIG3 drives UNIPHY1 link A, A+B
 763  * DIG4 drives UNIPHY1 link B
 764  * DIG5 drives UNIPHY2 link A, A+B
 765  * DIG6 drives UNIPHY2 link B
 766  *
 767  * DCE 4.1
 768  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 769  * Supports up to 6 digital outputs
 770  * - 2 DIG encoder blocks.
 771  * llano
 772  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 773  * ontario
 774  * DIG1 drives UNIPHY0/1/2 link A
 775  * DIG2 drives UNIPHY0/1/2 link B
 776  *
 777  * Routing
 778  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 779  * Examples:
 780  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 781  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 782  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 783  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 784  */
 785
 786 union dig_encoder_control {
 787         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 788         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 789         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 790         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 791 };
 792
 793 void
 794 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 795 {
 796         struct drm_device *dev = encoder->dev;
 797         struct radeon_device *rdev = dev->dev_private;
 798         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 799         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 800         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 801         union dig_encoder_control args;
 802         int index = 0;
 803         uint8_t frev, crev;
 804         int dp_clock = 0;
 805         int dp_lane_count = 0;
 806         int hpd_id = RADEON_HPD_NONE;
 807
 808         if (connector) {
 809                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 810                 struct radeon_connector_atom_dig *dig_connector =
 811                         radeon_connector->con_priv;
 812
 813                 dp_clock = dig_connector->dp_clock;
 814                 dp_lane_count = dig_connector->dp_lane_count;
 815                 hpd_id = radeon_connector->hpd.hpd;
 816         }
 817
 818         /* no dig encoder assigned */
 819         if (dig->dig_encoder == -1)
 820                 return;
 821
 822         memset(&args, 0, sizeof(args));
 823
 824         if (ASIC_IS_DCE4(rdev))
 825                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 826         else {
 827                 if (dig->dig_encoder)
 828                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 829                 else
 830                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 831         }
 832
 833         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 834                 return;
 835
 836         switch (frev) {
 837         case 1:
 838                 switch (crev) {
 839                 case 1:
 840                         args.v1.ucAction = action;
 841                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 842                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 843                                 args.v3.ucPanelMode = panel_mode;
 844                         else
 845                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 846
 847                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 848                                 args.v1.ucLaneNum = dp_lane_count;
 849                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 850                                 args.v1.ucLaneNum = 8;
 851                         else
 852                                 args.v1.ucLaneNum = 4;
 853
 854                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 855                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 856                         switch (radeon_encoder->encoder_id) {
 857                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 858                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 859                                 break;
 860                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 861                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 862                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 863                                 break;
 864                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 865                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 866                                 break;
 867                         }
 868                         if (dig->linkb)
 869                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 870                         else
 871                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 872                         break;
 873                 case 2:
 874                 case 3:
 875                         args.v3.ucAction = action;
 876                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 877                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 878                                 args.v3.ucPanelMode = panel_mode;
 879                         else
 880                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 881
 882                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 883                                 args.v3.ucLaneNum = dp_lane_count;
 884                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 885                                 args.v3.ucLaneNum = 8;
 886                         else
 887                                 args.v3.ucLaneNum = 4;
 888
 889                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 890                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 891                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
 892                         args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 893                         break;
 894                 case 4:
 895                         args.v4.ucAction = action;
 896                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 897                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 898                                 args.v4.ucPanelMode = panel_mode;
 899                         else
 900                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 901
 902                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 903                                 args.v4.ucLaneNum = dp_lane_count;
 904                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 905                                 args.v4.ucLaneNum = 8;
 906                         else
 907                                 args.v4.ucLaneNum = 4;
 908
 909                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 910                                 if (dp_clock == 270000)
 911                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 912                                 else if (dp_clock == 540000)
 913                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 914                         }
 915                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
 916                         args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 917                         if (hpd_id == RADEON_HPD_NONE)
 918                                 args.v4.ucHPD_ID = 0;
 919                         else
 920                                 args.v4.ucHPD_ID = hpd_id + 1;
 921                         break;
 922                 default:
 923                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 924                         break;
 925                 }
 926                 break;
 927         default:
 928                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 929                 break;
 930         }
 931
 932         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 933
 934 }
 935
 936 union dig_transmitter_control {
 937         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 938         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 939         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 940         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 941         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
 942 };
 943
 944 void
 945 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 946 {
 947         struct drm_device *dev = encoder->dev;
 948         struct radeon_device *rdev = dev->dev_private;
 949         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 950         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 951         struct drm_connector *connector;
 952         union dig_transmitter_control args;
 953         int index = 0;
 954         uint8_t frev, crev;
 955         bool is_dp = false;
 956         int pll_id = 0;
 957         int dp_clock = 0;
 958         int dp_lane_count = 0;
 959         int connector_object_id = 0;
 960         int igp_lane_info = 0;
 961         int dig_encoder = dig->dig_encoder;
 962         int hpd_id = RADEON_HPD_NONE;
 963
 964         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
 965                 connector = radeon_get_connector_for_encoder_init(encoder);
 966                 /* just needed to avoid bailing in the encoder check.  the encoder
 967                  * isn't used for init
 968                  */
 969                 dig_encoder = 0;
 970         } else
 971                 connector = radeon_get_connector_for_encoder(encoder);
 972
 973         if (connector) {
 974                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 975                 struct radeon_connector_atom_dig *dig_connector =
 976                         radeon_connector->con_priv;
 977
 978                 hpd_id = radeon_connector->hpd.hpd;
 979                 dp_clock = dig_connector->dp_clock;
 980                 dp_lane_count = dig_connector->dp_lane_count;
 981                 connector_object_id =
 982                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
 983                 igp_lane_info = dig_connector->igp_lane_info;
 984         }
 985
 986         if (encoder->crtc) {
 987                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 988                 pll_id = radeon_crtc->pll_id;
 989         }
 990
 991         /* no dig encoder assigned */
 992         if (dig_encoder == -1)
 993                 return;
 994
 995         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
 996                 is_dp = true;
 997
 998         memset(&args, 0, sizeof(args));
 999
1000         switch (radeon_encoder->encoder_id) {
1001         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1002                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1003                 break;
1004         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1005         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1006         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1007                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1008                 break;
1009         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1010                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1011                 break;
1012         }
1013
1014         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1015                 return;
1016
1017         switch (frev) {
1018         case 1:
1019                 switch (crev) {
1020                 case 1:
1021                         args.v1.ucAction = action;
1022                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1023                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1024                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1025                                 args.v1.asMode.ucLaneSel = lane_num;
1026                                 args.v1.asMode.ucLaneSet = lane_set;
1027                         } else {
1028                                 if (is_dp)
1029                                         args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1030                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1031                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1032                                 else
1033                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1034                         }
1035
1036                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1037
1038                         if (dig_encoder)
1039                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1040                         else
1041                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1042
1043                         if ((rdev->flags & RADEON_IS_IGP) &&
1044                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1045                                 if (is_dp ||
1046                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1047                                         if (igp_lane_info & 0x1)
1048                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1049                                         else if (igp_lane_info & 0x2)
1050                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1051                                         else if (igp_lane_info & 0x4)
1052                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1053                                         else if (igp_lane_info & 0x8)
1054                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1055                                 } else {
1056                                         if (igp_lane_info & 0x3)
1057                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1058                                         else if (igp_lane_info & 0xc)
1059                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1060                                 }
1061                         }
1062
1063                         if (dig->linkb)
1064                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1065                         else
1066                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1067
1068                         if (is_dp)
1069                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1070                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1071                                 if (dig->coherent_mode)
1072                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1073                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1074                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1075                         }
1076                         break;
1077                 case 2:
1078                         args.v2.ucAction = action;
1079                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1080                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1081                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1082                                 args.v2.asMode.ucLaneSel = lane_num;
1083                                 args.v2.asMode.ucLaneSet = lane_set;
1084                         } else {
1085                                 if (is_dp)
1086                                         args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1087                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1088                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1089                                 else
1090                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1091                         }
1092
1093                         args.v2.acConfig.ucEncoderSel = dig_encoder;
1094                         if (dig->linkb)
1095                                 args.v2.acConfig.ucLinkSel = 1;
1096
1097                         switch (radeon_encoder->encoder_id) {
1098                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1099                                 args.v2.acConfig.ucTransmitterSel = 0;
1100                                 break;
1101                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1102                                 args.v2.acConfig.ucTransmitterSel = 1;
1103                                 break;
1104                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1105                                 args.v2.acConfig.ucTransmitterSel = 2;
1106                                 break;
1107                         }
1108
1109                         if (is_dp) {
1110                                 args.v2.acConfig.fCoherentMode = 1;
1111                                 args.v2.acConfig.fDPConnector = 1;
1112                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1113                                 if (dig->coherent_mode)
1114                                         args.v2.acConfig.fCoherentMode = 1;
1115                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1116                                         args.v2.acConfig.fDualLinkConnector = 1;
1117                         }
1118                         break;
1119                 case 3:
1120                         args.v3.ucAction = action;
1121                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1122                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1123                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1124                                 args.v3.asMode.ucLaneSel = lane_num;
1125                                 args.v3.asMode.ucLaneSet = lane_set;
1126                         } else {
1127                                 if (is_dp)
1128                                         args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1129                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1130                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1131                                 else
1132                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1133                         }
1134
1135                         if (is_dp)
1136                                 args.v3.ucLaneNum = dp_lane_count;
1137                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1138                                 args.v3.ucLaneNum = 8;
1139                         else
1140                                 args.v3.ucLaneNum = 4;
1141
1142                         if (dig->linkb)
1143                                 args.v3.acConfig.ucLinkSel = 1;
1144                         if (dig_encoder & 1)
1145                                 args.v3.acConfig.ucEncoderSel = 1;
1146
1147                         /* Select the PLL for the PHY
1148                          * DP PHY should be clocked from external src if there is
1149                          * one.
1150                          */
1151                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1152                         if (is_dp && rdev->clock.dp_extclk)
1153                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1154                         else
1155                                 args.v3.acConfig.ucRefClkSource = pll_id;
1156
1157                         switch (radeon_encoder->encoder_id) {
1158                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1159                                 args.v3.acConfig.ucTransmitterSel = 0;
1160                                 break;
1161                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1162                                 args.v3.acConfig.ucTransmitterSel = 1;
1163                                 break;
1164                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1165                                 args.v3.acConfig.ucTransmitterSel = 2;
1166                                 break;
1167                         }
1168
1169                         if (is_dp)
1170                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1171                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1172                                 if (dig->coherent_mode)
1173                                         args.v3.acConfig.fCoherentMode = 1;
1174                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1175                                         args.v3.acConfig.fDualLinkConnector = 1;
1176                         }
1177                         break;
1178                 case 4:
1179                         args.v4.ucAction = action;
1180                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1181                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1182                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1183                                 args.v4.asMode.ucLaneSel = lane_num;
1184                                 args.v4.asMode.ucLaneSet = lane_set;
1185                         } else {
1186                                 if (is_dp)
1187                                         args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1188                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1189                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1190                                 else
1191                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1192                         }
1193
1194                         if (is_dp)
1195                                 args.v4.ucLaneNum = dp_lane_count;
1196                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1197                                 args.v4.ucLaneNum = 8;
1198                         else
1199                                 args.v4.ucLaneNum = 4;
1200
1201                         if (dig->linkb)
1202                                 args.v4.acConfig.ucLinkSel = 1;
1203                         if (dig_encoder & 1)
1204                                 args.v4.acConfig.ucEncoderSel = 1;
1205
1206                         /* Select the PLL for the PHY
1207                          * DP PHY should be clocked from external src if there is
1208                          * one.
1209                          */
1210                         /* On DCE5 DCPLL usually generates the DP ref clock */
1211                         if (is_dp) {
1212                                 if (rdev->clock.dp_extclk)
1213                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1214                                 else
1215                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1216                         } else
1217                                 args.v4.acConfig.ucRefClkSource = pll_id;
1218
1219                         switch (radeon_encoder->encoder_id) {
1220                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1221                                 args.v4.acConfig.ucTransmitterSel = 0;
1222                                 break;
1223                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1224                                 args.v4.acConfig.ucTransmitterSel = 1;
1225                                 break;
1226                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1227                                 args.v4.acConfig.ucTransmitterSel = 2;
1228                                 break;
1229                         }
1230
1231                         if (is_dp)
1232                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1233                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1234                                 if (dig->coherent_mode)
1235                                         args.v4.acConfig.fCoherentMode = 1;
1236                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1237                                         args.v4.acConfig.fDualLinkConnector = 1;
1238                         }
1239                         break;
1240                 case 5:
1241                         args.v5.ucAction = action;
1242                         if (is_dp)
1243                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1244                         else
1245                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1246
1247                         switch (radeon_encoder->encoder_id) {
1248                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1249                                 if (dig->linkb)
1250                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1251                                 else
1252                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1253                                 break;
1254                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1255                                 if (dig->linkb)
1256                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1257                                 else
1258                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1259                                 break;
1260                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1261                                 if (dig->linkb)
1262                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1263                                 else
1264                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1265                                 break;
1266                         }
1267                         if (is_dp)
1268                                 args.v5.ucLaneNum = dp_lane_count;
1269                         else if (radeon_encoder->pixel_clock > 165000)
1270                                 args.v5.ucLaneNum = 8;
1271                         else
1272                                 args.v5.ucLaneNum = 4;
1273                         args.v5.ucConnObjId = connector_object_id;
1274                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1275
1276                         if (is_dp && rdev->clock.dp_extclk)
1277                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1278                         else
1279                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1280
1281                         if (is_dp)
1282                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1283                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1284                                 if (dig->coherent_mode)
1285                                         args.v5.asConfig.ucCoherentMode = 1;
1286                         }
1287                         if (hpd_id == RADEON_HPD_NONE)
1288                                 args.v5.asConfig.ucHPDSel = 0;
1289                         else
1290                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1291                         args.v5.ucDigEncoderSel = 1 << dig_encoder;
1292                         args.v5.ucDPLaneSet = lane_set;
1293                         break;
1294                 default:
1295                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1296                         break;
1297                 }
1298                 break;
1299         default:
1300                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1301                 break;
1302         }
1303
1304         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1305 }
1306
1307 bool
1308 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1309 {
1310         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1311         struct drm_device *dev = radeon_connector->base.dev;
1312         struct radeon_device *rdev = dev->dev_private;
1313         union dig_transmitter_control args;
1314         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1315         uint8_t frev, crev;
1316
1317         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1318                 goto done;
1319
1320         if (!ASIC_IS_DCE4(rdev))
1321                 goto done;
1322
1323         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1324             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1325                 goto done;
1326
1327         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1328                 goto done;
1329
1330         memset(&args, 0, sizeof(args));
1331
1332         args.v1.ucAction = action;
1333
1334         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1335
1336         /* wait for the panel to power up */
1337         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1338                 int i;
1339
1340                 for (i = 0; i < 300; i++) {
1341                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1342                                 return true;
1343                         mdelay(1);
1344                 }
1345                 return false;
1346         }
1347 done:
1348         return true;
1349 }
1350
1351 union external_encoder_control {
1352         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1353         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1354 };
1355
1356 static void
1357 atombios_external_encoder_setup(struct drm_encoder *encoder,
1358                                 struct drm_encoder *ext_encoder,
1359                                 int action)
1360 {
1361         struct drm_device *dev = encoder->dev;
1362         struct radeon_device *rdev = dev->dev_private;
1363         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1364         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1365         union external_encoder_control args;
1366         struct drm_connector *connector;
1367         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1368         u8 frev, crev;
1369         int dp_clock = 0;
1370         int dp_lane_count = 0;
1371         int connector_object_id = 0;
1372         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1373
1374         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1375                 connector = radeon_get_connector_for_encoder_init(encoder);
1376         else
1377                 connector = radeon_get_connector_for_encoder(encoder);
1378
1379         if (connector) {
1380                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1381                 struct radeon_connector_atom_dig *dig_connector =
1382                         radeon_connector->con_priv;
1383
1384                 dp_clock = dig_connector->dp_clock;
1385                 dp_lane_count = dig_connector->dp_lane_count;
1386                 connector_object_id =
1387                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1388         }
1389
1390         memset(&args, 0, sizeof(args));
1391
1392         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1393                 return;
1394
1395         switch (frev) {
1396         case 1:
1397                 /* no params on frev 1 */
1398                 break;
1399         case 2:
1400                 switch (crev) {
1401                 case 1:
1402                 case 2:
1403                         args.v1.sDigEncoder.ucAction = action;
1404                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1405                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1406
1407                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1408                                 if (dp_clock == 270000)
1409                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1410                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1411                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1412                                 args.v1.sDigEncoder.ucLaneNum = 8;
1413                         else
1414                                 args.v1.sDigEncoder.ucLaneNum = 4;
1415                         break;
1416                 case 3:
1417                         args.v3.sExtEncoder.ucAction = action;
1418                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1419                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1420                         else
1421                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1422                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1423
1424                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1425                                 if (dp_clock == 270000)
1426                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1427                                 else if (dp_clock == 540000)
1428                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1429                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1430                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1431                                 args.v3.sExtEncoder.ucLaneNum = 8;
1432                         else
1433                                 args.v3.sExtEncoder.ucLaneNum = 4;
1434                         switch (ext_enum) {
1435                         case GRAPH_OBJECT_ENUM_ID1:
1436                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1437                                 break;
1438                         case GRAPH_OBJECT_ENUM_ID2:
1439                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1440                                 break;
1441                         case GRAPH_OBJECT_ENUM_ID3:
1442                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1443                                 break;
1444                         }
1445                         args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1446                         break;
1447                 default:
1448                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1449                         return;
1450                 }
1451                 break;
1452         default:
1453                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1454                 return;
1455         }
1456         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1457 }
1458
1459 static void
1460 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1461 {
1462         struct drm_device *dev = encoder->dev;
1463         struct radeon_device *rdev = dev->dev_private;
1464         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1465         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1466         ENABLE_YUV_PS_ALLOCATION args;
1467         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1468         uint32_t temp, reg;
1469
1470         memset(&args, 0, sizeof(args));
1471
1472         if (rdev->family >= CHIP_R600)
1473                 reg = R600_BIOS_3_SCRATCH;
1474         else
1475                 reg = RADEON_BIOS_3_SCRATCH;
1476
1477         /* XXX: fix up scratch reg handling */
1478         temp = RREG32(reg);
1479         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1480                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1481                              (radeon_crtc->crtc_id << 18)));
1482         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1483                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1484         else
1485                 WREG32(reg, 0);
1486
1487         if (enable)
1488                 args.ucEnable = ATOM_ENABLE;
1489         args.ucCRTC = radeon_crtc->crtc_id;
1490
1491         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1492
1493         WREG32(reg, temp);
1494 }
1495
1496 static void
1497 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1498 {
1499         struct drm_device *dev = encoder->dev;
1500         struct radeon_device *rdev = dev->dev_private;
1501         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1502         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1503         int index = 0;
1504
1505         memset(&args, 0, sizeof(args));
1506
1507         switch (radeon_encoder->encoder_id) {
1508         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1509         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1510                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1511                 break;
1512         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1513         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1514         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1515                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1516                 break;
1517         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1518                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1519                 break;
1520         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1521                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1522                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1523                 else
1524                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1525                 break;
1526         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1527         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1528                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1529                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1530                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1531                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1532                 else
1533                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1534                 break;
1535         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1536         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1537                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1538                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1539                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1540                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1541                 else
1542                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1543                 break;
1544         default:
1545                 return;
1546         }
1547
1548         switch (mode) {
1549         case DRM_MODE_DPMS_ON:
1550                 args.ucAction = ATOM_ENABLE;
1551                 /* workaround for DVOOutputControl on some RS690 systems */
1552                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1553                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1554                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1555                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1556                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1557                 } else
1558                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1559                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1560                         args.ucAction = ATOM_LCD_BLON;
1561                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1562                 }
1563                 break;
1564         case DRM_MODE_DPMS_STANDBY:
1565         case DRM_MODE_DPMS_SUSPEND:
1566         case DRM_MODE_DPMS_OFF:
1567                 args.ucAction = ATOM_DISABLE;
1568                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1569                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1570                         args.ucAction = ATOM_LCD_BLOFF;
1571                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1572                 }
1573                 break;
1574         }
1575 }
1576
1577 static void
1578 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1579 {
1580         struct drm_device *dev = encoder->dev;
1581         struct radeon_device *rdev = dev->dev_private;
1582         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1583         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1584         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1585         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1586         struct radeon_connector *radeon_connector = NULL;
1587         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1588
1589         if (connector) {
1590                 radeon_connector = to_radeon_connector(connector);
1591                 radeon_dig_connector = radeon_connector->con_priv;
1592         }
1593
1594         switch (mode) {
1595         case DRM_MODE_DPMS_ON:
1596                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1597                         if (!connector)
1598                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1599                         else
1600                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1601
1602                         /* setup and enable the encoder */
1603                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1604                         atombios_dig_encoder_setup(encoder,
1605                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1606                                                    dig->panel_mode);
1607                         if (ext_encoder) {
1608                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1609                                         atombios_external_encoder_setup(encoder, ext_encoder,
1610                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1611                         }
1612                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1613                 } else if (ASIC_IS_DCE4(rdev)) {
1614                         /* setup and enable the encoder */
1615                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1616                         /* enable the transmitter */
1617                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1618                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1619                 } else {
1620                         /* setup and enable the encoder and transmitter */
1621                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1622                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1623                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1624                         /* some early dce3.2 boards have a bug in their transmitter control table */
1625                         if ((rdev->family != CHIP_RV710) || (rdev->family != CHIP_RV730))
1626                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1627                 }
1628                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1629                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1630                                 atombios_set_edp_panel_power(connector,
1631                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1632                                 radeon_dig_connector->edp_on = true;
1633                         }
1634                         radeon_dp_link_train(encoder, connector);
1635                         if (ASIC_IS_DCE4(rdev))
1636                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1637                 }
1638                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1639                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1640                 break;
1641         case DRM_MODE_DPMS_STANDBY:
1642         case DRM_MODE_DPMS_SUSPEND:
1643         case DRM_MODE_DPMS_OFF:
1644                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1645                         /* disable the transmitter */
1646                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1647                 } else if (ASIC_IS_DCE4(rdev)) {
1648                         /* disable the transmitter */
1649                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1650                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1651                 } else {
1652                         /* disable the encoder and transmitter */
1653                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1654                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1655                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1656                 }
1657                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1658                         if (ASIC_IS_DCE4(rdev))
1659                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1660                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1661                                 atombios_set_edp_panel_power(connector,
1662                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1663                                 radeon_dig_connector->edp_on = false;
1664                         }
1665                 }
1666                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1667                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1668                 break;
1669         }
1670 }
1671
1672 static void
1673 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1674                              struct drm_encoder *ext_encoder,
1675                              int mode)
1676 {
1677         struct drm_device *dev = encoder->dev;
1678         struct radeon_device *rdev = dev->dev_private;
1679
1680         switch (mode) {
1681         case DRM_MODE_DPMS_ON:
1682         default:
1683                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1684                         atombios_external_encoder_setup(encoder, ext_encoder,
1685                                                         EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1686                         atombios_external_encoder_setup(encoder, ext_encoder,
1687                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1688                 } else
1689                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1690                 break;
1691         case DRM_MODE_DPMS_STANDBY:
1692         case DRM_MODE_DPMS_SUSPEND:
1693         case DRM_MODE_DPMS_OFF:
1694                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1695                         atombios_external_encoder_setup(encoder, ext_encoder,
1696                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1697                         atombios_external_encoder_setup(encoder, ext_encoder,
1698                                                         EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1699                 } else
1700                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1701                 break;
1702         }
1703 }
1704
1705 static void
1706 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1707 {
1708         struct drm_device *dev = encoder->dev;
1709         struct radeon_device *rdev = dev->dev_private;
1710         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1711         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1712
1713         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1714                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1715                   radeon_encoder->active_device);
1716         switch (radeon_encoder->encoder_id) {
1717         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1718         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1719         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1720         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1721         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1722         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1723         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1724         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1725                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1726                 break;
1727         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1728         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1729         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1730         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1731                 radeon_atom_encoder_dpms_dig(encoder, mode);
1732                 break;
1733         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1734                 if (ASIC_IS_DCE5(rdev)) {
1735                         switch (mode) {
1736                         case DRM_MODE_DPMS_ON:
1737                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1738                                 break;
1739                         case DRM_MODE_DPMS_STANDBY:
1740                         case DRM_MODE_DPMS_SUSPEND:
1741                         case DRM_MODE_DPMS_OFF:
1742                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1743                                 break;
1744                         }
1745                 } else if (ASIC_IS_DCE3(rdev))
1746                         radeon_atom_encoder_dpms_dig(encoder, mode);
1747                 else
1748                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1749                 break;
1750         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1751         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1752                 if (ASIC_IS_DCE5(rdev)) {
1753                         switch (mode) {
1754                         case DRM_MODE_DPMS_ON:
1755                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1756                                 break;
1757                         case DRM_MODE_DPMS_STANDBY:
1758                         case DRM_MODE_DPMS_SUSPEND:
1759                         case DRM_MODE_DPMS_OFF:
1760                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1761                                 break;
1762                         }
1763                 } else
1764                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1765                 break;
1766         default:
1767                 return;
1768         }
1769
1770         if (ext_encoder)
1771                 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1772
1773         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1774
1775 }
1776
1777 union crtc_source_param {
1778         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1779         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1780 };
1781
1782 static void
1783 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1784 {
1785         struct drm_device *dev = encoder->dev;
1786         struct radeon_device *rdev = dev->dev_private;
1787         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1788         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1789         union crtc_source_param args;
1790         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1791         uint8_t frev, crev;
1792         struct radeon_encoder_atom_dig *dig;
1793
1794         memset(&args, 0, sizeof(args));
1795
1796         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1797                 return;
1798
1799         switch (frev) {
1800         case 1:
1801                 switch (crev) {
1802                 case 1:
1803                 default:
1804                         if (ASIC_IS_AVIVO(rdev))
1805                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1806                         else {
1807                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1808                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1809                                 } else {
1810                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1811                                 }
1812                         }
1813                         switch (radeon_encoder->encoder_id) {
1814                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1815                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1816                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1817                                 break;
1818                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1819                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1820                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1821                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1822                                 else
1823                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1824                                 break;
1825                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1826                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1827                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1828                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1829                                 break;
1830                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1831                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1832                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1833                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1834                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1835                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1836                                 else
1837                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1838                                 break;
1839                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1840                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1841                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1842                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1843                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1844                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1845                                 else
1846                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1847                                 break;
1848                         }
1849                         break;
1850                 case 2:
1851                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1852                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1853                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1854
1855                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1856                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1857                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1858                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1859                                 else
1860                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1861                         } else
1862                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1863                         switch (radeon_encoder->encoder_id) {
1864                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1865                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1866                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1867                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1868                                 dig = radeon_encoder->enc_priv;
1869                                 switch (dig->dig_encoder) {
1870                                 case 0:
1871                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1872                                         break;
1873                                 case 1:
1874                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1875                                         break;
1876                                 case 2:
1877                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1878                                         break;
1879                                 case 3:
1880                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1881                                         break;
1882                                 case 4:
1883                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1884                                         break;
1885                                 case 5:
1886                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1887                                         break;
1888                                 }
1889                                 break;
1890                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1891                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1892                                 break;
1893                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1894                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1895                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1896                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1897                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1898                                 else
1899                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1900                                 break;
1901                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1902                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1903                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1904                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1905                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1906                                 else
1907                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1908                                 break;
1909                         }
1910                         break;
1911                 }
1912                 break;
1913         default:
1914                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1915                 return;
1916         }
1917
1918         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1919
1920         /* update scratch regs with new routing */
1921         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1922 }
1923
1924 static void
1925 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1926                               struct drm_display_mode *mode)
1927 {
1928         struct drm_device *dev = encoder->dev;
1929         struct radeon_device *rdev = dev->dev_private;
1930         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1931         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1932
1933         /* Funky macbooks */
1934         if ((dev->pdev->device == 0x71C5) &&
1935             (dev->pdev->subsystem_vendor == 0x106b) &&
1936             (dev->pdev->subsystem_device == 0x0080)) {
1937                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1938                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1939
1940                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1941                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1942
1943                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1944                 }
1945         }
1946
1947         /* set scaler clears this on some chips */
1948         if (ASIC_IS_AVIVO(rdev) &&
1949             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1950                 if (ASIC_IS_DCE4(rdev)) {
1951                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1952                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1953                                        EVERGREEN_INTERLEAVE_EN);
1954                         else
1955                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1956                 } else {
1957                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1958                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1959                                        AVIVO_D1MODE_INTERLEAVE_EN);
1960                         else
1961                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1962                 }
1963         }
1964 }
1965
1966 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1967 {
1968         struct drm_device *dev = encoder->dev;
1969         struct radeon_device *rdev = dev->dev_private;
1970         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1971         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1972         struct drm_encoder *test_encoder;
1973         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1974         uint32_t dig_enc_in_use = 0;
1975
1976         if (ASIC_IS_DCE6(rdev)) {
1977                 /* DCE6 */
1978                 switch (radeon_encoder->encoder_id) {
1979                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1980                         if (dig->linkb)
1981                                 return 1;
1982                         else
1983                                 return 0;
1984                         break;
1985                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1986                         if (dig->linkb)
1987                                 return 3;
1988                         else
1989                                 return 2;
1990                         break;
1991                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1992                         if (dig->linkb)
1993                                 return 5;
1994                         else
1995                                 return 4;
1996                         break;
1997                 }
1998         } else if (ASIC_IS_DCE4(rdev)) {
1999                 /* DCE4/5 */
2000                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2001                         /* ontario follows DCE4 */
2002                         if (rdev->family == CHIP_PALM) {
2003                                 if (dig->linkb)
2004                                         return 1;
2005                                 else
2006                                         return 0;
2007                         } else
2008                                 /* llano follows DCE3.2 */
2009                                 return radeon_crtc->crtc_id;
2010                 } else {
2011                         switch (radeon_encoder->encoder_id) {
2012                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2013                                 if (dig->linkb)
2014                                         return 1;
2015                                 else
2016                                         return 0;
2017                                 break;
2018                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2019                                 if (dig->linkb)
2020                                         return 3;
2021                                 else
2022                                         return 2;
2023                                 break;
2024                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2025                                 if (dig->linkb)
2026                                         return 5;
2027                                 else
2028                                         return 4;
2029                                 break;
2030                         }
2031                 }
2032         }
2033
2034         /* on DCE32 and encoder can driver any block so just crtc id */
2035         if (ASIC_IS_DCE32(rdev)) {
2036                 return radeon_crtc->crtc_id;
2037         }
2038
2039         /* on DCE3 - LVTMA can only be driven by DIGB */
2040         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2041                 struct radeon_encoder *radeon_test_encoder;
2042
2043                 if (encoder == test_encoder)
2044                         continue;
2045
2046                 if (!radeon_encoder_is_digital(test_encoder))
2047                         continue;
2048
2049                 radeon_test_encoder = to_radeon_encoder(test_encoder);
2050                 dig = radeon_test_encoder->enc_priv;
2051
2052                 if (dig->dig_encoder >= 0)
2053                         dig_enc_in_use |= (1 << dig->dig_encoder);
2054         }
2055
2056         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2057                 if (dig_enc_in_use & 0x2)
2058                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2059                 return 1;
2060         }
2061         if (!(dig_enc_in_use & 1))
2062                 return 0;
2063         return 1;
2064 }
2065
2066 /* This only needs to be called once at startup */
2067 void
2068 radeon_atom_encoder_init(struct radeon_device *rdev)
2069 {
2070         struct drm_device *dev = rdev->ddev;
2071         struct drm_encoder *encoder;
2072
2073         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2074                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2075                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2076
2077                 switch (radeon_encoder->encoder_id) {
2078                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2079                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2080                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2081                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2082                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2083                         break;
2084                 default:
2085                         break;
2086                 }
2087
2088                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2089                         atombios_external_encoder_setup(encoder, ext_encoder,
2090                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2091         }
2092 }
2093
2094 static void
2095 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2096                              struct drm_display_mode *mode,
2097                              struct drm_display_mode *adjusted_mode)
2098 {
2099         struct drm_device *dev = encoder->dev;
2100         struct radeon_device *rdev = dev->dev_private;
2101         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2102
2103         radeon_encoder->pixel_clock = adjusted_mode->clock;
2104
2105         /* need to call this here rather than in prepare() since we need some crtc info */
2106         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2107
2108         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2109                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2110                         atombios_yuv_setup(encoder, true);
2111                 else
2112                         atombios_yuv_setup(encoder, false);
2113         }
2114
2115         switch (radeon_encoder->encoder_id) {
2116         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2117         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2118         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2119         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2120                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2121                 break;
2122         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2123         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2124         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2125         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2126                 /* handled in dpms */
2127                 break;
2128         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2129         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2130         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2131                 atombios_dvo_setup(encoder, ATOM_ENABLE);
2132                 break;
2133         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2134         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2135         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2136         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2137                 atombios_dac_setup(encoder, ATOM_ENABLE);
2138                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2139                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2140                                 atombios_tv_setup(encoder, ATOM_ENABLE);
2141                         else
2142                                 atombios_tv_setup(encoder, ATOM_DISABLE);
2143                 }
2144                 break;
2145         }
2146
2147         atombios_apply_encoder_quirks(encoder, adjusted_mode);
2148
2149         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2150                 r600_hdmi_enable(encoder);
2151                 if (ASIC_IS_DCE6(rdev))
2152                         ; /* TODO (use pointers instead of if-s?) */
2153                 else if (ASIC_IS_DCE4(rdev))
2154                         evergreen_hdmi_setmode(encoder, adjusted_mode);
2155                 else
2156                         r600_hdmi_setmode(encoder, adjusted_mode);
2157         }
2158 }
2159
2160 static bool
2161 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2162 {
2163         struct drm_device *dev = encoder->dev;
2164         struct radeon_device *rdev = dev->dev_private;
2165         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2166         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2167
2168         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2169                                        ATOM_DEVICE_CV_SUPPORT |
2170                                        ATOM_DEVICE_CRT_SUPPORT)) {
2171                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2172                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2173                 uint8_t frev, crev;
2174
2175                 memset(&args, 0, sizeof(args));
2176
2177                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2178                         return false;
2179
2180                 args.sDacload.ucMisc = 0;
2181
2182                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2183                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2184                         args.sDacload.ucDacType = ATOM_DAC_A;
2185                 else
2186                         args.sDacload.ucDacType = ATOM_DAC_B;
2187
2188                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2189                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2190                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2191                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2192                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2193                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2194                         if (crev >= 3)
2195                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2196                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2197                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2198                         if (crev >= 3)
2199                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2200                 }
2201
2202                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2203
2204                 return true;
2205         } else
2206                 return false;
2207 }
2208
2209 static enum drm_connector_status
2210 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2211 {
2212         struct drm_device *dev = encoder->dev;
2213         struct radeon_device *rdev = dev->dev_private;
2214         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2215         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2216         uint32_t bios_0_scratch;
2217
2218         if (!atombios_dac_load_detect(encoder, connector)) {
2219                 DRM_DEBUG_KMS("detect returned false \n");
2220                 return connector_status_unknown;
2221         }
2222
2223         if (rdev->family >= CHIP_R600)
2224                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2225         else
2226                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2227
2228         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2229         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2230                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2231                         return connector_status_connected;
2232         }
2233         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2234                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2235                         return connector_status_connected;
2236         }
2237         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2238                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2239                         return connector_status_connected;
2240         }
2241         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2242                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2243                         return connector_status_connected; /* CTV */
2244                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2245                         return connector_status_connected; /* STV */
2246         }
2247         return connector_status_disconnected;
2248 }
2249
2250 static enum drm_connector_status
2251 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2252 {
2253         struct drm_device *dev = encoder->dev;
2254         struct radeon_device *rdev = dev->dev_private;
2255         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2256         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2257         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2258         u32 bios_0_scratch;
2259
2260         if (!ASIC_IS_DCE4(rdev))
2261                 return connector_status_unknown;
2262
2263         if (!ext_encoder)
2264                 return connector_status_unknown;
2265
2266         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2267                 return connector_status_unknown;
2268
2269         /* load detect on the dp bridge */
2270         atombios_external_encoder_setup(encoder, ext_encoder,
2271                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2272
2273         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2274
2275         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2276         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2277                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2278                         return connector_status_connected;
2279         }
2280         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2281                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2282                         return connector_status_connected;
2283         }
2284         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2285                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2286                         return connector_status_connected;
2287         }
2288         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2289                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2290                         return connector_status_connected; /* CTV */
2291                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2292                         return connector_status_connected; /* STV */
2293         }
2294         return connector_status_disconnected;
2295 }
2296
2297 void
2298 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2299 {
2300         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2301
2302         if (ext_encoder)
2303                 /* ddc_setup on the dp bridge */
2304                 atombios_external_encoder_setup(encoder, ext_encoder,
2305                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2306
2307 }
2308
2309 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2310 {
2311         struct radeon_device *rdev = encoder->dev->dev_private;
2312         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2313         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2314
2315         if ((radeon_encoder->active_device &
2316              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2317             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2318              ENCODER_OBJECT_ID_NONE)) {
2319                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2320                 if (dig) {
2321                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2322                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2323                                 if (rdev->family >= CHIP_R600)
2324                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2325                                 else
2326                                         /* RS600/690/740 have only 1 afmt block */
2327                                         dig->afmt = rdev->mode_info.afmt[0];
2328                         }
2329                 }
2330         }
2331
2332         radeon_atom_output_lock(encoder, true);
2333
2334         if (connector) {
2335                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2336
2337                 /* select the clock/data port if it uses a router */
2338                 if (radeon_connector->router.cd_valid)
2339                         radeon_router_select_cd_port(radeon_connector);
2340
2341                 /* turn eDP panel on for mode set */
2342                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2343                         atombios_set_edp_panel_power(connector,
2344                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2345         }
2346
2347         /* this is needed for the pll/ss setup to work correctly in some cases */
2348         atombios_set_encoder_crtc_source(encoder);
2349 }
2350
2351 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2352 {
2353         /* need to call this here as we need the crtc set up */
2354         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2355         radeon_atom_output_lock(encoder, false);
2356 }
2357
2358 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2359 {
2360         struct drm_device *dev = encoder->dev;
2361         struct radeon_device *rdev = dev->dev_private;
2362         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2363         struct radeon_encoder_atom_dig *dig;
2364
2365         /* check for pre-DCE3 cards with shared encoders;
2366          * can't really use the links individually, so don't disable
2367          * the encoder if it's in use by another connector
2368          */
2369         if (!ASIC_IS_DCE3(rdev)) {
2370                 struct drm_encoder *other_encoder;
2371                 struct radeon_encoder *other_radeon_encoder;
2372
2373                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2374                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2375                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2376                             drm_helper_encoder_in_use(other_encoder))
2377                                 goto disable_done;
2378                 }
2379         }
2380
2381         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2382
2383         switch (radeon_encoder->encoder_id) {
2384         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2385         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2386         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2387         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2388                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2389                 break;
2390         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2391         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2392         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2393         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2394                 /* handled in dpms */
2395                 break;
2396         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2397         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2398         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2399                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2400                 break;
2401         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2402         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2403         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2404         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2405                 atombios_dac_setup(encoder, ATOM_DISABLE);
2406                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2407                         atombios_tv_setup(encoder, ATOM_DISABLE);
2408                 break;
2409         }
2410
2411 disable_done:
2412         if (radeon_encoder_is_digital(encoder)) {
2413                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2414                         r600_hdmi_disable(encoder);
2415                 dig = radeon_encoder->enc_priv;
2416                 dig->dig_encoder = -1;
2417         }
2418         radeon_encoder->active_device = 0;
2419 }
2420
2421 /* these are handled by the primary encoders */
2422 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2423 {
2424
2425 }
2426
2427 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2428 {
2429
2430 }
2431
2432 static void
2433 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2434                          struct drm_display_mode *mode,
2435                          struct drm_display_mode *adjusted_mode)
2436 {
2437
2438 }
2439
2440 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2441 {
2442
2443 }
2444
2445 static void
2446 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2447 {
2448
2449 }
2450
2451 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2452                                        const struct drm_display_mode *mode,
2453                                        struct drm_display_mode *adjusted_mode)
2454 {
2455         return true;
2456 }
2457
2458 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2459         .dpms = radeon_atom_ext_dpms,
2460         .mode_fixup = radeon_atom_ext_mode_fixup,
2461         .prepare = radeon_atom_ext_prepare,
2462         .mode_set = radeon_atom_ext_mode_set,
2463         .commit = radeon_atom_ext_commit,
2464         .disable = radeon_atom_ext_disable,
2465         /* no detect for TMDS/LVDS yet */
2466 };
2467
2468 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2469         .dpms = radeon_atom_encoder_dpms,
2470         .mode_fixup = radeon_atom_mode_fixup,
2471         .prepare = radeon_atom_encoder_prepare,
2472         .mode_set = radeon_atom_encoder_mode_set,
2473         .commit = radeon_atom_encoder_commit,
2474         .disable = radeon_atom_encoder_disable,
2475         .detect = radeon_atom_dig_detect,
2476 };
2477
2478 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2479         .dpms = radeon_atom_encoder_dpms,
2480         .mode_fixup = radeon_atom_mode_fixup,
2481         .prepare = radeon_atom_encoder_prepare,
2482         .mode_set = radeon_atom_encoder_mode_set,
2483         .commit = radeon_atom_encoder_commit,
2484         .detect = radeon_atom_dac_detect,
2485 };
2486
2487 void radeon_enc_destroy(struct drm_encoder *encoder)
2488 {
2489         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2490         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2491                 radeon_atom_backlight_exit(radeon_encoder);
2492         kfree(radeon_encoder->enc_priv);
2493         drm_encoder_cleanup(encoder);
2494         kfree(radeon_encoder);
2495 }
2496
2497 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2498         .destroy = radeon_enc_destroy,
2499 };
2500
2501 static struct radeon_encoder_atom_dac *
2502 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2503 {
2504         struct drm_device *dev = radeon_encoder->base.dev;
2505         struct radeon_device *rdev = dev->dev_private;
2506         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2507
2508         if (!dac)
2509                 return NULL;
2510
2511         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2512         return dac;
2513 }
2514
2515 static struct radeon_encoder_atom_dig *
2516 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2517 {
2518         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2519         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2520
2521         if (!dig)
2522                 return NULL;
2523
2524         /* coherent mode by default */
2525         dig->coherent_mode = true;
2526         dig->dig_encoder = -1;
2527
2528         if (encoder_enum == 2)
2529                 dig->linkb = true;
2530         else
2531                 dig->linkb = false;
2532
2533         return dig;
2534 }
2535
2536 void
2537 radeon_add_atom_encoder(struct drm_device *dev,
2538                         uint32_t encoder_enum,
2539                         uint32_t supported_device,
2540                         u16 caps)
2541 {
2542         struct radeon_device *rdev = dev->dev_private;
2543         struct drm_encoder *encoder;
2544         struct radeon_encoder *radeon_encoder;
2545
2546         /* see if we already added it */
2547         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2548                 radeon_encoder = to_radeon_encoder(encoder);
2549                 if (radeon_encoder->encoder_enum == encoder_enum) {
2550                         radeon_encoder->devices |= supported_device;
2551                         return;
2552                 }
2553
2554         }
2555
2556         /* add a new one */
2557         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2558         if (!radeon_encoder)
2559                 return;
2560
2561         encoder = &radeon_encoder->base;
2562         switch (rdev->num_crtc) {
2563         case 1:
2564                 encoder->possible_crtcs = 0x1;
2565                 break;
2566         case 2:
2567         default:
2568                 encoder->possible_crtcs = 0x3;
2569                 break;
2570         case 4:
2571                 encoder->possible_crtcs = 0xf;
2572                 break;
2573         case 6:
2574                 encoder->possible_crtcs = 0x3f;
2575                 break;
2576         }
2577
2578         radeon_encoder->enc_priv = NULL;
2579
2580         radeon_encoder->encoder_enum = encoder_enum;
2581         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2582         radeon_encoder->devices = supported_device;
2583         radeon_encoder->rmx_type = RMX_OFF;
2584         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2585         radeon_encoder->is_ext_encoder = false;
2586         radeon_encoder->caps = caps;
2587
2588         switch (radeon_encoder->encoder_id) {
2589         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2590         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2591         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2592         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2593                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2594                         radeon_encoder->rmx_type = RMX_FULL;
2595                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2596                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2597                 } else {
2598                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2599                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2600                 }
2601                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2602                 break;
2603         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2604                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2605                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2606                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2607                 break;
2608         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2609         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2610         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2611                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2612                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2613                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2614                 break;
2615         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2616         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2617         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2618         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2619         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2620         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2621         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2622                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2623                         radeon_encoder->rmx_type = RMX_FULL;
2624                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2625                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2626                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2627                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2628                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2629                 } else {
2630                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2631                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2632                 }
2633                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2634                 break;
2635         case ENCODER_OBJECT_ID_SI170B:
2636         case ENCODER_OBJECT_ID_CH7303:
2637         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2638         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2639         case ENCODER_OBJECT_ID_TITFP513:
2640         case ENCODER_OBJECT_ID_VT1623:
2641         case ENCODER_OBJECT_ID_HDMI_SI1930:
2642         case ENCODER_OBJECT_ID_TRAVIS:
2643         case ENCODER_OBJECT_ID_NUTMEG:
2644                 /* these are handled by the primary encoders */
2645                 radeon_encoder->is_ext_encoder = true;
2646                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2647                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2648                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2649                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2650                 else
2651                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2652                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2653                 break;
2654         }
2655 }