3 * Copyright 2008 (c) Intel Corporation
4 * Jesse Barnes <jbarnes@virtuousgeek.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32 static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
34 struct drm_i915_private *dev_priv = dev->dev_private;
37 return (I915_READ(DPLL_A) & DPLL_VCO_ENABLE);
39 return (I915_READ(DPLL_B) & DPLL_VCO_ENABLE);
42 static void i915_save_palette(struct drm_device *dev, enum pipe pipe)
44 struct drm_i915_private *dev_priv = dev->dev_private;
45 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
49 if (!i915_pipe_enabled(dev, pipe))
53 array = dev_priv->save_palette_a;
55 array = dev_priv->save_palette_b;
57 for(i = 0; i < 256; i++)
58 array[i] = I915_READ(reg + (i << 2));
61 static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
63 struct drm_i915_private *dev_priv = dev->dev_private;
64 unsigned long reg = (pipe == PIPE_A ? PALETTE_A : PALETTE_B);
68 if (!i915_pipe_enabled(dev, pipe))
72 array = dev_priv->save_palette_a;
74 array = dev_priv->save_palette_b;
76 for(i = 0; i < 256; i++)
77 I915_WRITE(reg + (i << 2), array[i]);
80 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
82 struct drm_i915_private *dev_priv = dev->dev_private;
84 I915_WRITE8(index_port, reg);
85 return I915_READ8(data_port);
88 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
90 struct drm_i915_private *dev_priv = dev->dev_private;
93 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
94 return I915_READ8(VGA_AR_DATA_READ);
97 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
99 struct drm_i915_private *dev_priv = dev->dev_private;
102 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
103 I915_WRITE8(VGA_AR_DATA_WRITE, val);
106 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
108 struct drm_i915_private *dev_priv = dev->dev_private;
110 I915_WRITE8(index_port, reg);
111 I915_WRITE8(data_port, val);
114 static void i915_save_vga(struct drm_device *dev)
116 struct drm_i915_private *dev_priv = dev->dev_private;
118 u16 cr_index, cr_data, st01;
120 /* VGA color palette registers */
121 dev_priv->saveDACMASK = I915_READ8(VGA_DACMASK);
124 dev_priv->saveMSR = I915_READ8(VGA_MSR_READ);
125 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
126 cr_index = VGA_CR_INDEX_CGA;
127 cr_data = VGA_CR_DATA_CGA;
130 cr_index = VGA_CR_INDEX_MDA;
131 cr_data = VGA_CR_DATA_MDA;
135 /* CRT controller regs */
136 i915_write_indexed(dev, cr_index, cr_data, 0x11,
137 i915_read_indexed(dev, cr_index, cr_data, 0x11) &
139 for (i = 0; i <= 0x24; i++)
140 dev_priv->saveCR[i] =
141 i915_read_indexed(dev, cr_index, cr_data, i);
142 /* Make sure we don't turn off CR group 0 writes */
143 dev_priv->saveCR[0x11] &= ~0x80;
145 /* Attribute controller registers */
147 dev_priv->saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
148 for (i = 0; i <= 0x14; i++)
149 dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
151 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX);
154 /* Graphics controller registers */
155 for (i = 0; i < 9; i++)
156 dev_priv->saveGR[i] =
157 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
159 dev_priv->saveGR[0x10] =
160 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
161 dev_priv->saveGR[0x11] =
162 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
163 dev_priv->saveGR[0x18] =
164 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
166 /* Sequencer registers */
167 for (i = 0; i < 8; i++)
168 dev_priv->saveSR[i] =
169 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
172 static void i915_restore_vga(struct drm_device *dev)
174 struct drm_i915_private *dev_priv = dev->dev_private;
176 u16 cr_index, cr_data, st01;
179 I915_WRITE8(VGA_MSR_WRITE, dev_priv->saveMSR);
180 if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
181 cr_index = VGA_CR_INDEX_CGA;
182 cr_data = VGA_CR_DATA_CGA;
185 cr_index = VGA_CR_INDEX_MDA;
186 cr_data = VGA_CR_DATA_MDA;
190 /* Sequencer registers, don't write SR07 */
191 for (i = 0; i < 7; i++)
192 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
193 dev_priv->saveSR[i]);
195 /* CRT controller regs */
196 /* Enable CR group 0 writes */
197 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
198 for (i = 0; i <= 0x24; i++)
199 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->saveCR[i]);
201 /* Graphics controller regs */
202 for (i = 0; i < 9; i++)
203 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
204 dev_priv->saveGR[i]);
206 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
207 dev_priv->saveGR[0x10]);
208 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
209 dev_priv->saveGR[0x11]);
210 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
211 dev_priv->saveGR[0x18]);
213 /* Attribute controller registers */
214 I915_READ8(st01); /* switch back to index mode */
215 for (i = 0; i <= 0x14; i++)
216 i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
217 I915_READ8(st01); /* switch back to index mode */
218 I915_WRITE8(VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
221 /* VGA color palette registers */
222 I915_WRITE8(VGA_DACMASK, dev_priv->saveDACMASK);
225 int i915_save_state(struct drm_device *dev)
227 struct drm_i915_private *dev_priv = dev->dev_private;
230 pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
233 if (IS_I965G(dev) && IS_MOBILE(dev))
234 dev_priv->saveRENDERSTANDBY = I915_READ(MCHBAR_RENDER_STANDBY);
236 /* Hardware status page */
237 dev_priv->saveHWS = I915_READ(HWS_PGA);
239 /* Display arbitration control */
240 dev_priv->saveDSPARB = I915_READ(DSPARB);
242 /* Pipe & plane A info */
243 dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
244 dev_priv->savePIPEASRC = I915_READ(PIPEASRC);
245 dev_priv->saveFPA0 = I915_READ(FPA0);
246 dev_priv->saveFPA1 = I915_READ(FPA1);
247 dev_priv->saveDPLL_A = I915_READ(DPLL_A);
249 dev_priv->saveDPLL_A_MD = I915_READ(DPLL_A_MD);
250 dev_priv->saveHTOTAL_A = I915_READ(HTOTAL_A);
251 dev_priv->saveHBLANK_A = I915_READ(HBLANK_A);
252 dev_priv->saveHSYNC_A = I915_READ(HSYNC_A);
253 dev_priv->saveVTOTAL_A = I915_READ(VTOTAL_A);
254 dev_priv->saveVBLANK_A = I915_READ(VBLANK_A);
255 dev_priv->saveVSYNC_A = I915_READ(VSYNC_A);
256 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
258 dev_priv->saveDSPACNTR = I915_READ(DSPACNTR);
259 dev_priv->saveDSPASTRIDE = I915_READ(DSPASTRIDE);
260 dev_priv->saveDSPASIZE = I915_READ(DSPASIZE);
261 dev_priv->saveDSPAPOS = I915_READ(DSPAPOS);
262 dev_priv->saveDSPAADDR = I915_READ(DSPAADDR);
264 dev_priv->saveDSPASURF = I915_READ(DSPASURF);
265 dev_priv->saveDSPATILEOFF = I915_READ(DSPATILEOFF);
267 i915_save_palette(dev, PIPE_A);
268 dev_priv->savePIPEASTAT = I915_READ(PIPEASTAT);
270 /* Pipe & plane B info */
271 dev_priv->savePIPEBCONF = I915_READ(PIPEBCONF);
272 dev_priv->savePIPEBSRC = I915_READ(PIPEBSRC);
273 dev_priv->saveFPB0 = I915_READ(FPB0);
274 dev_priv->saveFPB1 = I915_READ(FPB1);
275 dev_priv->saveDPLL_B = I915_READ(DPLL_B);
277 dev_priv->saveDPLL_B_MD = I915_READ(DPLL_B_MD);
278 dev_priv->saveHTOTAL_B = I915_READ(HTOTAL_B);
279 dev_priv->saveHBLANK_B = I915_READ(HBLANK_B);
280 dev_priv->saveHSYNC_B = I915_READ(HSYNC_B);
281 dev_priv->saveVTOTAL_B = I915_READ(VTOTAL_B);
282 dev_priv->saveVBLANK_B = I915_READ(VBLANK_B);
283 dev_priv->saveVSYNC_B = I915_READ(VSYNC_B);
284 dev_priv->saveBCLRPAT_A = I915_READ(BCLRPAT_A);
286 dev_priv->saveDSPBCNTR = I915_READ(DSPBCNTR);
287 dev_priv->saveDSPBSTRIDE = I915_READ(DSPBSTRIDE);
288 dev_priv->saveDSPBSIZE = I915_READ(DSPBSIZE);
289 dev_priv->saveDSPBPOS = I915_READ(DSPBPOS);
290 dev_priv->saveDSPBADDR = I915_READ(DSPBADDR);
291 if (IS_I965GM(dev) || IS_GM45(dev)) {
292 dev_priv->saveDSPBSURF = I915_READ(DSPBSURF);
293 dev_priv->saveDSPBTILEOFF = I915_READ(DSPBTILEOFF);
295 i915_save_palette(dev, PIPE_B);
296 dev_priv->savePIPEBSTAT = I915_READ(PIPEBSTAT);
299 dev_priv->saveCURACNTR = I915_READ(CURACNTR);
300 dev_priv->saveCURAPOS = I915_READ(CURAPOS);
301 dev_priv->saveCURABASE = I915_READ(CURABASE);
302 dev_priv->saveCURBCNTR = I915_READ(CURBCNTR);
303 dev_priv->saveCURBPOS = I915_READ(CURBPOS);
304 dev_priv->saveCURBBASE = I915_READ(CURBBASE);
306 dev_priv->saveCURSIZE = I915_READ(CURSIZE);
309 dev_priv->saveADPA = I915_READ(ADPA);
312 dev_priv->savePP_CONTROL = I915_READ(PP_CONTROL);
313 dev_priv->savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
314 dev_priv->saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
316 dev_priv->saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
317 if (IS_MOBILE(dev) && !IS_I830(dev))
318 dev_priv->saveLVDS = I915_READ(LVDS);
319 if (!IS_I830(dev) && !IS_845G(dev))
320 dev_priv->savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
321 dev_priv->savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
322 dev_priv->savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
323 dev_priv->savePP_DIVISOR = I915_READ(PP_DIVISOR);
325 /* Display Port state */
326 if (SUPPORTS_INTEGRATED_DP(dev)) {
327 dev_priv->saveDP_B = I915_READ(DP_B);
328 dev_priv->saveDP_C = I915_READ(DP_C);
329 dev_priv->saveDP_D = I915_READ(DP_D);
330 dev_priv->savePIPEA_GMCH_DATA_M = I915_READ(PIPEA_GMCH_DATA_M);
331 dev_priv->savePIPEB_GMCH_DATA_M = I915_READ(PIPEB_GMCH_DATA_M);
332 dev_priv->savePIPEA_GMCH_DATA_N = I915_READ(PIPEA_GMCH_DATA_N);
333 dev_priv->savePIPEB_GMCH_DATA_N = I915_READ(PIPEB_GMCH_DATA_N);
334 dev_priv->savePIPEA_DP_LINK_M = I915_READ(PIPEA_DP_LINK_M);
335 dev_priv->savePIPEB_DP_LINK_M = I915_READ(PIPEB_DP_LINK_M);
336 dev_priv->savePIPEA_DP_LINK_N = I915_READ(PIPEA_DP_LINK_N);
337 dev_priv->savePIPEB_DP_LINK_N = I915_READ(PIPEB_DP_LINK_N);
339 /* FIXME: save TV & SDVO state */
342 dev_priv->saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
343 dev_priv->saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
344 dev_priv->saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
345 dev_priv->saveFBC_CONTROL = I915_READ(FBC_CONTROL);
347 /* Interrupt state */
348 dev_priv->saveIIR = I915_READ(IIR);
349 dev_priv->saveIER = I915_READ(IER);
350 dev_priv->saveIMR = I915_READ(IMR);
353 dev_priv->saveVGA0 = I915_READ(VGA0);
354 dev_priv->saveVGA1 = I915_READ(VGA1);
355 dev_priv->saveVGA_PD = I915_READ(VGA_PD);
356 dev_priv->saveVGACNTRL = I915_READ(VGACNTRL);
358 /* Clock gating state */
359 dev_priv->saveD_STATE = I915_READ(D_STATE);
360 dev_priv->saveCG_2D_DIS = I915_READ(CG_2D_DIS);
362 /* Cache mode state */
363 dev_priv->saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
365 /* Memory Arbitration state */
366 dev_priv->saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
369 for (i = 0; i < 16; i++) {
370 dev_priv->saveSWF0[i] = I915_READ(SWF00 + (i << 2));
371 dev_priv->saveSWF1[i] = I915_READ(SWF10 + (i << 2));
373 for (i = 0; i < 3; i++)
374 dev_priv->saveSWF2[i] = I915_READ(SWF30 + (i << 2));
378 for (i = 0; i < 16; i++)
379 dev_priv->saveFENCE[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
381 for (i = 0; i < 8; i++)
382 dev_priv->saveFENCE[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
384 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
385 for (i = 0; i < 8; i++)
386 dev_priv->saveFENCE[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
393 int i915_restore_state(struct drm_device *dev)
395 struct drm_i915_private *dev_priv = dev->dev_private;
398 pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
401 if (IS_I965G(dev) && IS_MOBILE(dev))
402 I915_WRITE(MCHBAR_RENDER_STANDBY, dev_priv->saveRENDERSTANDBY);
404 /* Hardware status page */
405 I915_WRITE(HWS_PGA, dev_priv->saveHWS);
407 /* Display arbitration */
408 I915_WRITE(DSPARB, dev_priv->saveDSPARB);
412 for (i = 0; i < 16; i++)
413 I915_WRITE64(FENCE_REG_965_0 + (i * 8), dev_priv->saveFENCE[i]);
415 for (i = 0; i < 8; i++)
416 I915_WRITE(FENCE_REG_830_0 + (i * 4), dev_priv->saveFENCE[i]);
417 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
418 for (i = 0; i < 8; i++)
419 I915_WRITE(FENCE_REG_945_8 + (i * 4), dev_priv->saveFENCE[i+8]);
422 /* Display port ratios (must be done before clock is set) */
423 if (SUPPORTS_INTEGRATED_DP(dev)) {
424 I915_WRITE(PIPEA_GMCH_DATA_M, dev_priv->savePIPEA_GMCH_DATA_M);
425 I915_WRITE(PIPEB_GMCH_DATA_M, dev_priv->savePIPEB_GMCH_DATA_M);
426 I915_WRITE(PIPEA_GMCH_DATA_N, dev_priv->savePIPEA_GMCH_DATA_N);
427 I915_WRITE(PIPEB_GMCH_DATA_N, dev_priv->savePIPEB_GMCH_DATA_N);
428 I915_WRITE(PIPEA_DP_LINK_M, dev_priv->savePIPEA_DP_LINK_M);
429 I915_WRITE(PIPEB_DP_LINK_M, dev_priv->savePIPEB_DP_LINK_M);
430 I915_WRITE(PIPEA_DP_LINK_N, dev_priv->savePIPEA_DP_LINK_N);
431 I915_WRITE(PIPEB_DP_LINK_N, dev_priv->savePIPEB_DP_LINK_N);
434 /* Pipe & plane A info */
435 /* Prime the clock */
436 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
437 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A &
441 I915_WRITE(FPA0, dev_priv->saveFPA0);
442 I915_WRITE(FPA1, dev_priv->saveFPA1);
443 /* Actually enable it */
444 I915_WRITE(DPLL_A, dev_priv->saveDPLL_A);
447 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
451 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
452 I915_WRITE(HBLANK_A, dev_priv->saveHBLANK_A);
453 I915_WRITE(HSYNC_A, dev_priv->saveHSYNC_A);
454 I915_WRITE(VTOTAL_A, dev_priv->saveVTOTAL_A);
455 I915_WRITE(VBLANK_A, dev_priv->saveVBLANK_A);
456 I915_WRITE(VSYNC_A, dev_priv->saveVSYNC_A);
457 I915_WRITE(BCLRPAT_A, dev_priv->saveBCLRPAT_A);
459 /* Restore plane info */
460 I915_WRITE(DSPASIZE, dev_priv->saveDSPASIZE);
461 I915_WRITE(DSPAPOS, dev_priv->saveDSPAPOS);
462 I915_WRITE(PIPEASRC, dev_priv->savePIPEASRC);
463 I915_WRITE(DSPAADDR, dev_priv->saveDSPAADDR);
464 I915_WRITE(DSPASTRIDE, dev_priv->saveDSPASTRIDE);
466 I915_WRITE(DSPASURF, dev_priv->saveDSPASURF);
467 I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
470 I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
472 i915_restore_palette(dev, PIPE_A);
473 /* Enable the plane */
474 I915_WRITE(DSPACNTR, dev_priv->saveDSPACNTR);
475 I915_WRITE(DSPAADDR, I915_READ(DSPAADDR));
477 /* Pipe & plane B info */
478 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
479 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B &
483 I915_WRITE(FPB0, dev_priv->saveFPB0);
484 I915_WRITE(FPB1, dev_priv->saveFPB1);
485 /* Actually enable it */
486 I915_WRITE(DPLL_B, dev_priv->saveDPLL_B);
489 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
493 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
494 I915_WRITE(HBLANK_B, dev_priv->saveHBLANK_B);
495 I915_WRITE(HSYNC_B, dev_priv->saveHSYNC_B);
496 I915_WRITE(VTOTAL_B, dev_priv->saveVTOTAL_B);
497 I915_WRITE(VBLANK_B, dev_priv->saveVBLANK_B);
498 I915_WRITE(VSYNC_B, dev_priv->saveVSYNC_B);
499 I915_WRITE(BCLRPAT_B, dev_priv->saveBCLRPAT_B);
501 /* Restore plane info */
502 I915_WRITE(DSPBSIZE, dev_priv->saveDSPBSIZE);
503 I915_WRITE(DSPBPOS, dev_priv->saveDSPBPOS);
504 I915_WRITE(PIPEBSRC, dev_priv->savePIPEBSRC);
505 I915_WRITE(DSPBADDR, dev_priv->saveDSPBADDR);
506 I915_WRITE(DSPBSTRIDE, dev_priv->saveDSPBSTRIDE);
508 I915_WRITE(DSPBSURF, dev_priv->saveDSPBSURF);
509 I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
512 I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
514 i915_restore_palette(dev, PIPE_B);
515 /* Enable the plane */
516 I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
517 I915_WRITE(DSPBADDR, I915_READ(DSPBADDR));
520 I915_WRITE(CURAPOS, dev_priv->saveCURAPOS);
521 I915_WRITE(CURACNTR, dev_priv->saveCURACNTR);
522 I915_WRITE(CURABASE, dev_priv->saveCURABASE);
523 I915_WRITE(CURBPOS, dev_priv->saveCURBPOS);
524 I915_WRITE(CURBCNTR, dev_priv->saveCURBCNTR);
525 I915_WRITE(CURBBASE, dev_priv->saveCURBBASE);
527 I915_WRITE(CURSIZE, dev_priv->saveCURSIZE);
530 I915_WRITE(ADPA, dev_priv->saveADPA);
534 I915_WRITE(BLC_PWM_CTL2, dev_priv->saveBLC_PWM_CTL2);
535 if (IS_MOBILE(dev) && !IS_I830(dev))
536 I915_WRITE(LVDS, dev_priv->saveLVDS);
537 if (!IS_I830(dev) && !IS_845G(dev))
538 I915_WRITE(PFIT_CONTROL, dev_priv->savePFIT_CONTROL);
540 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->savePFIT_PGM_RATIOS);
541 I915_WRITE(BLC_PWM_CTL, dev_priv->saveBLC_PWM_CTL);
542 I915_WRITE(PP_ON_DELAYS, dev_priv->savePP_ON_DELAYS);
543 I915_WRITE(PP_OFF_DELAYS, dev_priv->savePP_OFF_DELAYS);
544 I915_WRITE(PP_DIVISOR, dev_priv->savePP_DIVISOR);
545 I915_WRITE(PP_CONTROL, dev_priv->savePP_CONTROL);
547 /* Display Port state */
548 if (SUPPORTS_INTEGRATED_DP(dev)) {
549 I915_WRITE(DP_B, dev_priv->saveDP_B);
550 I915_WRITE(DP_C, dev_priv->saveDP_C);
551 I915_WRITE(DP_D, dev_priv->saveDP_D);
553 /* FIXME: restore TV & SDVO state */
556 I915_WRITE(FBC_CFB_BASE, dev_priv->saveFBC_CFB_BASE);
557 I915_WRITE(FBC_LL_BASE, dev_priv->saveFBC_LL_BASE);
558 I915_WRITE(FBC_CONTROL2, dev_priv->saveFBC_CONTROL2);
559 I915_WRITE(FBC_CONTROL, dev_priv->saveFBC_CONTROL);
562 I915_WRITE(VGACNTRL, dev_priv->saveVGACNTRL);
563 I915_WRITE(VGA0, dev_priv->saveVGA0);
564 I915_WRITE(VGA1, dev_priv->saveVGA1);
565 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
568 /* Clock gating state */
569 I915_WRITE (D_STATE, dev_priv->saveD_STATE);
570 I915_WRITE (CG_2D_DIS, dev_priv->saveCG_2D_DIS);
572 /* Cache mode state */
573 I915_WRITE (CACHE_MODE_0, dev_priv->saveCACHE_MODE_0 | 0xffff0000);
575 /* Memory arbitration state */
576 I915_WRITE (MI_ARB_STATE, dev_priv->saveMI_ARB_STATE | 0xffff0000);
578 for (i = 0; i < 16; i++) {
579 I915_WRITE(SWF00 + (i << 2), dev_priv->saveSWF0[i]);
580 I915_WRITE(SWF10 + (i << 2), dev_priv->saveSWF1[i+7]);
582 for (i = 0; i < 3; i++)
583 I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
585 i915_restore_vga(dev);