2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
24 #include "kvm_cache_regs.h"
26 #include <linux/kvm_host.h>
27 #include <linux/types.h>
28 #include <linux/string.h>
30 #include <linux/highmem.h>
31 #include <linux/module.h>
32 #include <linux/swap.h>
33 #include <linux/hugetlb.h>
34 #include <linux/compiler.h>
35 #include <linux/srcu.h>
36 #include <linux/slab.h>
37 #include <linux/uaccess.h>
40 #include <asm/cmpxchg.h>
45 * When setting this variable to true it enables Two-Dimensional-Paging
46 * where the hardware walks 2 page tables:
47 * 1. the guest-virtual to guest-physical
48 * 2. while doing 1. it walks guest-physical to host-physical
49 * If the hardware supports that we don't need to do shadow paging.
51 bool tdp_enabled = false;
55 AUDIT_POST_PAGE_FAULT,
62 char *audit_point_name[] = {
75 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
76 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
80 #define pgprintk(x...) do { } while (0)
81 #define rmap_printk(x...) do { } while (0)
87 module_param(dbg, bool, 0644);
90 static int oos_shadow = 1;
91 module_param(oos_shadow, bool, 0644);
94 #define ASSERT(x) do { } while (0)
98 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
99 __FILE__, __LINE__, #x); \
103 #define PTE_PREFETCH_NUM 8
105 #define PT_FIRST_AVAIL_BITS_SHIFT 9
106 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
108 #define PT64_LEVEL_BITS 9
110 #define PT64_LEVEL_SHIFT(level) \
111 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
113 #define PT64_INDEX(address, level)\
114 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
117 #define PT32_LEVEL_BITS 10
119 #define PT32_LEVEL_SHIFT(level) \
120 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
122 #define PT32_LVL_OFFSET_MASK(level) \
123 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
124 * PT32_LEVEL_BITS))) - 1))
126 #define PT32_INDEX(address, level)\
127 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
130 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
131 #define PT64_DIR_BASE_ADDR_MASK \
132 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
133 #define PT64_LVL_ADDR_MASK(level) \
134 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
135 * PT64_LEVEL_BITS))) - 1))
136 #define PT64_LVL_OFFSET_MASK(level) \
137 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
138 * PT64_LEVEL_BITS))) - 1))
140 #define PT32_BASE_ADDR_MASK PAGE_MASK
141 #define PT32_DIR_BASE_ADDR_MASK \
142 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
143 #define PT32_LVL_ADDR_MASK(level) \
144 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
145 * PT32_LEVEL_BITS))) - 1))
147 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
150 #define PTE_LIST_EXT 4
152 #define ACC_EXEC_MASK 1
153 #define ACC_WRITE_MASK PT_WRITABLE_MASK
154 #define ACC_USER_MASK PT_USER_MASK
155 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
157 #include <trace/events/kvm.h>
159 #define CREATE_TRACE_POINTS
160 #include "mmutrace.h"
162 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
164 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
166 struct pte_list_desc {
167 u64 *sptes[PTE_LIST_EXT];
168 struct pte_list_desc *more;
171 struct kvm_shadow_walk_iterator {
179 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
180 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
181 shadow_walk_okay(&(_walker)); \
182 shadow_walk_next(&(_walker)))
184 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
185 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
186 shadow_walk_okay(&(_walker)) && \
187 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
188 __shadow_walk_next(&(_walker), spte))
190 static struct kmem_cache *pte_list_desc_cache;
191 static struct kmem_cache *mmu_page_header_cache;
192 static struct percpu_counter kvm_total_used_mmu_pages;
194 static u64 __read_mostly shadow_nx_mask;
195 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
196 static u64 __read_mostly shadow_user_mask;
197 static u64 __read_mostly shadow_accessed_mask;
198 static u64 __read_mostly shadow_dirty_mask;
199 static u64 __read_mostly shadow_mmio_mask;
201 static void mmu_spte_set(u64 *sptep, u64 spte);
203 void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask)
205 shadow_mmio_mask = mmio_mask;
207 EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask);
209 static void mark_mmio_spte(u64 *sptep, u64 gfn, unsigned access)
211 access &= ACC_WRITE_MASK | ACC_USER_MASK;
213 trace_mark_mmio_spte(sptep, gfn, access);
214 mmu_spte_set(sptep, shadow_mmio_mask | access | gfn << PAGE_SHIFT);
217 static bool is_mmio_spte(u64 spte)
219 return (spte & shadow_mmio_mask) == shadow_mmio_mask;
222 static gfn_t get_mmio_spte_gfn(u64 spte)
224 return (spte & ~shadow_mmio_mask) >> PAGE_SHIFT;
227 static unsigned get_mmio_spte_access(u64 spte)
229 return (spte & ~shadow_mmio_mask) & ~PAGE_MASK;
232 static bool set_mmio_spte(u64 *sptep, gfn_t gfn, pfn_t pfn, unsigned access)
234 if (unlikely(is_noslot_pfn(pfn))) {
235 mark_mmio_spte(sptep, gfn, access);
242 static inline u64 rsvd_bits(int s, int e)
244 return ((1ULL << (e - s + 1)) - 1) << s;
247 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
248 u64 dirty_mask, u64 nx_mask, u64 x_mask)
250 shadow_user_mask = user_mask;
251 shadow_accessed_mask = accessed_mask;
252 shadow_dirty_mask = dirty_mask;
253 shadow_nx_mask = nx_mask;
254 shadow_x_mask = x_mask;
256 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
258 static int is_cpuid_PSE36(void)
263 static int is_nx(struct kvm_vcpu *vcpu)
265 return vcpu->arch.efer & EFER_NX;
268 static int is_shadow_present_pte(u64 pte)
270 return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
273 static int is_large_pte(u64 pte)
275 return pte & PT_PAGE_SIZE_MASK;
278 static int is_dirty_gpte(unsigned long pte)
280 return pte & PT_DIRTY_MASK;
283 static int is_rmap_spte(u64 pte)
285 return is_shadow_present_pte(pte);
288 static int is_last_spte(u64 pte, int level)
290 if (level == PT_PAGE_TABLE_LEVEL)
292 if (is_large_pte(pte))
297 static pfn_t spte_to_pfn(u64 pte)
299 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
302 static gfn_t pse36_gfn_delta(u32 gpte)
304 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
306 return (gpte & PT32_DIR_PSE36_MASK) << shift;
310 static void __set_spte(u64 *sptep, u64 spte)
315 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
320 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
322 return xchg(sptep, spte);
325 static u64 __get_spte_lockless(u64 *sptep)
327 return ACCESS_ONCE(*sptep);
330 static bool __check_direct_spte_mmio_pf(u64 spte)
332 /* It is valid if the spte is zapped. */
344 static void count_spte_clear(u64 *sptep, u64 spte)
346 struct kvm_mmu_page *sp = page_header(__pa(sptep));
348 if (is_shadow_present_pte(spte))
351 /* Ensure the spte is completely set before we increase the count */
353 sp->clear_spte_count++;
356 static void __set_spte(u64 *sptep, u64 spte)
358 union split_spte *ssptep, sspte;
360 ssptep = (union split_spte *)sptep;
361 sspte = (union split_spte)spte;
363 ssptep->spte_high = sspte.spte_high;
366 * If we map the spte from nonpresent to present, We should store
367 * the high bits firstly, then set present bit, so cpu can not
368 * fetch this spte while we are setting the spte.
372 ssptep->spte_low = sspte.spte_low;
375 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
377 union split_spte *ssptep, sspte;
379 ssptep = (union split_spte *)sptep;
380 sspte = (union split_spte)spte;
382 ssptep->spte_low = sspte.spte_low;
385 * If we map the spte from present to nonpresent, we should clear
386 * present bit firstly to avoid vcpu fetch the old high bits.
390 ssptep->spte_high = sspte.spte_high;
391 count_spte_clear(sptep, spte);
394 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
396 union split_spte *ssptep, sspte, orig;
398 ssptep = (union split_spte *)sptep;
399 sspte = (union split_spte)spte;
401 /* xchg acts as a barrier before the setting of the high bits */
402 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
403 orig.spte_high = ssptep->spte_high = sspte.spte_high;
404 count_spte_clear(sptep, spte);
410 * The idea using the light way get the spte on x86_32 guest is from
411 * gup_get_pte(arch/x86/mm/gup.c).
412 * The difference is we can not catch the spte tlb flush if we leave
413 * guest mode, so we emulate it by increase clear_spte_count when spte
416 static u64 __get_spte_lockless(u64 *sptep)
418 struct kvm_mmu_page *sp = page_header(__pa(sptep));
419 union split_spte spte, *orig = (union split_spte *)sptep;
423 count = sp->clear_spte_count;
426 spte.spte_low = orig->spte_low;
429 spte.spte_high = orig->spte_high;
432 if (unlikely(spte.spte_low != orig->spte_low ||
433 count != sp->clear_spte_count))
439 static bool __check_direct_spte_mmio_pf(u64 spte)
441 union split_spte sspte = (union split_spte)spte;
442 u32 high_mmio_mask = shadow_mmio_mask >> 32;
444 /* It is valid if the spte is zapped. */
448 /* It is valid if the spte is being zapped. */
449 if (sspte.spte_low == 0ull &&
450 (sspte.spte_high & high_mmio_mask) == high_mmio_mask)
457 static bool spte_has_volatile_bits(u64 spte)
459 if (!shadow_accessed_mask)
462 if (!is_shadow_present_pte(spte))
465 if ((spte & shadow_accessed_mask) &&
466 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
472 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
474 return (old_spte & bit_mask) && !(new_spte & bit_mask);
477 /* Rules for using mmu_spte_set:
478 * Set the sptep from nonpresent to present.
479 * Note: the sptep being assigned *must* be either not present
480 * or in a state where the hardware will not attempt to update
483 static void mmu_spte_set(u64 *sptep, u64 new_spte)
485 WARN_ON(is_shadow_present_pte(*sptep));
486 __set_spte(sptep, new_spte);
489 /* Rules for using mmu_spte_update:
490 * Update the state bits, it means the mapped pfn is not changged.
492 static void mmu_spte_update(u64 *sptep, u64 new_spte)
494 u64 mask, old_spte = *sptep;
496 WARN_ON(!is_rmap_spte(new_spte));
498 if (!is_shadow_present_pte(old_spte))
499 return mmu_spte_set(sptep, new_spte);
501 new_spte |= old_spte & shadow_dirty_mask;
503 mask = shadow_accessed_mask;
504 if (is_writable_pte(old_spte))
505 mask |= shadow_dirty_mask;
507 if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
508 __update_clear_spte_fast(sptep, new_spte);
510 old_spte = __update_clear_spte_slow(sptep, new_spte);
512 if (!shadow_accessed_mask)
515 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
516 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
517 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
518 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
522 * Rules for using mmu_spte_clear_track_bits:
523 * It sets the sptep from present to nonpresent, and track the
524 * state bits, it is used to clear the last level sptep.
526 static int mmu_spte_clear_track_bits(u64 *sptep)
529 u64 old_spte = *sptep;
531 if (!spte_has_volatile_bits(old_spte))
532 __update_clear_spte_fast(sptep, 0ull);
534 old_spte = __update_clear_spte_slow(sptep, 0ull);
536 if (!is_rmap_spte(old_spte))
539 pfn = spte_to_pfn(old_spte);
540 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
541 kvm_set_pfn_accessed(pfn);
542 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
543 kvm_set_pfn_dirty(pfn);
548 * Rules for using mmu_spte_clear_no_track:
549 * Directly clear spte without caring the state bits of sptep,
550 * it is used to set the upper level spte.
552 static void mmu_spte_clear_no_track(u64 *sptep)
554 __update_clear_spte_fast(sptep, 0ull);
557 static u64 mmu_spte_get_lockless(u64 *sptep)
559 return __get_spte_lockless(sptep);
562 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
565 atomic_inc(&vcpu->kvm->arch.reader_counter);
567 /* Increase the counter before walking shadow page table */
568 smp_mb__after_atomic_inc();
571 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
573 /* Decrease the counter after walking shadow page table finished */
574 smp_mb__before_atomic_dec();
575 atomic_dec(&vcpu->kvm->arch.reader_counter);
579 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
580 struct kmem_cache *base_cache, int min)
584 if (cache->nobjs >= min)
586 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
587 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
590 cache->objects[cache->nobjs++] = obj;
595 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
596 struct kmem_cache *cache)
599 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
602 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
607 if (cache->nobjs >= min)
609 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
610 page = (void *)__get_free_page(GFP_KERNEL);
613 cache->objects[cache->nobjs++] = page;
618 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
621 free_page((unsigned long)mc->objects[--mc->nobjs]);
624 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
628 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
629 pte_list_desc_cache, 8 + PTE_PREFETCH_NUM);
632 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
635 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
636 mmu_page_header_cache, 4);
641 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
643 mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
644 pte_list_desc_cache);
645 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
646 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
647 mmu_page_header_cache);
650 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
656 p = mc->objects[--mc->nobjs];
660 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
662 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache,
663 sizeof(struct pte_list_desc));
666 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
668 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
671 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
673 if (!sp->role.direct)
674 return sp->gfns[index];
676 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
679 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
682 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
684 sp->gfns[index] = gfn;
688 * Return the pointer to the large page information for a given gfn,
689 * handling slots that are not large page aligned.
691 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
692 struct kvm_memory_slot *slot,
697 idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
698 (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
699 return &slot->lpage_info[level - 2][idx];
702 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
704 struct kvm_memory_slot *slot;
705 struct kvm_lpage_info *linfo;
708 slot = gfn_to_memslot(kvm, gfn);
709 for (i = PT_DIRECTORY_LEVEL;
710 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
711 linfo = lpage_info_slot(gfn, slot, i);
712 linfo->write_count += 1;
714 kvm->arch.indirect_shadow_pages++;
717 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
719 struct kvm_memory_slot *slot;
720 struct kvm_lpage_info *linfo;
723 slot = gfn_to_memslot(kvm, gfn);
724 for (i = PT_DIRECTORY_LEVEL;
725 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
726 linfo = lpage_info_slot(gfn, slot, i);
727 linfo->write_count -= 1;
728 WARN_ON(linfo->write_count < 0);
730 kvm->arch.indirect_shadow_pages--;
733 static int has_wrprotected_page(struct kvm *kvm,
737 struct kvm_memory_slot *slot;
738 struct kvm_lpage_info *linfo;
740 slot = gfn_to_memslot(kvm, gfn);
742 linfo = lpage_info_slot(gfn, slot, level);
743 return linfo->write_count;
749 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
751 unsigned long page_size;
754 page_size = kvm_host_page_size(kvm, gfn);
756 for (i = PT_PAGE_TABLE_LEVEL;
757 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
758 if (page_size >= KVM_HPAGE_SIZE(i))
767 static struct kvm_memory_slot *
768 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
771 struct kvm_memory_slot *slot;
773 slot = gfn_to_memslot(vcpu->kvm, gfn);
774 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
775 (no_dirty_log && slot->dirty_bitmap))
781 static bool mapping_level_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t large_gfn)
783 return !gfn_to_memslot_dirty_bitmap(vcpu, large_gfn, true);
786 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
788 int host_level, level, max_level;
790 host_level = host_mapping_level(vcpu->kvm, large_gfn);
792 if (host_level == PT_PAGE_TABLE_LEVEL)
795 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
796 kvm_x86_ops->get_lpage_level() : host_level;
798 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
799 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
806 * Pte mapping structures:
808 * If pte_list bit zero is zero, then pte_list point to the spte.
810 * If pte_list bit zero is one, (then pte_list & ~1) points to a struct
811 * pte_list_desc containing more mappings.
813 * Returns the number of pte entries before the spte was added or zero if
814 * the spte was not added.
817 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
818 unsigned long *pte_list)
820 struct pte_list_desc *desc;
824 rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte);
825 *pte_list = (unsigned long)spte;
826 } else if (!(*pte_list & 1)) {
827 rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte);
828 desc = mmu_alloc_pte_list_desc(vcpu);
829 desc->sptes[0] = (u64 *)*pte_list;
830 desc->sptes[1] = spte;
831 *pte_list = (unsigned long)desc | 1;
834 rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte);
835 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
836 while (desc->sptes[PTE_LIST_EXT-1] && desc->more) {
838 count += PTE_LIST_EXT;
840 if (desc->sptes[PTE_LIST_EXT-1]) {
841 desc->more = mmu_alloc_pte_list_desc(vcpu);
844 for (i = 0; desc->sptes[i]; ++i)
846 desc->sptes[i] = spte;
851 static u64 *pte_list_next(unsigned long *pte_list, u64 *spte)
853 struct pte_list_desc *desc;
859 else if (!(*pte_list & 1)) {
861 return (u64 *)*pte_list;
864 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
867 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
868 if (prev_spte == spte)
869 return desc->sptes[i];
870 prev_spte = desc->sptes[i];
878 pte_list_desc_remove_entry(unsigned long *pte_list, struct pte_list_desc *desc,
879 int i, struct pte_list_desc *prev_desc)
883 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
885 desc->sptes[i] = desc->sptes[j];
886 desc->sptes[j] = NULL;
889 if (!prev_desc && !desc->more)
890 *pte_list = (unsigned long)desc->sptes[0];
893 prev_desc->more = desc->more;
895 *pte_list = (unsigned long)desc->more | 1;
896 mmu_free_pte_list_desc(desc);
899 static void pte_list_remove(u64 *spte, unsigned long *pte_list)
901 struct pte_list_desc *desc;
902 struct pte_list_desc *prev_desc;
906 printk(KERN_ERR "pte_list_remove: %p 0->BUG\n", spte);
908 } else if (!(*pte_list & 1)) {
909 rmap_printk("pte_list_remove: %p 1->0\n", spte);
910 if ((u64 *)*pte_list != spte) {
911 printk(KERN_ERR "pte_list_remove: %p 1->BUG\n", spte);
916 rmap_printk("pte_list_remove: %p many->many\n", spte);
917 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
920 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
921 if (desc->sptes[i] == spte) {
922 pte_list_desc_remove_entry(pte_list,
930 pr_err("pte_list_remove: %p many->many\n", spte);
935 typedef void (*pte_list_walk_fn) (u64 *spte);
936 static void pte_list_walk(unsigned long *pte_list, pte_list_walk_fn fn)
938 struct pte_list_desc *desc;
944 if (!(*pte_list & 1))
945 return fn((u64 *)*pte_list);
947 desc = (struct pte_list_desc *)(*pte_list & ~1ul);
949 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i)
956 * Take gfn and return the reverse mapping to it.
958 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
960 struct kvm_memory_slot *slot;
961 struct kvm_lpage_info *linfo;
963 slot = gfn_to_memslot(kvm, gfn);
964 if (likely(level == PT_PAGE_TABLE_LEVEL))
965 return &slot->rmap[gfn - slot->base_gfn];
967 linfo = lpage_info_slot(gfn, slot, level);
969 return &linfo->rmap_pde;
972 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
974 struct kvm_mmu_page *sp;
975 unsigned long *rmapp;
977 sp = page_header(__pa(spte));
978 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
979 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
980 return pte_list_add(vcpu, spte, rmapp);
983 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
985 return pte_list_next(rmapp, spte);
988 static void rmap_remove(struct kvm *kvm, u64 *spte)
990 struct kvm_mmu_page *sp;
992 unsigned long *rmapp;
994 sp = page_header(__pa(spte));
995 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
996 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
997 pte_list_remove(spte, rmapp);
1000 static void drop_spte(struct kvm *kvm, u64 *sptep)
1002 if (mmu_spte_clear_track_bits(sptep))
1003 rmap_remove(kvm, sptep);
1006 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
1008 unsigned long *rmapp;
1010 int i, write_protected = 0;
1012 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
1014 spte = rmap_next(kvm, rmapp, NULL);
1017 BUG_ON(!(*spte & PT_PRESENT_MASK));
1018 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
1019 if (is_writable_pte(*spte)) {
1020 mmu_spte_update(spte, *spte & ~PT_WRITABLE_MASK);
1021 write_protected = 1;
1023 spte = rmap_next(kvm, rmapp, spte);
1026 /* check for huge page mappings */
1027 for (i = PT_DIRECTORY_LEVEL;
1028 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
1029 rmapp = gfn_to_rmap(kvm, gfn, i);
1030 spte = rmap_next(kvm, rmapp, NULL);
1033 BUG_ON(!(*spte & PT_PRESENT_MASK));
1034 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
1035 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
1036 if (is_writable_pte(*spte)) {
1037 drop_spte(kvm, spte);
1040 write_protected = 1;
1042 spte = rmap_next(kvm, rmapp, spte);
1046 return write_protected;
1049 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
1053 int need_tlb_flush = 0;
1055 while ((spte = rmap_next(kvm, rmapp, NULL))) {
1056 BUG_ON(!(*spte & PT_PRESENT_MASK));
1057 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
1058 drop_spte(kvm, spte);
1061 return need_tlb_flush;
1064 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
1068 u64 *spte, new_spte;
1069 pte_t *ptep = (pte_t *)data;
1072 WARN_ON(pte_huge(*ptep));
1073 new_pfn = pte_pfn(*ptep);
1074 spte = rmap_next(kvm, rmapp, NULL);
1076 BUG_ON(!is_shadow_present_pte(*spte));
1077 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
1079 if (pte_write(*ptep)) {
1080 drop_spte(kvm, spte);
1081 spte = rmap_next(kvm, rmapp, NULL);
1083 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
1084 new_spte |= (u64)new_pfn << PAGE_SHIFT;
1086 new_spte &= ~PT_WRITABLE_MASK;
1087 new_spte &= ~SPTE_HOST_WRITEABLE;
1088 new_spte &= ~shadow_accessed_mask;
1089 mmu_spte_clear_track_bits(spte);
1090 mmu_spte_set(spte, new_spte);
1091 spte = rmap_next(kvm, rmapp, spte);
1095 kvm_flush_remote_tlbs(kvm);
1100 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
1102 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
1103 unsigned long data))
1108 struct kvm_memslots *slots;
1110 slots = kvm_memslots(kvm);
1112 for (i = 0; i < slots->nmemslots; i++) {
1113 struct kvm_memory_slot *memslot = &slots->memslots[i];
1114 unsigned long start = memslot->userspace_addr;
1117 end = start + (memslot->npages << PAGE_SHIFT);
1118 if (hva >= start && hva < end) {
1119 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
1120 gfn_t gfn = memslot->base_gfn + gfn_offset;
1122 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
1124 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
1125 struct kvm_lpage_info *linfo;
1127 linfo = lpage_info_slot(gfn, memslot,
1128 PT_DIRECTORY_LEVEL + j);
1129 ret |= handler(kvm, &linfo->rmap_pde, data);
1131 trace_kvm_age_page(hva, memslot, ret);
1139 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
1141 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
1144 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
1146 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
1149 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1156 * Emulate the accessed bit for EPT, by checking if this page has
1157 * an EPT mapping, and clearing it if it does. On the next access,
1158 * a new EPT mapping will be established.
1159 * This has some overhead, but not as much as the cost of swapping
1160 * out actively used pages or breaking up actively used hugepages.
1162 if (!shadow_accessed_mask)
1163 return kvm_unmap_rmapp(kvm, rmapp, data);
1165 spte = rmap_next(kvm, rmapp, NULL);
1169 BUG_ON(!(_spte & PT_PRESENT_MASK));
1170 _young = _spte & PT_ACCESSED_MASK;
1173 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
1175 spte = rmap_next(kvm, rmapp, spte);
1180 static int kvm_test_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
1187 * If there's no access bit in the secondary pte set by the
1188 * hardware it's up to gup-fast/gup to set the access bit in
1189 * the primary pte or in the page structure.
1191 if (!shadow_accessed_mask)
1194 spte = rmap_next(kvm, rmapp, NULL);
1197 BUG_ON(!(_spte & PT_PRESENT_MASK));
1198 young = _spte & PT_ACCESSED_MASK;
1203 spte = rmap_next(kvm, rmapp, spte);
1209 #define RMAP_RECYCLE_THRESHOLD 1000
1211 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1213 unsigned long *rmapp;
1214 struct kvm_mmu_page *sp;
1216 sp = page_header(__pa(spte));
1218 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
1220 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
1221 kvm_flush_remote_tlbs(vcpu->kvm);
1224 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
1226 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
1229 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
1231 return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp);
1235 static int is_empty_shadow_page(u64 *spt)
1240 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1241 if (is_shadow_present_pte(*pos)) {
1242 printk(KERN_ERR "%s: %p %llx\n", __func__,
1251 * This value is the sum of all of the kvm instances's
1252 * kvm->arch.n_used_mmu_pages values. We need a global,
1253 * aggregate version in order to make the slab shrinker
1256 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
1258 kvm->arch.n_used_mmu_pages += nr;
1259 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1263 * Remove the sp from shadow page cache, after call it,
1264 * we can not find this sp from the cache, and the shadow
1265 * page table is still valid.
1266 * It should be under the protection of mmu lock.
1268 static void kvm_mmu_isolate_page(struct kvm_mmu_page *sp)
1270 ASSERT(is_empty_shadow_page(sp->spt));
1271 hlist_del(&sp->hash_link);
1272 if (!sp->role.direct)
1273 free_page((unsigned long)sp->gfns);
1277 * Free the shadow page table and the sp, we can do it
1278 * out of the protection of mmu lock.
1280 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1282 list_del(&sp->link);
1283 free_page((unsigned long)sp->spt);
1284 kmem_cache_free(mmu_page_header_cache, sp);
1287 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1289 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1292 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1293 struct kvm_mmu_page *sp, u64 *parent_pte)
1298 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1301 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1304 pte_list_remove(parent_pte, &sp->parent_ptes);
1307 static void drop_parent_pte(struct kvm_mmu_page *sp,
1310 mmu_page_remove_parent_pte(sp, parent_pte);
1311 mmu_spte_clear_no_track(parent_pte);
1314 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1315 u64 *parent_pte, int direct)
1317 struct kvm_mmu_page *sp;
1318 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache,
1320 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1322 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1324 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1325 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1326 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
1327 sp->parent_ptes = 0;
1328 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1329 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1333 static void mark_unsync(u64 *spte);
1334 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1336 pte_list_walk(&sp->parent_ptes, mark_unsync);
1339 static void mark_unsync(u64 *spte)
1341 struct kvm_mmu_page *sp;
1344 sp = page_header(__pa(spte));
1345 index = spte - sp->spt;
1346 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1348 if (sp->unsync_children++)
1350 kvm_mmu_mark_parents_unsync(sp);
1353 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1354 struct kvm_mmu_page *sp)
1359 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1363 static void nonpaging_update_pte(struct kvm_vcpu *vcpu,
1364 struct kvm_mmu_page *sp, u64 *spte,
1370 #define KVM_PAGE_ARRAY_NR 16
1372 struct kvm_mmu_pages {
1373 struct mmu_page_and_offset {
1374 struct kvm_mmu_page *sp;
1376 } page[KVM_PAGE_ARRAY_NR];
1380 #define for_each_unsync_children(bitmap, idx) \
1381 for (idx = find_first_bit(bitmap, 512); \
1383 idx = find_next_bit(bitmap, 512, idx+1))
1385 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1391 for (i=0; i < pvec->nr; i++)
1392 if (pvec->page[i].sp == sp)
1395 pvec->page[pvec->nr].sp = sp;
1396 pvec->page[pvec->nr].idx = idx;
1398 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1401 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1402 struct kvm_mmu_pages *pvec)
1404 int i, ret, nr_unsync_leaf = 0;
1406 for_each_unsync_children(sp->unsync_child_bitmap, i) {
1407 struct kvm_mmu_page *child;
1408 u64 ent = sp->spt[i];
1410 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1411 goto clear_child_bitmap;
1413 child = page_header(ent & PT64_BASE_ADDR_MASK);
1415 if (child->unsync_children) {
1416 if (mmu_pages_add(pvec, child, i))
1419 ret = __mmu_unsync_walk(child, pvec);
1421 goto clear_child_bitmap;
1423 nr_unsync_leaf += ret;
1426 } else if (child->unsync) {
1428 if (mmu_pages_add(pvec, child, i))
1431 goto clear_child_bitmap;
1436 __clear_bit(i, sp->unsync_child_bitmap);
1437 sp->unsync_children--;
1438 WARN_ON((int)sp->unsync_children < 0);
1442 return nr_unsync_leaf;
1445 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1446 struct kvm_mmu_pages *pvec)
1448 if (!sp->unsync_children)
1451 mmu_pages_add(pvec, sp, 0);
1452 return __mmu_unsync_walk(sp, pvec);
1455 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1457 WARN_ON(!sp->unsync);
1458 trace_kvm_mmu_sync_page(sp);
1460 --kvm->stat.mmu_unsync;
1463 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1464 struct list_head *invalid_list);
1465 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1466 struct list_head *invalid_list);
1468 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1469 hlist_for_each_entry(sp, pos, \
1470 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1471 if ((sp)->gfn != (gfn)) {} else
1473 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1474 hlist_for_each_entry(sp, pos, \
1475 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1476 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1477 (sp)->role.invalid) {} else
1479 /* @sp->gfn should be write-protected at the call site */
1480 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1481 struct list_head *invalid_list, bool clear_unsync)
1483 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1484 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1489 kvm_unlink_unsync_page(vcpu->kvm, sp);
1491 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1492 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1496 kvm_mmu_flush_tlb(vcpu);
1500 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1501 struct kvm_mmu_page *sp)
1503 LIST_HEAD(invalid_list);
1506 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1508 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1513 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1514 struct list_head *invalid_list)
1516 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1519 /* @gfn should be write-protected at the call site */
1520 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1522 struct kvm_mmu_page *s;
1523 struct hlist_node *node;
1524 LIST_HEAD(invalid_list);
1527 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1531 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1532 kvm_unlink_unsync_page(vcpu->kvm, s);
1533 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1534 (vcpu->arch.mmu.sync_page(vcpu, s))) {
1535 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1541 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1543 kvm_mmu_flush_tlb(vcpu);
1546 struct mmu_page_path {
1547 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1548 unsigned int idx[PT64_ROOT_LEVEL-1];
1551 #define for_each_sp(pvec, sp, parents, i) \
1552 for (i = mmu_pages_next(&pvec, &parents, -1), \
1553 sp = pvec.page[i].sp; \
1554 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1555 i = mmu_pages_next(&pvec, &parents, i))
1557 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1558 struct mmu_page_path *parents,
1563 for (n = i+1; n < pvec->nr; n++) {
1564 struct kvm_mmu_page *sp = pvec->page[n].sp;
1566 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1567 parents->idx[0] = pvec->page[n].idx;
1571 parents->parent[sp->role.level-2] = sp;
1572 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1578 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1580 struct kvm_mmu_page *sp;
1581 unsigned int level = 0;
1584 unsigned int idx = parents->idx[level];
1586 sp = parents->parent[level];
1590 --sp->unsync_children;
1591 WARN_ON((int)sp->unsync_children < 0);
1592 __clear_bit(idx, sp->unsync_child_bitmap);
1594 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1597 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1598 struct mmu_page_path *parents,
1599 struct kvm_mmu_pages *pvec)
1601 parents->parent[parent->role.level-1] = NULL;
1605 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1606 struct kvm_mmu_page *parent)
1609 struct kvm_mmu_page *sp;
1610 struct mmu_page_path parents;
1611 struct kvm_mmu_pages pages;
1612 LIST_HEAD(invalid_list);
1614 kvm_mmu_pages_init(parent, &parents, &pages);
1615 while (mmu_unsync_walk(parent, &pages)) {
1618 for_each_sp(pages, sp, parents, i)
1619 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1622 kvm_flush_remote_tlbs(vcpu->kvm);
1624 for_each_sp(pages, sp, parents, i) {
1625 kvm_sync_page(vcpu, sp, &invalid_list);
1626 mmu_pages_clear_parents(&parents);
1628 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1629 cond_resched_lock(&vcpu->kvm->mmu_lock);
1630 kvm_mmu_pages_init(parent, &parents, &pages);
1634 static void init_shadow_page_table(struct kvm_mmu_page *sp)
1638 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1642 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1650 union kvm_mmu_page_role role;
1652 struct kvm_mmu_page *sp;
1653 struct hlist_node *node;
1654 bool need_sync = false;
1656 role = vcpu->arch.mmu.base_role;
1658 role.direct = direct;
1661 role.access = access;
1662 if (!vcpu->arch.mmu.direct_map
1663 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1664 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1665 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1666 role.quadrant = quadrant;
1668 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1669 if (!need_sync && sp->unsync)
1672 if (sp->role.word != role.word)
1675 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1678 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1679 if (sp->unsync_children) {
1680 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1681 kvm_mmu_mark_parents_unsync(sp);
1682 } else if (sp->unsync)
1683 kvm_mmu_mark_parents_unsync(sp);
1685 trace_kvm_mmu_get_page(sp, false);
1688 ++vcpu->kvm->stat.mmu_cache_miss;
1689 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1694 hlist_add_head(&sp->hash_link,
1695 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1697 if (rmap_write_protect(vcpu->kvm, gfn))
1698 kvm_flush_remote_tlbs(vcpu->kvm);
1699 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1700 kvm_sync_pages(vcpu, gfn);
1702 account_shadowed(vcpu->kvm, gfn);
1704 init_shadow_page_table(sp);
1705 trace_kvm_mmu_get_page(sp, true);
1709 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1710 struct kvm_vcpu *vcpu, u64 addr)
1712 iterator->addr = addr;
1713 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1714 iterator->level = vcpu->arch.mmu.shadow_root_level;
1716 if (iterator->level == PT64_ROOT_LEVEL &&
1717 vcpu->arch.mmu.root_level < PT64_ROOT_LEVEL &&
1718 !vcpu->arch.mmu.direct_map)
1721 if (iterator->level == PT32E_ROOT_LEVEL) {
1722 iterator->shadow_addr
1723 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1724 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1726 if (!iterator->shadow_addr)
1727 iterator->level = 0;
1731 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1733 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1736 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1737 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1741 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
1744 if (is_last_spte(spte, iterator->level)) {
1745 iterator->level = 0;
1749 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
1753 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1755 return __shadow_walk_next(iterator, *iterator->sptep);
1758 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1762 spte = __pa(sp->spt)
1763 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1764 | PT_WRITABLE_MASK | PT_USER_MASK;
1765 mmu_spte_set(sptep, spte);
1768 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1770 if (is_large_pte(*sptep)) {
1771 drop_spte(vcpu->kvm, sptep);
1772 kvm_flush_remote_tlbs(vcpu->kvm);
1776 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1777 unsigned direct_access)
1779 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1780 struct kvm_mmu_page *child;
1783 * For the direct sp, if the guest pte's dirty bit
1784 * changed form clean to dirty, it will corrupt the
1785 * sp's access: allow writable in the read-only sp,
1786 * so we should update the spte at this point to get
1787 * a new sp with the correct access.
1789 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1790 if (child->role.access == direct_access)
1793 drop_parent_pte(child, sptep);
1794 kvm_flush_remote_tlbs(vcpu->kvm);
1798 static void mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
1802 struct kvm_mmu_page *child;
1805 if (is_shadow_present_pte(pte)) {
1806 if (is_last_spte(pte, sp->role.level))
1807 drop_spte(kvm, spte);
1809 child = page_header(pte & PT64_BASE_ADDR_MASK);
1810 drop_parent_pte(child, spte);
1812 } else if (is_mmio_spte(pte))
1813 mmu_spte_clear_no_track(spte);
1815 if (is_large_pte(pte))
1819 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1820 struct kvm_mmu_page *sp)
1824 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1825 mmu_page_zap_pte(kvm, sp, sp->spt + i);
1828 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1830 mmu_page_remove_parent_pte(sp, parent_pte);
1833 static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1836 struct kvm_vcpu *vcpu;
1838 kvm_for_each_vcpu(i, vcpu, kvm)
1839 vcpu->arch.last_pte_updated = NULL;
1842 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1846 while ((parent_pte = pte_list_next(&sp->parent_ptes, NULL)))
1847 drop_parent_pte(sp, parent_pte);
1850 static int mmu_zap_unsync_children(struct kvm *kvm,
1851 struct kvm_mmu_page *parent,
1852 struct list_head *invalid_list)
1855 struct mmu_page_path parents;
1856 struct kvm_mmu_pages pages;
1858 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1861 kvm_mmu_pages_init(parent, &parents, &pages);
1862 while (mmu_unsync_walk(parent, &pages)) {
1863 struct kvm_mmu_page *sp;
1865 for_each_sp(pages, sp, parents, i) {
1866 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
1867 mmu_pages_clear_parents(&parents);
1870 kvm_mmu_pages_init(parent, &parents, &pages);
1876 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1877 struct list_head *invalid_list)
1881 trace_kvm_mmu_prepare_zap_page(sp);
1882 ++kvm->stat.mmu_shadow_zapped;
1883 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
1884 kvm_mmu_page_unlink_children(kvm, sp);
1885 kvm_mmu_unlink_parents(kvm, sp);
1886 if (!sp->role.invalid && !sp->role.direct)
1887 unaccount_shadowed(kvm, sp->gfn);
1889 kvm_unlink_unsync_page(kvm, sp);
1890 if (!sp->root_count) {
1893 list_move(&sp->link, invalid_list);
1894 kvm_mod_used_mmu_pages(kvm, -1);
1896 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1897 kvm_reload_remote_mmus(kvm);
1900 sp->role.invalid = 1;
1901 kvm_mmu_reset_last_pte_updated(kvm);
1905 static void kvm_mmu_isolate_pages(struct list_head *invalid_list)
1907 struct kvm_mmu_page *sp;
1909 list_for_each_entry(sp, invalid_list, link)
1910 kvm_mmu_isolate_page(sp);
1913 static void free_pages_rcu(struct rcu_head *head)
1915 struct kvm_mmu_page *next, *sp;
1917 sp = container_of(head, struct kvm_mmu_page, rcu);
1919 if (!list_empty(&sp->link))
1920 next = list_first_entry(&sp->link,
1921 struct kvm_mmu_page, link);
1924 kvm_mmu_free_page(sp);
1929 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1930 struct list_head *invalid_list)
1932 struct kvm_mmu_page *sp;
1934 if (list_empty(invalid_list))
1937 kvm_flush_remote_tlbs(kvm);
1939 if (atomic_read(&kvm->arch.reader_counter)) {
1940 kvm_mmu_isolate_pages(invalid_list);
1941 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1942 list_del_init(invalid_list);
1944 trace_kvm_mmu_delay_free_pages(sp);
1945 call_rcu(&sp->rcu, free_pages_rcu);
1950 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1951 WARN_ON(!sp->role.invalid || sp->root_count);
1952 kvm_mmu_isolate_page(sp);
1953 kvm_mmu_free_page(sp);
1954 } while (!list_empty(invalid_list));
1959 * Changing the number of mmu pages allocated to the vm
1960 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
1962 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
1964 LIST_HEAD(invalid_list);
1966 * If we set the number of mmu pages to be smaller be than the
1967 * number of actived pages , we must to free some mmu pages before we
1971 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
1972 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
1973 !list_empty(&kvm->arch.active_mmu_pages)) {
1974 struct kvm_mmu_page *page;
1976 page = container_of(kvm->arch.active_mmu_pages.prev,
1977 struct kvm_mmu_page, link);
1978 kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
1980 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1981 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
1984 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
1987 static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
1989 struct kvm_mmu_page *sp;
1990 struct hlist_node *node;
1991 LIST_HEAD(invalid_list);
1994 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
1997 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
1998 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2001 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2003 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2007 static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
2009 struct kvm_mmu_page *sp;
2010 struct hlist_node *node;
2011 LIST_HEAD(invalid_list);
2013 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
2014 pgprintk("%s: zap %llx %x\n",
2015 __func__, gfn, sp->role.word);
2016 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2018 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2021 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
2023 int slot = memslot_id(kvm, gfn);
2024 struct kvm_mmu_page *sp = page_header(__pa(pte));
2026 __set_bit(slot, sp->slot_bitmap);
2030 * The function is based on mtrr_type_lookup() in
2031 * arch/x86/kernel/cpu/mtrr/generic.c
2033 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
2038 u8 prev_match, curr_match;
2039 int num_var_ranges = KVM_NR_VAR_MTRR;
2041 if (!mtrr_state->enabled)
2044 /* Make end inclusive end, instead of exclusive */
2047 /* Look in fixed ranges. Just return the type as per start */
2048 if (mtrr_state->have_fixed && (start < 0x100000)) {
2051 if (start < 0x80000) {
2053 idx += (start >> 16);
2054 return mtrr_state->fixed_ranges[idx];
2055 } else if (start < 0xC0000) {
2057 idx += ((start - 0x80000) >> 14);
2058 return mtrr_state->fixed_ranges[idx];
2059 } else if (start < 0x1000000) {
2061 idx += ((start - 0xC0000) >> 12);
2062 return mtrr_state->fixed_ranges[idx];
2067 * Look in variable ranges
2068 * Look of multiple ranges matching this address and pick type
2069 * as per MTRR precedence
2071 if (!(mtrr_state->enabled & 2))
2072 return mtrr_state->def_type;
2075 for (i = 0; i < num_var_ranges; ++i) {
2076 unsigned short start_state, end_state;
2078 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
2081 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
2082 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
2083 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
2084 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
2086 start_state = ((start & mask) == (base & mask));
2087 end_state = ((end & mask) == (base & mask));
2088 if (start_state != end_state)
2091 if ((start & mask) != (base & mask))
2094 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
2095 if (prev_match == 0xFF) {
2096 prev_match = curr_match;
2100 if (prev_match == MTRR_TYPE_UNCACHABLE ||
2101 curr_match == MTRR_TYPE_UNCACHABLE)
2102 return MTRR_TYPE_UNCACHABLE;
2104 if ((prev_match == MTRR_TYPE_WRBACK &&
2105 curr_match == MTRR_TYPE_WRTHROUGH) ||
2106 (prev_match == MTRR_TYPE_WRTHROUGH &&
2107 curr_match == MTRR_TYPE_WRBACK)) {
2108 prev_match = MTRR_TYPE_WRTHROUGH;
2109 curr_match = MTRR_TYPE_WRTHROUGH;
2112 if (prev_match != curr_match)
2113 return MTRR_TYPE_UNCACHABLE;
2116 if (prev_match != 0xFF)
2119 return mtrr_state->def_type;
2122 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
2126 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
2127 (gfn << PAGE_SHIFT) + PAGE_SIZE);
2128 if (mtrr == 0xfe || mtrr == 0xff)
2129 mtrr = MTRR_TYPE_WRBACK;
2132 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
2134 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2136 trace_kvm_mmu_unsync_page(sp);
2137 ++vcpu->kvm->stat.mmu_unsync;
2140 kvm_mmu_mark_parents_unsync(sp);
2143 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
2145 struct kvm_mmu_page *s;
2146 struct hlist_node *node;
2148 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2151 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
2152 __kvm_unsync_page(vcpu, s);
2156 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
2159 struct kvm_mmu_page *s;
2160 struct hlist_node *node;
2161 bool need_unsync = false;
2163 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
2167 if (s->role.level != PT_PAGE_TABLE_LEVEL)
2170 if (!need_unsync && !s->unsync) {
2177 kvm_unsync_pages(vcpu, gfn);
2181 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2182 unsigned pte_access, int user_fault,
2183 int write_fault, int level,
2184 gfn_t gfn, pfn_t pfn, bool speculative,
2185 bool can_unsync, bool host_writable)
2187 u64 spte, entry = *sptep;
2190 if (set_mmio_spte(sptep, gfn, pfn, pte_access))
2194 * We don't set the accessed bit, since we sometimes want to see
2195 * whether the guest actually used the pte (in order to detect
2198 spte = PT_PRESENT_MASK;
2200 spte |= shadow_accessed_mask;
2202 if (pte_access & ACC_EXEC_MASK)
2203 spte |= shadow_x_mask;
2205 spte |= shadow_nx_mask;
2206 if (pte_access & ACC_USER_MASK)
2207 spte |= shadow_user_mask;
2208 if (level > PT_PAGE_TABLE_LEVEL)
2209 spte |= PT_PAGE_SIZE_MASK;
2211 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
2212 kvm_is_mmio_pfn(pfn));
2215 spte |= SPTE_HOST_WRITEABLE;
2217 pte_access &= ~ACC_WRITE_MASK;
2219 spte |= (u64)pfn << PAGE_SHIFT;
2221 if ((pte_access & ACC_WRITE_MASK)
2222 || (!vcpu->arch.mmu.direct_map && write_fault
2223 && !is_write_protection(vcpu) && !user_fault)) {
2225 if (level > PT_PAGE_TABLE_LEVEL &&
2226 has_wrprotected_page(vcpu->kvm, gfn, level)) {
2228 drop_spte(vcpu->kvm, sptep);
2232 spte |= PT_WRITABLE_MASK;
2234 if (!vcpu->arch.mmu.direct_map
2235 && !(pte_access & ACC_WRITE_MASK)) {
2236 spte &= ~PT_USER_MASK;
2238 * If we converted a user page to a kernel page,
2239 * so that the kernel can write to it when cr0.wp=0,
2240 * then we should prevent the kernel from executing it
2241 * if SMEP is enabled.
2243 if (kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
2244 spte |= PT64_NX_MASK;
2248 * Optimization: for pte sync, if spte was writable the hash
2249 * lookup is unnecessary (and expensive). Write protection
2250 * is responsibility of mmu_get_page / kvm_sync_page.
2251 * Same reasoning can be applied to dirty page accounting.
2253 if (!can_unsync && is_writable_pte(*sptep))
2256 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2257 pgprintk("%s: found shadow page for %llx, marking ro\n",
2260 pte_access &= ~ACC_WRITE_MASK;
2261 if (is_writable_pte(spte))
2262 spte &= ~PT_WRITABLE_MASK;
2266 if (pte_access & ACC_WRITE_MASK)
2267 mark_page_dirty(vcpu->kvm, gfn);
2270 mmu_spte_update(sptep, spte);
2272 * If we overwrite a writable spte with a read-only one we
2273 * should flush remote TLBs. Otherwise rmap_write_protect
2274 * will find a read-only spte, even though the writable spte
2275 * might be cached on a CPU's TLB.
2277 if (is_writable_pte(entry) && !is_writable_pte(*sptep))
2278 kvm_flush_remote_tlbs(vcpu->kvm);
2283 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2284 unsigned pt_access, unsigned pte_access,
2285 int user_fault, int write_fault,
2286 int *emulate, int level, gfn_t gfn,
2287 pfn_t pfn, bool speculative,
2290 int was_rmapped = 0;
2293 pgprintk("%s: spte %llx access %x write_fault %d"
2294 " user_fault %d gfn %llx\n",
2295 __func__, *sptep, pt_access,
2296 write_fault, user_fault, gfn);
2298 if (is_rmap_spte(*sptep)) {
2300 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2301 * the parent of the now unreachable PTE.
2303 if (level > PT_PAGE_TABLE_LEVEL &&
2304 !is_large_pte(*sptep)) {
2305 struct kvm_mmu_page *child;
2308 child = page_header(pte & PT64_BASE_ADDR_MASK);
2309 drop_parent_pte(child, sptep);
2310 kvm_flush_remote_tlbs(vcpu->kvm);
2311 } else if (pfn != spte_to_pfn(*sptep)) {
2312 pgprintk("hfn old %llx new %llx\n",
2313 spte_to_pfn(*sptep), pfn);
2314 drop_spte(vcpu->kvm, sptep);
2315 kvm_flush_remote_tlbs(vcpu->kvm);
2320 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2321 level, gfn, pfn, speculative, true,
2325 kvm_mmu_flush_tlb(vcpu);
2328 if (unlikely(is_mmio_spte(*sptep) && emulate))
2331 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2332 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2333 is_large_pte(*sptep)? "2MB" : "4kB",
2334 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2336 if (!was_rmapped && is_large_pte(*sptep))
2337 ++vcpu->kvm->stat.lpages;
2339 if (is_shadow_present_pte(*sptep)) {
2340 page_header_update_slot(vcpu->kvm, sptep, gfn);
2342 rmap_count = rmap_add(vcpu, sptep, gfn);
2343 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2344 rmap_recycle(vcpu, sptep, gfn);
2347 kvm_release_pfn_clean(pfn);
2349 vcpu->arch.last_pte_updated = sptep;
2350 vcpu->arch.last_pte_gfn = gfn;
2354 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2358 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2361 struct kvm_memory_slot *slot;
2364 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2366 get_page(fault_page);
2367 return page_to_pfn(fault_page);
2370 hva = gfn_to_hva_memslot(slot, gfn);
2372 return hva_to_pfn_atomic(vcpu->kvm, hva);
2375 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2376 struct kvm_mmu_page *sp,
2377 u64 *start, u64 *end)
2379 struct page *pages[PTE_PREFETCH_NUM];
2380 unsigned access = sp->role.access;
2384 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2385 if (!gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK))
2388 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2392 for (i = 0; i < ret; i++, gfn++, start++)
2393 mmu_set_spte(vcpu, start, ACC_ALL,
2395 sp->role.level, gfn,
2396 page_to_pfn(pages[i]), true, true);
2401 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2402 struct kvm_mmu_page *sp, u64 *sptep)
2404 u64 *spte, *start = NULL;
2407 WARN_ON(!sp->role.direct);
2409 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2412 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2413 if (is_shadow_present_pte(*spte) || spte == sptep) {
2416 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2424 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2426 struct kvm_mmu_page *sp;
2429 * Since it's no accessed bit on EPT, it's no way to
2430 * distinguish between actually accessed translations
2431 * and prefetched, so disable pte prefetch if EPT is
2434 if (!shadow_accessed_mask)
2437 sp = page_header(__pa(sptep));
2438 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2441 __direct_pte_prefetch(vcpu, sp, sptep);
2444 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2445 int map_writable, int level, gfn_t gfn, pfn_t pfn,
2448 struct kvm_shadow_walk_iterator iterator;
2449 struct kvm_mmu_page *sp;
2453 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2454 if (iterator.level == level) {
2455 unsigned pte_access = ACC_ALL;
2457 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, pte_access,
2459 level, gfn, pfn, prefault, map_writable);
2460 direct_pte_prefetch(vcpu, iterator.sptep);
2461 ++vcpu->stat.pf_fixed;
2465 if (!is_shadow_present_pte(*iterator.sptep)) {
2466 u64 base_addr = iterator.addr;
2468 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2469 pseudo_gfn = base_addr >> PAGE_SHIFT;
2470 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2472 1, ACC_ALL, iterator.sptep);
2474 pgprintk("nonpaging_map: ENOMEM\n");
2475 kvm_release_pfn_clean(pfn);
2479 mmu_spte_set(iterator.sptep,
2481 | PT_PRESENT_MASK | PT_WRITABLE_MASK
2482 | shadow_user_mask | shadow_x_mask
2483 | shadow_accessed_mask);
2489 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2493 info.si_signo = SIGBUS;
2495 info.si_code = BUS_MCEERR_AR;
2496 info.si_addr = (void __user *)address;
2497 info.si_addr_lsb = PAGE_SHIFT;
2499 send_sig_info(SIGBUS, &info, tsk);
2502 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, pfn_t pfn)
2504 kvm_release_pfn_clean(pfn);
2505 if (is_hwpoison_pfn(pfn)) {
2506 kvm_send_hwpoison_signal(gfn_to_hva(vcpu->kvm, gfn), current);
2513 static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu,
2514 gfn_t *gfnp, pfn_t *pfnp, int *levelp)
2518 int level = *levelp;
2521 * Check if it's a transparent hugepage. If this would be an
2522 * hugetlbfs page, level wouldn't be set to
2523 * PT_PAGE_TABLE_LEVEL and there would be no adjustment done
2526 if (!is_error_pfn(pfn) && !kvm_is_mmio_pfn(pfn) &&
2527 level == PT_PAGE_TABLE_LEVEL &&
2528 PageTransCompound(pfn_to_page(pfn)) &&
2529 !has_wrprotected_page(vcpu->kvm, gfn, PT_DIRECTORY_LEVEL)) {
2532 * mmu_notifier_retry was successful and we hold the
2533 * mmu_lock here, so the pmd can't become splitting
2534 * from under us, and in turn
2535 * __split_huge_page_refcount() can't run from under
2536 * us and we can safely transfer the refcount from
2537 * PG_tail to PG_head as we switch the pfn to tail to
2540 *levelp = level = PT_DIRECTORY_LEVEL;
2541 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2542 VM_BUG_ON((gfn & mask) != (pfn & mask));
2546 kvm_release_pfn_clean(pfn);
2548 if (!get_page_unless_zero(pfn_to_page(pfn)))
2555 static bool mmu_invalid_pfn(pfn_t pfn)
2557 return unlikely(is_invalid_pfn(pfn));
2560 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2561 pfn_t pfn, unsigned access, int *ret_val)
2565 /* The pfn is invalid, report the error! */
2566 if (unlikely(is_invalid_pfn(pfn))) {
2567 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2571 if (unlikely(is_noslot_pfn(pfn)))
2572 vcpu_cache_mmio_info(vcpu, gva, gfn, access);
2579 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
2580 gva_t gva, pfn_t *pfn, bool write, bool *writable);
2582 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn,
2589 unsigned long mmu_seq;
2592 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
2593 if (likely(!force_pt_level)) {
2594 level = mapping_level(vcpu, gfn);
2596 * This path builds a PAE pagetable - so we can map
2597 * 2mb pages at maximum. Therefore check if the level
2598 * is larger than that.
2600 if (level > PT_DIRECTORY_LEVEL)
2601 level = PT_DIRECTORY_LEVEL;
2603 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2605 level = PT_PAGE_TABLE_LEVEL;
2607 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2610 if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable))
2613 if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r))
2616 spin_lock(&vcpu->kvm->mmu_lock);
2617 if (mmu_notifier_retry(vcpu, mmu_seq))
2619 kvm_mmu_free_some_pages(vcpu);
2620 if (likely(!force_pt_level))
2621 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
2622 r = __direct_map(vcpu, v, write, map_writable, level, gfn, pfn,
2624 spin_unlock(&vcpu->kvm->mmu_lock);
2630 spin_unlock(&vcpu->kvm->mmu_lock);
2631 kvm_release_pfn_clean(pfn);
2636 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2639 struct kvm_mmu_page *sp;
2640 LIST_HEAD(invalid_list);
2642 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2644 spin_lock(&vcpu->kvm->mmu_lock);
2645 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL &&
2646 (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL ||
2647 vcpu->arch.mmu.direct_map)) {
2648 hpa_t root = vcpu->arch.mmu.root_hpa;
2650 sp = page_header(root);
2652 if (!sp->root_count && sp->role.invalid) {
2653 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2654 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2656 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2657 spin_unlock(&vcpu->kvm->mmu_lock);
2660 for (i = 0; i < 4; ++i) {
2661 hpa_t root = vcpu->arch.mmu.pae_root[i];
2664 root &= PT64_BASE_ADDR_MASK;
2665 sp = page_header(root);
2667 if (!sp->root_count && sp->role.invalid)
2668 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2671 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2673 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2674 spin_unlock(&vcpu->kvm->mmu_lock);
2675 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2678 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2682 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2683 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2690 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2692 struct kvm_mmu_page *sp;
2695 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2696 spin_lock(&vcpu->kvm->mmu_lock);
2697 kvm_mmu_free_some_pages(vcpu);
2698 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2701 spin_unlock(&vcpu->kvm->mmu_lock);
2702 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2703 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2704 for (i = 0; i < 4; ++i) {
2705 hpa_t root = vcpu->arch.mmu.pae_root[i];
2707 ASSERT(!VALID_PAGE(root));
2708 spin_lock(&vcpu->kvm->mmu_lock);
2709 kvm_mmu_free_some_pages(vcpu);
2710 sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT),
2712 PT32_ROOT_LEVEL, 1, ACC_ALL,
2714 root = __pa(sp->spt);
2716 spin_unlock(&vcpu->kvm->mmu_lock);
2717 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2719 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2726 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2728 struct kvm_mmu_page *sp;
2733 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2735 if (mmu_check_root(vcpu, root_gfn))
2739 * Do we shadow a long mode page table? If so we need to
2740 * write-protect the guests page table root.
2742 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2743 hpa_t root = vcpu->arch.mmu.root_hpa;
2745 ASSERT(!VALID_PAGE(root));
2747 spin_lock(&vcpu->kvm->mmu_lock);
2748 kvm_mmu_free_some_pages(vcpu);
2749 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2751 root = __pa(sp->spt);
2753 spin_unlock(&vcpu->kvm->mmu_lock);
2754 vcpu->arch.mmu.root_hpa = root;
2759 * We shadow a 32 bit page table. This may be a legacy 2-level
2760 * or a PAE 3-level page table. In either case we need to be aware that
2761 * the shadow page table may be a PAE or a long mode page table.
2763 pm_mask = PT_PRESENT_MASK;
2764 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL)
2765 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
2767 for (i = 0; i < 4; ++i) {
2768 hpa_t root = vcpu->arch.mmu.pae_root[i];
2770 ASSERT(!VALID_PAGE(root));
2771 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2772 pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i);
2773 if (!is_present_gpte(pdptr)) {
2774 vcpu->arch.mmu.pae_root[i] = 0;
2777 root_gfn = pdptr >> PAGE_SHIFT;
2778 if (mmu_check_root(vcpu, root_gfn))
2781 spin_lock(&vcpu->kvm->mmu_lock);
2782 kvm_mmu_free_some_pages(vcpu);
2783 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2786 root = __pa(sp->spt);
2788 spin_unlock(&vcpu->kvm->mmu_lock);
2790 vcpu->arch.mmu.pae_root[i] = root | pm_mask;
2792 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2795 * If we shadow a 32 bit page table with a long mode page
2796 * table we enter this path.
2798 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2799 if (vcpu->arch.mmu.lm_root == NULL) {
2801 * The additional page necessary for this is only
2802 * allocated on demand.
2807 lm_root = (void*)get_zeroed_page(GFP_KERNEL);
2808 if (lm_root == NULL)
2811 lm_root[0] = __pa(vcpu->arch.mmu.pae_root) | pm_mask;
2813 vcpu->arch.mmu.lm_root = lm_root;
2816 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.lm_root);
2822 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2824 if (vcpu->arch.mmu.direct_map)
2825 return mmu_alloc_direct_roots(vcpu);
2827 return mmu_alloc_shadow_roots(vcpu);
2830 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2833 struct kvm_mmu_page *sp;
2835 if (vcpu->arch.mmu.direct_map)
2838 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2841 vcpu_clear_mmio_info(vcpu, ~0ul);
2842 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
2843 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2844 hpa_t root = vcpu->arch.mmu.root_hpa;
2845 sp = page_header(root);
2846 mmu_sync_children(vcpu, sp);
2847 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2850 for (i = 0; i < 4; ++i) {
2851 hpa_t root = vcpu->arch.mmu.pae_root[i];
2853 if (root && VALID_PAGE(root)) {
2854 root &= PT64_BASE_ADDR_MASK;
2855 sp = page_header(root);
2856 mmu_sync_children(vcpu, sp);
2859 trace_kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
2862 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2864 spin_lock(&vcpu->kvm->mmu_lock);
2865 mmu_sync_roots(vcpu);
2866 spin_unlock(&vcpu->kvm->mmu_lock);
2869 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2870 u32 access, struct x86_exception *exception)
2873 exception->error_code = 0;
2877 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
2879 struct x86_exception *exception)
2882 exception->error_code = 0;
2883 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2886 static bool quickly_check_mmio_pf(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2889 return vcpu_match_mmio_gpa(vcpu, addr);
2891 return vcpu_match_mmio_gva(vcpu, addr);
2896 * On direct hosts, the last spte is only allows two states
2897 * for mmio page fault:
2898 * - It is the mmio spte
2899 * - It is zapped or it is being zapped.
2901 * This function completely checks the spte when the last spte
2902 * is not the mmio spte.
2904 static bool check_direct_spte_mmio_pf(u64 spte)
2906 return __check_direct_spte_mmio_pf(spte);
2909 static u64 walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr)
2911 struct kvm_shadow_walk_iterator iterator;
2914 walk_shadow_page_lockless_begin(vcpu);
2915 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte)
2916 if (!is_shadow_present_pte(spte))
2918 walk_shadow_page_lockless_end(vcpu);
2924 * If it is a real mmio page fault, return 1 and emulat the instruction
2925 * directly, return 0 to let CPU fault again on the address, -1 is
2926 * returned if bug is detected.
2928 int handle_mmio_page_fault_common(struct kvm_vcpu *vcpu, u64 addr, bool direct)
2932 if (quickly_check_mmio_pf(vcpu, addr, direct))
2935 spte = walk_shadow_page_get_mmio_spte(vcpu, addr);
2937 if (is_mmio_spte(spte)) {
2938 gfn_t gfn = get_mmio_spte_gfn(spte);
2939 unsigned access = get_mmio_spte_access(spte);
2944 trace_handle_mmio_page_fault(addr, gfn, access);
2945 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
2950 * It's ok if the gva is remapped by other cpus on shadow guest,
2951 * it's a BUG if the gfn is not a mmio page.
2953 if (direct && !check_direct_spte_mmio_pf(spte))
2957 * If the page table is zapped by other cpus, let CPU fault again on
2962 EXPORT_SYMBOL_GPL(handle_mmio_page_fault_common);
2964 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr,
2965 u32 error_code, bool direct)
2969 ret = handle_mmio_page_fault_common(vcpu, addr, direct);
2974 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2975 u32 error_code, bool prefault)
2980 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2982 if (unlikely(error_code & PFERR_RSVD_MASK))
2983 return handle_mmio_page_fault(vcpu, gva, error_code, true);
2985 r = mmu_topup_memory_caches(vcpu);
2990 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2992 gfn = gva >> PAGE_SHIFT;
2994 return nonpaging_map(vcpu, gva & PAGE_MASK,
2995 error_code & PFERR_WRITE_MASK, gfn, prefault);
2998 static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn)
3000 struct kvm_arch_async_pf arch;
3002 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3004 arch.direct_map = vcpu->arch.mmu.direct_map;
3005 arch.cr3 = vcpu->arch.mmu.get_cr3(vcpu);
3007 return kvm_setup_async_pf(vcpu, gva, gfn, &arch);
3010 static bool can_do_async_pf(struct kvm_vcpu *vcpu)
3012 if (unlikely(!irqchip_in_kernel(vcpu->kvm) ||
3013 kvm_event_needs_reinjection(vcpu)))
3016 return kvm_x86_ops->interrupt_allowed(vcpu);
3019 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3020 gva_t gva, pfn_t *pfn, bool write, bool *writable)
3024 *pfn = gfn_to_pfn_async(vcpu->kvm, gfn, &async, write, writable);
3027 return false; /* *pfn has correct page already */
3029 put_page(pfn_to_page(*pfn));
3031 if (!prefault && can_do_async_pf(vcpu)) {
3032 trace_kvm_try_async_get_page(gva, gfn);
3033 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3034 trace_kvm_async_pf_doublefault(gva, gfn);
3035 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3037 } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn))
3041 *pfn = gfn_to_pfn_prot(vcpu->kvm, gfn, write, writable);
3046 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,
3053 gfn_t gfn = gpa >> PAGE_SHIFT;
3054 unsigned long mmu_seq;
3055 int write = error_code & PFERR_WRITE_MASK;
3059 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
3061 if (unlikely(error_code & PFERR_RSVD_MASK))
3062 return handle_mmio_page_fault(vcpu, gpa, error_code, true);
3064 r = mmu_topup_memory_caches(vcpu);
3068 force_pt_level = mapping_level_dirty_bitmap(vcpu, gfn);
3069 if (likely(!force_pt_level)) {
3070 level = mapping_level(vcpu, gfn);
3071 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
3073 level = PT_PAGE_TABLE_LEVEL;
3075 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3078 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable))
3081 if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r))
3084 spin_lock(&vcpu->kvm->mmu_lock);
3085 if (mmu_notifier_retry(vcpu, mmu_seq))
3087 kvm_mmu_free_some_pages(vcpu);
3088 if (likely(!force_pt_level))
3089 transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level);
3090 r = __direct_map(vcpu, gpa, write, map_writable,
3091 level, gfn, pfn, prefault);
3092 spin_unlock(&vcpu->kvm->mmu_lock);
3097 spin_unlock(&vcpu->kvm->mmu_lock);
3098 kvm_release_pfn_clean(pfn);
3102 static void nonpaging_free(struct kvm_vcpu *vcpu)
3104 mmu_free_roots(vcpu);
3107 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
3108 struct kvm_mmu *context)
3110 context->new_cr3 = nonpaging_new_cr3;
3111 context->page_fault = nonpaging_page_fault;
3112 context->gva_to_gpa = nonpaging_gva_to_gpa;
3113 context->free = nonpaging_free;
3114 context->sync_page = nonpaging_sync_page;
3115 context->invlpg = nonpaging_invlpg;
3116 context->update_pte = nonpaging_update_pte;
3117 context->root_level = 0;
3118 context->shadow_root_level = PT32E_ROOT_LEVEL;
3119 context->root_hpa = INVALID_PAGE;
3120 context->direct_map = true;
3121 context->nx = false;
3125 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3127 ++vcpu->stat.tlb_flush;
3128 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
3131 static void paging_new_cr3(struct kvm_vcpu *vcpu)
3133 pgprintk("%s: cr3 %lx\n", __func__, kvm_read_cr3(vcpu));
3134 mmu_free_roots(vcpu);
3137 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
3139 return kvm_read_cr3(vcpu);
3142 static void inject_page_fault(struct kvm_vcpu *vcpu,
3143 struct x86_exception *fault)
3145 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
3148 static void paging_free(struct kvm_vcpu *vcpu)
3150 nonpaging_free(vcpu);
3153 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
3157 bit7 = (gpte >> 7) & 1;
3158 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
3161 static bool sync_mmio_spte(u64 *sptep, gfn_t gfn, unsigned access,
3164 if (unlikely(is_mmio_spte(*sptep))) {
3165 if (gfn != get_mmio_spte_gfn(*sptep)) {
3166 mmu_spte_clear_no_track(sptep);
3171 mark_mmio_spte(sptep, gfn, access);
3179 #include "paging_tmpl.h"
3183 #include "paging_tmpl.h"
3186 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
3187 struct kvm_mmu *context,
3190 int maxphyaddr = cpuid_maxphyaddr(vcpu);
3191 u64 exb_bit_rsvd = 0;
3194 exb_bit_rsvd = rsvd_bits(63, 63);
3196 case PT32_ROOT_LEVEL:
3197 /* no rsvd bits for 2 level 4K page table entries */
3198 context->rsvd_bits_mask[0][1] = 0;
3199 context->rsvd_bits_mask[0][0] = 0;
3200 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3202 if (!is_pse(vcpu)) {
3203 context->rsvd_bits_mask[1][1] = 0;
3207 if (is_cpuid_PSE36())
3208 /* 36bits PSE 4MB page */
3209 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
3211 /* 32 bits PSE 4MB page */
3212 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
3214 case PT32E_ROOT_LEVEL:
3215 context->rsvd_bits_mask[0][2] =
3216 rsvd_bits(maxphyaddr, 63) |
3217 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
3218 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3219 rsvd_bits(maxphyaddr, 62); /* PDE */
3220 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3221 rsvd_bits(maxphyaddr, 62); /* PTE */
3222 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3223 rsvd_bits(maxphyaddr, 62) |
3224 rsvd_bits(13, 20); /* large page */
3225 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3227 case PT64_ROOT_LEVEL:
3228 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
3229 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3230 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
3231 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
3232 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
3233 rsvd_bits(maxphyaddr, 51);
3234 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
3235 rsvd_bits(maxphyaddr, 51);
3236 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
3237 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
3238 rsvd_bits(maxphyaddr, 51) |
3240 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
3241 rsvd_bits(maxphyaddr, 51) |
3242 rsvd_bits(13, 20); /* large page */
3243 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
3248 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
3249 struct kvm_mmu *context,
3252 context->nx = is_nx(vcpu);
3254 reset_rsvds_bits_mask(vcpu, context, level);
3256 ASSERT(is_pae(vcpu));
3257 context->new_cr3 = paging_new_cr3;
3258 context->page_fault = paging64_page_fault;
3259 context->gva_to_gpa = paging64_gva_to_gpa;
3260 context->sync_page = paging64_sync_page;
3261 context->invlpg = paging64_invlpg;
3262 context->update_pte = paging64_update_pte;
3263 context->free = paging_free;
3264 context->root_level = level;
3265 context->shadow_root_level = level;
3266 context->root_hpa = INVALID_PAGE;
3267 context->direct_map = false;
3271 static int paging64_init_context(struct kvm_vcpu *vcpu,
3272 struct kvm_mmu *context)
3274 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
3277 static int paging32_init_context(struct kvm_vcpu *vcpu,
3278 struct kvm_mmu *context)
3280 context->nx = false;
3282 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3284 context->new_cr3 = paging_new_cr3;
3285 context->page_fault = paging32_page_fault;
3286 context->gva_to_gpa = paging32_gva_to_gpa;
3287 context->free = paging_free;
3288 context->sync_page = paging32_sync_page;
3289 context->invlpg = paging32_invlpg;
3290 context->update_pte = paging32_update_pte;
3291 context->root_level = PT32_ROOT_LEVEL;
3292 context->shadow_root_level = PT32E_ROOT_LEVEL;
3293 context->root_hpa = INVALID_PAGE;
3294 context->direct_map = false;
3298 static int paging32E_init_context(struct kvm_vcpu *vcpu,
3299 struct kvm_mmu *context)
3301 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
3304 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
3306 struct kvm_mmu *context = vcpu->arch.walk_mmu;
3308 context->base_role.word = 0;
3309 context->new_cr3 = nonpaging_new_cr3;
3310 context->page_fault = tdp_page_fault;
3311 context->free = nonpaging_free;
3312 context->sync_page = nonpaging_sync_page;
3313 context->invlpg = nonpaging_invlpg;
3314 context->update_pte = nonpaging_update_pte;
3315 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
3316 context->root_hpa = INVALID_PAGE;
3317 context->direct_map = true;
3318 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
3319 context->get_cr3 = get_cr3;
3320 context->inject_page_fault = kvm_inject_page_fault;
3321 context->nx = is_nx(vcpu);
3323 if (!is_paging(vcpu)) {
3324 context->nx = false;
3325 context->gva_to_gpa = nonpaging_gva_to_gpa;
3326 context->root_level = 0;
3327 } else if (is_long_mode(vcpu)) {
3328 context->nx = is_nx(vcpu);
3329 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
3330 context->gva_to_gpa = paging64_gva_to_gpa;
3331 context->root_level = PT64_ROOT_LEVEL;
3332 } else if (is_pae(vcpu)) {
3333 context->nx = is_nx(vcpu);
3334 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
3335 context->gva_to_gpa = paging64_gva_to_gpa;
3336 context->root_level = PT32E_ROOT_LEVEL;
3338 context->nx = false;
3339 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
3340 context->gva_to_gpa = paging32_gva_to_gpa;
3341 context->root_level = PT32_ROOT_LEVEL;
3347 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
3350 bool smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
3352 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3354 if (!is_paging(vcpu))
3355 r = nonpaging_init_context(vcpu, context);
3356 else if (is_long_mode(vcpu))
3357 r = paging64_init_context(vcpu, context);
3358 else if (is_pae(vcpu))
3359 r = paging32E_init_context(vcpu, context);
3361 r = paging32_init_context(vcpu, context);
3363 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
3364 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
3365 vcpu->arch.mmu.base_role.smep_andnot_wp
3366 = smep && !is_write_protection(vcpu);
3370 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
3372 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
3374 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
3376 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
3377 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
3378 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
3383 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
3385 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
3387 g_context->get_cr3 = get_cr3;
3388 g_context->inject_page_fault = kvm_inject_page_fault;
3391 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
3392 * translation of l2_gpa to l1_gpa addresses is done using the
3393 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
3394 * functions between mmu and nested_mmu are swapped.
3396 if (!is_paging(vcpu)) {
3397 g_context->nx = false;
3398 g_context->root_level = 0;
3399 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
3400 } else if (is_long_mode(vcpu)) {
3401 g_context->nx = is_nx(vcpu);
3402 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
3403 g_context->root_level = PT64_ROOT_LEVEL;
3404 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3405 } else if (is_pae(vcpu)) {
3406 g_context->nx = is_nx(vcpu);
3407 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
3408 g_context->root_level = PT32E_ROOT_LEVEL;
3409 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
3411 g_context->nx = false;
3412 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
3413 g_context->root_level = PT32_ROOT_LEVEL;
3414 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
3420 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
3422 if (mmu_is_nested(vcpu))
3423 return init_kvm_nested_mmu(vcpu);
3424 else if (tdp_enabled)
3425 return init_kvm_tdp_mmu(vcpu);
3427 return init_kvm_softmmu(vcpu);
3430 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
3433 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
3434 /* mmu.free() should set root_hpa = INVALID_PAGE */
3435 vcpu->arch.mmu.free(vcpu);
3438 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
3440 destroy_kvm_mmu(vcpu);
3441 return init_kvm_mmu(vcpu);
3443 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
3445 int kvm_mmu_load(struct kvm_vcpu *vcpu)
3449 r = mmu_topup_memory_caches(vcpu);
3452 r = mmu_alloc_roots(vcpu);
3453 spin_lock(&vcpu->kvm->mmu_lock);
3454 mmu_sync_roots(vcpu);
3455 spin_unlock(&vcpu->kvm->mmu_lock);
3458 /* set_cr3() should ensure TLB has been flushed */
3459 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
3463 EXPORT_SYMBOL_GPL(kvm_mmu_load);
3465 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
3467 mmu_free_roots(vcpu);
3469 EXPORT_SYMBOL_GPL(kvm_mmu_unload);
3471 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
3472 struct kvm_mmu_page *sp, u64 *spte,
3475 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
3476 ++vcpu->kvm->stat.mmu_pde_zapped;
3480 ++vcpu->kvm->stat.mmu_pte_updated;
3481 vcpu->arch.mmu.update_pte(vcpu, sp, spte, new);
3484 static bool need_remote_flush(u64 old, u64 new)
3486 if (!is_shadow_present_pte(old))
3488 if (!is_shadow_present_pte(new))
3490 if ((old ^ new) & PT64_BASE_ADDR_MASK)
3492 old ^= PT64_NX_MASK;
3493 new ^= PT64_NX_MASK;
3494 return (old & ~new & PT64_PERM_MASK) != 0;
3497 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
3498 bool remote_flush, bool local_flush)
3504 kvm_flush_remote_tlbs(vcpu->kvm);
3505 else if (local_flush)
3506 kvm_mmu_flush_tlb(vcpu);
3509 static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
3511 u64 *spte = vcpu->arch.last_pte_updated;
3513 return !!(spte && (*spte & shadow_accessed_mask));
3516 static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
3518 u64 *spte = vcpu->arch.last_pte_updated;
3521 && vcpu->arch.last_pte_gfn == gfn
3522 && shadow_accessed_mask
3523 && !(*spte & shadow_accessed_mask)
3524 && is_shadow_present_pte(*spte))
3525 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
3528 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3529 const u8 *new, int bytes,
3530 bool guest_initiated)
3532 gfn_t gfn = gpa >> PAGE_SHIFT;
3533 union kvm_mmu_page_role mask = { .word = 0 };
3534 struct kvm_mmu_page *sp;
3535 struct hlist_node *node;
3536 LIST_HEAD(invalid_list);
3537 u64 entry, gentry, *spte;
3538 unsigned pte_size, page_offset, misaligned, quadrant, offset;
3539 int level, npte, invlpg_counter, r, flooded = 0;
3540 bool remote_flush, local_flush, zap_page;
3543 * If we don't have indirect shadow pages, it means no page is
3544 * write-protected, so we can exit simply.
3546 if (!ACCESS_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
3549 zap_page = remote_flush = local_flush = false;
3550 offset = offset_in_page(gpa);
3552 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3554 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
3557 * Assume that the pte write on a page table of the same type
3558 * as the current vcpu paging mode since we update the sptes only
3559 * when they have the same mode.
3561 if ((is_pae(vcpu) && bytes == 4) || !new) {
3562 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3567 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
3570 new = (const u8 *)&gentry;
3575 gentry = *(const u32 *)new;
3578 gentry = *(const u64 *)new;
3585 spin_lock(&vcpu->kvm->mmu_lock);
3586 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
3588 kvm_mmu_free_some_pages(vcpu);
3589 ++vcpu->kvm->stat.mmu_pte_write;
3590 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3591 if (guest_initiated) {
3592 kvm_mmu_access_page(vcpu, gfn);
3593 if (gfn == vcpu->arch.last_pt_write_gfn
3594 && !last_updated_pte_accessed(vcpu)) {
3595 ++vcpu->arch.last_pt_write_count;
3596 if (vcpu->arch.last_pt_write_count >= 3)
3599 vcpu->arch.last_pt_write_gfn = gfn;
3600 vcpu->arch.last_pt_write_count = 1;
3601 vcpu->arch.last_pte_updated = NULL;
3605 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3606 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3607 pte_size = sp->role.cr4_pae ? 8 : 4;
3608 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3609 misaligned |= bytes < 4;
3610 if (misaligned || flooded) {
3612 * Misaligned accesses are too much trouble to fix
3613 * up; also, they usually indicate a page is not used
3616 * If we're seeing too many writes to a page,
3617 * it may no longer be a page table, or we may be
3618 * forking, in which case it is better to unmap the
3621 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3622 gpa, bytes, sp->role.word);
3623 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3625 ++vcpu->kvm->stat.mmu_flooded;
3628 page_offset = offset;
3629 level = sp->role.level;
3631 if (!sp->role.cr4_pae) {
3632 page_offset <<= 1; /* 32->64 */
3634 * A 32-bit pde maps 4MB while the shadow pdes map
3635 * only 2MB. So we need to double the offset again
3636 * and zap two pdes instead of one.
3638 if (level == PT32_ROOT_LEVEL) {
3639 page_offset &= ~7; /* kill rounding error */
3643 quadrant = page_offset >> PAGE_SHIFT;
3644 page_offset &= ~PAGE_MASK;
3645 if (quadrant != sp->role.quadrant)
3649 spte = &sp->spt[page_offset / sizeof(*spte)];
3652 mmu_page_zap_pte(vcpu->kvm, sp, spte);
3654 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3656 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3657 if (!remote_flush && need_remote_flush(entry, *spte))
3658 remote_flush = true;
3662 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3663 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3664 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3665 spin_unlock(&vcpu->kvm->mmu_lock);
3668 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3673 if (vcpu->arch.mmu.direct_map)
3676 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3678 spin_lock(&vcpu->kvm->mmu_lock);
3679 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3680 spin_unlock(&vcpu->kvm->mmu_lock);
3683 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3685 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3687 LIST_HEAD(invalid_list);
3689 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3690 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3691 struct kvm_mmu_page *sp;
3693 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3694 struct kvm_mmu_page, link);
3695 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3696 ++vcpu->kvm->stat.mmu_recycled;
3698 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3701 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code,
3702 void *insn, int insn_len)
3705 enum emulation_result er;
3707 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code, false);
3716 r = mmu_topup_memory_caches(vcpu);
3720 er = x86_emulate_instruction(vcpu, cr2, 0, insn, insn_len);
3725 case EMULATE_DO_MMIO:
3726 ++vcpu->stat.mmio_exits;
3736 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3738 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3740 vcpu->arch.mmu.invlpg(vcpu, gva);
3741 kvm_mmu_flush_tlb(vcpu);
3742 ++vcpu->stat.invlpg;
3744 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3746 void kvm_enable_tdp(void)
3750 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3752 void kvm_disable_tdp(void)
3754 tdp_enabled = false;
3756 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3758 static void free_mmu_pages(struct kvm_vcpu *vcpu)
3760 free_page((unsigned long)vcpu->arch.mmu.pae_root);
3761 if (vcpu->arch.mmu.lm_root != NULL)
3762 free_page((unsigned long)vcpu->arch.mmu.lm_root);
3765 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3773 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3774 * Therefore we need to allocate shadow page tables in the first
3775 * 4GB of memory, which happens to fit the DMA32 zone.
3777 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3781 vcpu->arch.mmu.pae_root = page_address(page);
3782 for (i = 0; i < 4; ++i)
3783 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3788 int kvm_mmu_create(struct kvm_vcpu *vcpu)
3791 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3793 return alloc_mmu_pages(vcpu);
3796 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3799 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3801 return init_kvm_mmu(vcpu);
3804 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
3806 struct kvm_mmu_page *sp;
3808 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
3812 if (!test_bit(slot, sp->slot_bitmap))
3816 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3817 if (!is_shadow_present_pte(pt[i]) ||
3818 !is_last_spte(pt[i], sp->role.level))
3821 if (is_large_pte(pt[i])) {
3822 drop_spte(kvm, &pt[i]);
3828 if (is_writable_pte(pt[i]))
3829 mmu_spte_update(&pt[i],
3830 pt[i] & ~PT_WRITABLE_MASK);
3833 kvm_flush_remote_tlbs(kvm);
3836 void kvm_mmu_zap_all(struct kvm *kvm)
3838 struct kvm_mmu_page *sp, *node;
3839 LIST_HEAD(invalid_list);
3841 spin_lock(&kvm->mmu_lock);
3843 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
3844 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3847 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3848 spin_unlock(&kvm->mmu_lock);
3851 static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3852 struct list_head *invalid_list)
3854 struct kvm_mmu_page *page;
3856 page = container_of(kvm->arch.active_mmu_pages.prev,
3857 struct kvm_mmu_page, link);
3858 return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3861 static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
3864 struct kvm *kvm_freed = NULL;
3865 int nr_to_scan = sc->nr_to_scan;
3867 if (nr_to_scan == 0)
3870 raw_spin_lock(&kvm_lock);
3872 list_for_each_entry(kvm, &vm_list, vm_list) {
3873 int idx, freed_pages;
3874 LIST_HEAD(invalid_list);
3876 idx = srcu_read_lock(&kvm->srcu);
3877 spin_lock(&kvm->mmu_lock);
3878 if (!kvm_freed && nr_to_scan > 0 &&
3879 kvm->arch.n_used_mmu_pages > 0) {
3880 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3886 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3887 spin_unlock(&kvm->mmu_lock);
3888 srcu_read_unlock(&kvm->srcu, idx);
3891 list_move_tail(&kvm_freed->vm_list, &vm_list);
3893 raw_spin_unlock(&kvm_lock);
3896 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3899 static struct shrinker mmu_shrinker = {
3900 .shrink = mmu_shrink,
3901 .seeks = DEFAULT_SEEKS * 10,
3904 static void mmu_destroy_caches(void)
3906 if (pte_list_desc_cache)
3907 kmem_cache_destroy(pte_list_desc_cache);
3908 if (mmu_page_header_cache)
3909 kmem_cache_destroy(mmu_page_header_cache);
3912 int kvm_mmu_module_init(void)
3914 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
3915 sizeof(struct pte_list_desc),
3917 if (!pte_list_desc_cache)
3920 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3921 sizeof(struct kvm_mmu_page),
3923 if (!mmu_page_header_cache)
3926 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
3929 register_shrinker(&mmu_shrinker);
3934 mmu_destroy_caches();
3939 * Caculate mmu pages needed for kvm.
3941 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3944 unsigned int nr_mmu_pages;
3945 unsigned int nr_pages = 0;
3946 struct kvm_memslots *slots;
3948 slots = kvm_memslots(kvm);
3950 for (i = 0; i < slots->nmemslots; i++)
3951 nr_pages += slots->memslots[i].npages;
3953 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3954 nr_mmu_pages = max(nr_mmu_pages,
3955 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3957 return nr_mmu_pages;
3960 static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3963 if (len > buffer->len)
3968 static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3973 ret = pv_mmu_peek_buffer(buffer, len);
3978 buffer->processed += len;
3982 static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3983 gpa_t addr, gpa_t value)
3988 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3991 r = mmu_topup_memory_caches(vcpu);
3995 if (!emulator_write_phys(vcpu, addr, &value, bytes))
4001 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
4003 (void)kvm_set_cr3(vcpu, kvm_read_cr3(vcpu));
4007 static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
4009 spin_lock(&vcpu->kvm->mmu_lock);
4010 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
4011 spin_unlock(&vcpu->kvm->mmu_lock);
4015 static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
4016 struct kvm_pv_mmu_op_buffer *buffer)
4018 struct kvm_mmu_op_header *header;
4020 header = pv_mmu_peek_buffer(buffer, sizeof *header);
4023 switch (header->op) {
4024 case KVM_MMU_OP_WRITE_PTE: {
4025 struct kvm_mmu_op_write_pte *wpte;
4027 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
4030 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
4033 case KVM_MMU_OP_FLUSH_TLB: {
4034 struct kvm_mmu_op_flush_tlb *ftlb;
4036 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
4039 return kvm_pv_mmu_flush_tlb(vcpu);
4041 case KVM_MMU_OP_RELEASE_PT: {
4042 struct kvm_mmu_op_release_pt *rpt;
4044 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
4047 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
4053 int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
4054 gpa_t addr, unsigned long *ret)
4057 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
4059 buffer->ptr = buffer->buf;
4060 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
4061 buffer->processed = 0;
4063 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
4067 while (buffer->len) {
4068 r = kvm_pv_mmu_op_one(vcpu, buffer);
4077 *ret = buffer->processed;
4081 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
4083 struct kvm_shadow_walk_iterator iterator;
4087 walk_shadow_page_lockless_begin(vcpu);
4088 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
4089 sptes[iterator.level-1] = spte;
4091 if (!is_shadow_present_pte(spte))
4094 walk_shadow_page_lockless_end(vcpu);
4098 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
4100 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
4104 destroy_kvm_mmu(vcpu);
4105 free_mmu_pages(vcpu);
4106 mmu_free_memory_caches(vcpu);
4109 #ifdef CONFIG_KVM_MMU_AUDIT
4110 #include "mmu_audit.c"
4112 static void mmu_audit_disable(void) { }
4115 void kvm_mmu_module_exit(void)
4117 mmu_destroy_caches();
4118 percpu_counter_destroy(&kvm_total_used_mmu_pages);
4119 unregister_shrinker(&mmu_shrinker);
4120 mmu_audit_disable();