3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
38 #ifndef _LANGUAGE_ASSEMBLY
40 #include <linux/delay.h>
41 #include <linux/types.h>
44 #include <linux/irq.h>
46 /* cpu pipeline flush */
47 void static inline au_sync(void)
49 __asm__ volatile ("sync");
52 void static inline au_sync_udelay(int us)
54 __asm__ volatile ("sync");
58 void static inline au_sync_delay(int ms)
60 __asm__ volatile ("sync");
64 void static inline au_writeb(u8 val, unsigned long reg)
66 *(volatile u8 *)reg = val;
69 void static inline au_writew(u16 val, unsigned long reg)
71 *(volatile u16 *)reg = val;
74 void static inline au_writel(u32 val, unsigned long reg)
76 *(volatile u32 *)reg = val;
79 static inline u8 au_readb(unsigned long reg)
81 return *(volatile u8 *)reg;
84 static inline u16 au_readw(unsigned long reg)
86 return *(volatile u16 *)reg;
89 static inline u32 au_readl(unsigned long reg)
91 return *(volatile u32 *)reg;
94 /* Early Au1000 have a write-only SYS_CPUPLL register. */
95 static inline int au1xxx_cpu_has_pll_wo(void)
97 switch (read_c0_prid()) {
98 case 0x00030100: /* Au1000 DA */
99 case 0x00030201: /* Au1000 HA */
100 case 0x00030202: /* Au1000 HB */
106 /* does CPU need CONFIG[OD] set to fix tons of errata? */
107 static inline int au1xxx_cpu_needs_config_od(void)
110 * c0_config.od (bit 19) was write only (and read as 0) on the
111 * early revisions of Alchemy SOCs. It disables the bus trans-
112 * action overlapping and needs to be set to fix various errata.
114 switch (read_c0_prid()) {
115 case 0x00030100: /* Au1000 DA */
116 case 0x00030201: /* Au1000 HA */
117 case 0x00030202: /* Au1000 HB */
118 case 0x01030200: /* Au1500 AB */
120 * Au1100/Au1200 errata actually keep silence about this bit,
121 * so we set it just in case for those revisions that require
122 * it to be set according to the (now gone) cpu_table.
124 case 0x02030200: /* Au1100 AB */
125 case 0x02030201: /* Au1100 BA */
126 case 0x02030202: /* Au1100 BC */
127 case 0x04030201: /* Au1200 AC */
133 #define ALCHEMY_CPU_UNKNOWN -1
134 #define ALCHEMY_CPU_AU1000 0
135 #define ALCHEMY_CPU_AU1500 1
136 #define ALCHEMY_CPU_AU1100 2
137 #define ALCHEMY_CPU_AU1550 3
138 #define ALCHEMY_CPU_AU1200 4
140 static inline int alchemy_get_cputype(void)
142 switch (read_c0_prid() & 0xffff0000) {
144 return ALCHEMY_CPU_AU1000;
147 return ALCHEMY_CPU_AU1500;
150 return ALCHEMY_CPU_AU1100;
153 return ALCHEMY_CPU_AU1550;
157 return ALCHEMY_CPU_AU1200;
161 return ALCHEMY_CPU_UNKNOWN;
164 /* return number of uarts on a given cputype */
165 static inline int alchemy_get_uarts(int type)
168 case ALCHEMY_CPU_AU1000:
170 case ALCHEMY_CPU_AU1500:
171 case ALCHEMY_CPU_AU1200:
173 case ALCHEMY_CPU_AU1100:
174 case ALCHEMY_CPU_AU1550:
180 /* enable an UART block if it isn't already */
181 static inline void alchemy_uart_enable(u32 uart_phys)
183 void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
185 /* reset, enable clock, deassert reset */
186 if ((__raw_readl(addr + 0x100) & 3) != 3) {
187 __raw_writel(0, addr + 0x100);
189 __raw_writel(1, addr + 0x100);
192 __raw_writel(3, addr + 0x100);
196 static inline void alchemy_uart_disable(u32 uart_phys)
198 void __iomem *addr = (void __iomem *)KSEG1ADDR(uart_phys);
199 __raw_writel(0, addr + 0x100); /* UART_MOD_CNTRL */
203 static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
205 void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
208 /* check LSR TX_EMPTY bit */
211 if (__raw_readl(base + 0x1c) & 0x20)
214 for (i = 10000; i; i--)
215 asm volatile ("nop");
218 __raw_writel(c, base + 0x04); /* tx */
222 /* arch/mips/au1000/common/clocks.c */
223 extern void set_au1x00_speed(unsigned int new_freq);
224 extern unsigned int get_au1x00_speed(void);
225 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
226 extern unsigned long get_au1x00_uart_baud_base(void);
227 extern unsigned long au1xxx_calc_clock(void);
229 /* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
230 void alchemy_sleep_au1000(void);
231 void alchemy_sleep_au1550(void);
235 /* SOC Interrupt numbers */
237 #define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 8)
238 #define AU1000_INTC0_INT_LAST (AU1000_INTC0_INT_BASE + 31)
239 #define AU1000_INTC1_INT_BASE (AU1000_INTC0_INT_LAST + 1)
240 #define AU1000_INTC1_INT_LAST (AU1000_INTC1_INT_BASE + 31)
241 #define AU1000_MAX_INTR AU1000_INTC1_INT_LAST
243 enum soc_au1000_ints {
244 AU1000_FIRST_INT = AU1000_INTC0_INT_BASE,
245 AU1000_UART0_INT = AU1000_FIRST_INT,
253 AU1000_TOY_INT = AU1000_FIRST_INT + 14,
254 AU1000_TOY_MATCH0_INT,
255 AU1000_TOY_MATCH1_INT,
256 AU1000_TOY_MATCH2_INT,
258 AU1000_RTC_MATCH0_INT,
259 AU1000_RTC_MATCH1_INT,
260 AU1000_RTC_MATCH2_INT,
263 AU1000_USB_DEV_REQ_INT,
264 AU1000_USB_DEV_SUS_INT,
305 enum soc_au1100_ints {
306 AU1100_FIRST_INT = AU1000_INTC0_INT_BASE,
307 AU1100_UART0_INT = AU1100_FIRST_INT,
315 AU1100_TOY_INT = AU1100_FIRST_INT + 14,
316 AU1100_TOY_MATCH0_INT,
317 AU1100_TOY_MATCH1_INT,
318 AU1100_TOY_MATCH2_INT,
320 AU1100_RTC_MATCH0_INT,
321 AU1100_RTC_MATCH1_INT,
322 AU1100_RTC_MATCH2_INT,
325 AU1100_USB_DEV_REQ_INT,
326 AU1100_USB_DEV_SUS_INT,
330 AU1100_GPIO208_215_INT,
367 enum soc_au1500_ints {
368 AU1500_FIRST_INT = AU1000_INTC0_INT_BASE,
369 AU1500_UART0_INT = AU1500_FIRST_INT,
377 AU1500_TOY_INT = AU1500_FIRST_INT + 14,
378 AU1500_TOY_MATCH0_INT,
379 AU1500_TOY_MATCH1_INT,
380 AU1500_TOY_MATCH2_INT,
382 AU1500_RTC_MATCH0_INT,
383 AU1500_RTC_MATCH1_INT,
384 AU1500_RTC_MATCH2_INT,
387 AU1500_USB_DEV_REQ_INT,
388 AU1500_USB_DEV_SUS_INT,
393 AU1500_AC97C_INT = AU1500_FIRST_INT + 31,
425 AU1500_GPIO208_215_INT,
428 enum soc_au1550_ints {
429 AU1550_FIRST_INT = AU1000_INTC0_INT_BASE,
430 AU1550_UART0_INT = AU1550_FIRST_INT,
445 AU1550_TOY_MATCH0_INT,
446 AU1550_TOY_MATCH1_INT,
447 AU1550_TOY_MATCH2_INT,
449 AU1550_RTC_MATCH0_INT,
450 AU1550_RTC_MATCH1_INT,
451 AU1550_RTC_MATCH2_INT,
453 AU1550_NAND_INT = AU1550_FIRST_INT + 23,
454 AU1550_USB_DEV_REQ_INT,
455 AU1550_USB_DEV_SUS_INT,
459 AU1550_GPIO0_INT = AU1550_FIRST_INT + 32,
476 AU1550_GPIO201_205_INT, /* Logical or of GPIO201:205 */
490 AU1550_GPIO208_215_INT, /* Logical or of GPIO208:215 */
493 enum soc_au1200_ints {
494 AU1200_FIRST_INT = AU1000_INTC0_INT_BASE,
495 AU1200_UART0_INT = AU1200_FIRST_INT,
510 AU1200_TOY_MATCH0_INT,
511 AU1200_TOY_MATCH1_INT,
512 AU1200_TOY_MATCH2_INT,
514 AU1200_RTC_MATCH0_INT,
515 AU1200_RTC_MATCH1_INT,
516 AU1200_RTC_MATCH2_INT,
523 AU1200_GPIO208_215_INT, /* Logical OR of 208:215 */
561 #endif /* !defined (_LANGUAGE_ASSEMBLY) */
564 * SDRAM register offsets
566 #if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
567 defined(CONFIG_SOC_AU1100)
568 #define MEM_SDMODE0 0x0000
569 #define MEM_SDMODE1 0x0004
570 #define MEM_SDMODE2 0x0008
571 #define MEM_SDADDR0 0x000C
572 #define MEM_SDADDR1 0x0010
573 #define MEM_SDADDR2 0x0014
574 #define MEM_SDREFCFG 0x0018
575 #define MEM_SDPRECMD 0x001C
576 #define MEM_SDAUTOREF 0x0020
577 #define MEM_SDWRMD0 0x0024
578 #define MEM_SDWRMD1 0x0028
579 #define MEM_SDWRMD2 0x002C
580 #define MEM_SDSLEEP 0x0030
581 #define MEM_SDSMCKE 0x0034
584 * MEM_SDMODE register content definitions
586 #define MEM_SDMODE_F (1 << 22)
587 #define MEM_SDMODE_SR (1 << 21)
588 #define MEM_SDMODE_BS (1 << 20)
589 #define MEM_SDMODE_RS (3 << 18)
590 #define MEM_SDMODE_CS (7 << 15)
591 #define MEM_SDMODE_TRAS (15 << 11)
592 #define MEM_SDMODE_TMRD (3 << 9)
593 #define MEM_SDMODE_TWR (3 << 7)
594 #define MEM_SDMODE_TRP (3 << 5)
595 #define MEM_SDMODE_TRCD (3 << 3)
596 #define MEM_SDMODE_TCL (7 << 0)
598 #define MEM_SDMODE_BS_2Bank (0 << 20)
599 #define MEM_SDMODE_BS_4Bank (1 << 20)
600 #define MEM_SDMODE_RS_11Row (0 << 18)
601 #define MEM_SDMODE_RS_12Row (1 << 18)
602 #define MEM_SDMODE_RS_13Row (2 << 18)
603 #define MEM_SDMODE_RS_N(N) ((N) << 18)
604 #define MEM_SDMODE_CS_7Col (0 << 15)
605 #define MEM_SDMODE_CS_8Col (1 << 15)
606 #define MEM_SDMODE_CS_9Col (2 << 15)
607 #define MEM_SDMODE_CS_10Col (3 << 15)
608 #define MEM_SDMODE_CS_11Col (4 << 15)
609 #define MEM_SDMODE_CS_N(N) ((N) << 15)
610 #define MEM_SDMODE_TRAS_N(N) ((N) << 11)
611 #define MEM_SDMODE_TMRD_N(N) ((N) << 9)
612 #define MEM_SDMODE_TWR_N(N) ((N) << 7)
613 #define MEM_SDMODE_TRP_N(N) ((N) << 5)
614 #define MEM_SDMODE_TRCD_N(N) ((N) << 3)
615 #define MEM_SDMODE_TCL_N(N) ((N) << 0)
618 * MEM_SDADDR register contents definitions
620 #define MEM_SDADDR_E (1 << 20)
621 #define MEM_SDADDR_CSBA (0x03FF << 10)
622 #define MEM_SDADDR_CSMASK (0x03FF << 0)
623 #define MEM_SDADDR_CSBA_N(N) ((N) & (0x03FF << 22) >> 12)
624 #define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF << 22) >> 22)
627 * MEM_SDREFCFG register content definitions
629 #define MEM_SDREFCFG_TRC (15 << 28)
630 #define MEM_SDREFCFG_TRPM (3 << 26)
631 #define MEM_SDREFCFG_E (1 << 25)
632 #define MEM_SDREFCFG_RE (0x1ffffff << 0)
633 #define MEM_SDREFCFG_TRC_N(N) ((N) << MEM_SDREFCFG_TRC)
634 #define MEM_SDREFCFG_TRPM_N(N) ((N) << MEM_SDREFCFG_TRPM)
635 #define MEM_SDREFCFG_REF_N(N) (N)
638 /***********************************************************************/
641 * Au1550 SDRAM Register Offsets
644 /***********************************************************************/
646 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
647 #define MEM_SDMODE0 0x0800
648 #define MEM_SDMODE1 0x0808
649 #define MEM_SDMODE2 0x0810
650 #define MEM_SDADDR0 0x0820
651 #define MEM_SDADDR1 0x0828
652 #define MEM_SDADDR2 0x0830
653 #define MEM_SDCONFIGA 0x0840
654 #define MEM_SDCONFIGB 0x0848
655 #define MEM_SDSTAT 0x0850
656 #define MEM_SDERRADDR 0x0858
657 #define MEM_SDSTRIDE0 0x0860
658 #define MEM_SDSTRIDE1 0x0868
659 #define MEM_SDSTRIDE2 0x0870
660 #define MEM_SDWRMD0 0x0880
661 #define MEM_SDWRMD1 0x0888
662 #define MEM_SDWRMD2 0x0890
663 #define MEM_SDPRECMD 0x08C0
664 #define MEM_SDAUTOREF 0x08C8
665 #define MEM_SDSREF 0x08D0
666 #define MEM_SDSLEEP MEM_SDSREF
671 * Physical base addresses for integrated peripherals
672 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200
675 #define AU1000_IC0_PHYS_ADDR 0x10400000 /* 01234 */
676 #define AU1000_UART0_PHYS_ADDR 0x11100000 /* 01234 */
677 #define AU1000_UART1_PHYS_ADDR 0x11200000 /* 0234 */
678 #define AU1000_UART2_PHYS_ADDR 0x11300000 /* 0 */
679 #define AU1000_UART3_PHYS_ADDR 0x11400000 /* 0123 */
680 #define AU1000_IC1_PHYS_ADDR 0x11800000 /* 01234 */
681 #define AU1550_DBDMA_PHYS_ADDR 0x14002000 /* 34 */
682 #define AU1550_DBDMA_CONF_PHYS_ADDR 0x14003000 /* 34 */
685 #ifdef CONFIG_SOC_AU1000
686 #define MEM_PHYS_ADDR 0x14000000
687 #define STATIC_MEM_PHYS_ADDR 0x14001000
688 #define DMA0_PHYS_ADDR 0x14002000
689 #define DMA1_PHYS_ADDR 0x14002100
690 #define DMA2_PHYS_ADDR 0x14002200
691 #define DMA3_PHYS_ADDR 0x14002300
692 #define DMA4_PHYS_ADDR 0x14002400
693 #define DMA5_PHYS_ADDR 0x14002500
694 #define DMA6_PHYS_ADDR 0x14002600
695 #define DMA7_PHYS_ADDR 0x14002700
696 #define AC97_PHYS_ADDR 0x10000000
697 #define USBH_PHYS_ADDR 0x10100000
698 #define USBD_PHYS_ADDR 0x10200000
699 #define IRDA_PHYS_ADDR 0x10300000
700 #define MAC0_PHYS_ADDR 0x10500000
701 #define MAC1_PHYS_ADDR 0x10510000
702 #define MACEN_PHYS_ADDR 0x10520000
703 #define MACDMA0_PHYS_ADDR 0x14004000
704 #define MACDMA1_PHYS_ADDR 0x14004200
705 #define I2S_PHYS_ADDR 0x11000000
706 #define SSI0_PHYS_ADDR 0x11600000
707 #define SSI1_PHYS_ADDR 0x11680000
708 #define SYS_PHYS_ADDR 0x11900000
709 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
710 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
711 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
714 /********************************************************************/
716 #ifdef CONFIG_SOC_AU1500
717 #define MEM_PHYS_ADDR 0x14000000
718 #define STATIC_MEM_PHYS_ADDR 0x14001000
719 #define DMA0_PHYS_ADDR 0x14002000
720 #define DMA1_PHYS_ADDR 0x14002100
721 #define DMA2_PHYS_ADDR 0x14002200
722 #define DMA3_PHYS_ADDR 0x14002300
723 #define DMA4_PHYS_ADDR 0x14002400
724 #define DMA5_PHYS_ADDR 0x14002500
725 #define DMA6_PHYS_ADDR 0x14002600
726 #define DMA7_PHYS_ADDR 0x14002700
727 #define AC97_PHYS_ADDR 0x10000000
728 #define USBH_PHYS_ADDR 0x10100000
729 #define USBD_PHYS_ADDR 0x10200000
730 #define PCI_PHYS_ADDR 0x14005000
731 #define MAC0_PHYS_ADDR 0x11500000
732 #define MAC1_PHYS_ADDR 0x11510000
733 #define MACEN_PHYS_ADDR 0x11520000
734 #define MACDMA0_PHYS_ADDR 0x14004000
735 #define MACDMA1_PHYS_ADDR 0x14004200
736 #define I2S_PHYS_ADDR 0x11000000
737 #define GPIO2_PHYS_ADDR 0x11700000
738 #define SYS_PHYS_ADDR 0x11900000
739 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
740 #define PCI_IO_PHYS_ADDR 0x500000000ULL
741 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
742 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
743 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
744 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
745 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
748 /********************************************************************/
750 #ifdef CONFIG_SOC_AU1100
751 #define MEM_PHYS_ADDR 0x14000000
752 #define STATIC_MEM_PHYS_ADDR 0x14001000
753 #define DMA0_PHYS_ADDR 0x14002000
754 #define DMA1_PHYS_ADDR 0x14002100
755 #define DMA2_PHYS_ADDR 0x14002200
756 #define DMA3_PHYS_ADDR 0x14002300
757 #define DMA4_PHYS_ADDR 0x14002400
758 #define DMA5_PHYS_ADDR 0x14002500
759 #define DMA6_PHYS_ADDR 0x14002600
760 #define DMA7_PHYS_ADDR 0x14002700
761 #define SD0_PHYS_ADDR 0x10600000
762 #define SD1_PHYS_ADDR 0x10680000
763 #define AC97_PHYS_ADDR 0x10000000
764 #define USBH_PHYS_ADDR 0x10100000
765 #define USBD_PHYS_ADDR 0x10200000
766 #define IRDA_PHYS_ADDR 0x10300000
767 #define MAC0_PHYS_ADDR 0x10500000
768 #define MACEN_PHYS_ADDR 0x10520000
769 #define MACDMA0_PHYS_ADDR 0x14004000
770 #define MACDMA1_PHYS_ADDR 0x14004200
771 #define I2S_PHYS_ADDR 0x11000000
772 #define SSI0_PHYS_ADDR 0x11600000
773 #define SSI1_PHYS_ADDR 0x11680000
774 #define GPIO2_PHYS_ADDR 0x11700000
775 #define SYS_PHYS_ADDR 0x11900000
776 #define LCD_PHYS_ADDR 0x15000000
777 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
778 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
779 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
782 /***********************************************************************/
784 #ifdef CONFIG_SOC_AU1550
785 #define MEM_PHYS_ADDR 0x14000000
786 #define STATIC_MEM_PHYS_ADDR 0x14001000
787 #define USBH_PHYS_ADDR 0x14020000
788 #define USBD_PHYS_ADDR 0x10200000
789 #define PCI_PHYS_ADDR 0x14005000
790 #define MAC0_PHYS_ADDR 0x10500000
791 #define MAC1_PHYS_ADDR 0x10510000
792 #define MACEN_PHYS_ADDR 0x10520000
793 #define MACDMA0_PHYS_ADDR 0x14004000
794 #define MACDMA1_PHYS_ADDR 0x14004200
795 #define GPIO2_PHYS_ADDR 0x11700000
796 #define SYS_PHYS_ADDR 0x11900000
797 #define PE_PHYS_ADDR 0x14008000
798 #define PSC0_PHYS_ADDR 0x11A00000
799 #define PSC1_PHYS_ADDR 0x11B00000
800 #define PSC2_PHYS_ADDR 0x10A00000
801 #define PSC3_PHYS_ADDR 0x10B00000
802 #define PCI_MEM_PHYS_ADDR 0x400000000ULL
803 #define PCI_IO_PHYS_ADDR 0x500000000ULL
804 #define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
805 #define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
806 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
807 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
808 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
811 /***********************************************************************/
813 #ifdef CONFIG_SOC_AU1200
814 #define MEM_PHYS_ADDR 0x14000000
815 #define STATIC_MEM_PHYS_ADDR 0x14001000
816 #define AES_PHYS_ADDR 0x10300000
817 #define CIM_PHYS_ADDR 0x14004000
818 #define USBM_PHYS_ADDR 0x14020000
819 #define USBH_PHYS_ADDR 0x14020100
820 #define GPIO2_PHYS_ADDR 0x11700000
821 #define SYS_PHYS_ADDR 0x11900000
822 #define PSC0_PHYS_ADDR 0x11A00000
823 #define PSC1_PHYS_ADDR 0x11B00000
824 #define SD0_PHYS_ADDR 0x10600000
825 #define SD1_PHYS_ADDR 0x10680000
826 #define LCD_PHYS_ADDR 0x15000000
827 #define SWCNT_PHYS_ADDR 0x1110010C
828 #define MAEFE_PHYS_ADDR 0x14012000
829 #define MAEBE_PHYS_ADDR 0x14010000
830 #define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
831 #define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
832 #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
835 /* Static Bus Controller */
836 #define MEM_STCFG0 0xB4001000
837 #define MEM_STTIME0 0xB4001004
838 #define MEM_STADDR0 0xB4001008
840 #define MEM_STCFG1 0xB4001010
841 #define MEM_STTIME1 0xB4001014
842 #define MEM_STADDR1 0xB4001018
844 #define MEM_STCFG2 0xB4001020
845 #define MEM_STTIME2 0xB4001024
846 #define MEM_STADDR2 0xB4001028
848 #define MEM_STCFG3 0xB4001030
849 #define MEM_STTIME3 0xB4001034
850 #define MEM_STADDR3 0xB4001038
852 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
853 #define MEM_STNDCTL 0xB4001100
854 #define MEM_STSTAT 0xB4001104
856 #define MEM_STNAND_CMD 0x0
857 #define MEM_STNAND_ADDR 0x4
858 #define MEM_STNAND_DATA 0x20
865 #ifdef CONFIG_SOC_AU1000
867 #define UART0_ADDR 0xB1100000
868 #define UART3_ADDR 0xB1400000
870 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
871 #define USB_HOST_CONFIG 0xB017FFFC
872 #define FOR_PLATFORM_C_USB_HOST_INT AU1000_USB_HOST_INT
874 #define AU1000_ETH0_BASE 0xB0500000
875 #define AU1000_ETH1_BASE 0xB0510000
876 #define AU1000_MAC0_ENABLE 0xB0520000
877 #define AU1000_MAC1_ENABLE 0xB0520004
878 #define NUM_ETH_INTERFACES 2
879 #endif /* CONFIG_SOC_AU1000 */
882 #ifdef CONFIG_SOC_AU1500
884 #define UART0_ADDR 0xB1100000
885 #define UART3_ADDR 0xB1400000
887 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
888 #define USB_HOST_CONFIG 0xB017fffc
889 #define FOR_PLATFORM_C_USB_HOST_INT AU1500_USB_HOST_INT
891 #define AU1500_ETH0_BASE 0xB1500000
892 #define AU1500_ETH1_BASE 0xB1510000
893 #define AU1500_MAC0_ENABLE 0xB1520000
894 #define AU1500_MAC1_ENABLE 0xB1520004
895 #define NUM_ETH_INTERFACES 2
896 #endif /* CONFIG_SOC_AU1500 */
899 #ifdef CONFIG_SOC_AU1100
901 #define UART0_ADDR 0xB1100000
902 #define UART3_ADDR 0xB1400000
904 #define USB_OHCI_BASE 0x10100000 /* phys addr for ioremap */
905 #define USB_HOST_CONFIG 0xB017FFFC
906 #define FOR_PLATFORM_C_USB_HOST_INT AU1100_USB_HOST_INT
908 #define AU1100_ETH0_BASE 0xB0500000
909 #define AU1100_MAC0_ENABLE 0xB0520000
910 #define NUM_ETH_INTERFACES 1
911 #endif /* CONFIG_SOC_AU1100 */
913 #ifdef CONFIG_SOC_AU1550
914 #define UART0_ADDR 0xB1100000
916 #define USB_OHCI_BASE 0x14020000 /* phys addr for ioremap */
917 #define USB_OHCI_LEN 0x00060000
918 #define USB_HOST_CONFIG 0xB4027ffc
919 #define FOR_PLATFORM_C_USB_HOST_INT AU1550_USB_HOST_INT
921 #define AU1550_ETH0_BASE 0xB0500000
922 #define AU1550_ETH1_BASE 0xB0510000
923 #define AU1550_MAC0_ENABLE 0xB0520000
924 #define AU1550_MAC1_ENABLE 0xB0520004
925 #define NUM_ETH_INTERFACES 2
926 #endif /* CONFIG_SOC_AU1550 */
929 #ifdef CONFIG_SOC_AU1200
931 #define UART0_ADDR 0xB1100000
933 #define USB_UOC_BASE 0x14020020
934 #define USB_UOC_LEN 0x20
935 #define USB_OHCI_BASE 0x14020100
936 #define USB_OHCI_LEN 0x100
937 #define USB_EHCI_BASE 0x14020200
938 #define USB_EHCI_LEN 0x100
939 #define USB_UDC_BASE 0x14022000
940 #define USB_UDC_LEN 0x2000
941 #define USB_MSR_BASE 0xB4020000
942 #define USB_MSR_MCFG 4
943 #define USBMSRMCFG_OMEMEN 0
944 #define USBMSRMCFG_OBMEN 1
945 #define USBMSRMCFG_EMEMEN 2
946 #define USBMSRMCFG_EBMEN 3
947 #define USBMSRMCFG_DMEMEN 4
948 #define USBMSRMCFG_DBMEN 5
949 #define USBMSRMCFG_GMEMEN 6
950 #define USBMSRMCFG_OHCCLKEN 16
951 #define USBMSRMCFG_EHCCLKEN 17
952 #define USBMSRMCFG_UDCCLKEN 18
953 #define USBMSRMCFG_PHYPLLEN 19
954 #define USBMSRMCFG_RDCOMB 30
955 #define USBMSRMCFG_PFEN 31
957 #define FOR_PLATFORM_C_USB_HOST_INT AU1200_USB_INT
959 #endif /* CONFIG_SOC_AU1200 */
961 /* Programmable Counters 0 and 1 */
962 #define SYS_BASE 0xB1900000
963 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
964 # define SYS_CNTRL_E1S (1 << 23)
965 # define SYS_CNTRL_T1S (1 << 20)
966 # define SYS_CNTRL_M21 (1 << 19)
967 # define SYS_CNTRL_M11 (1 << 18)
968 # define SYS_CNTRL_M01 (1 << 17)
969 # define SYS_CNTRL_C1S (1 << 16)
970 # define SYS_CNTRL_BP (1 << 14)
971 # define SYS_CNTRL_EN1 (1 << 13)
972 # define SYS_CNTRL_BT1 (1 << 12)
973 # define SYS_CNTRL_EN0 (1 << 11)
974 # define SYS_CNTRL_BT0 (1 << 10)
975 # define SYS_CNTRL_E0 (1 << 8)
976 # define SYS_CNTRL_E0S (1 << 7)
977 # define SYS_CNTRL_32S (1 << 5)
978 # define SYS_CNTRL_T0S (1 << 4)
979 # define SYS_CNTRL_M20 (1 << 3)
980 # define SYS_CNTRL_M10 (1 << 2)
981 # define SYS_CNTRL_M00 (1 << 1)
982 # define SYS_CNTRL_C0S (1 << 0)
984 /* Programmable Counter 0 Registers */
985 #define SYS_TOYTRIM (SYS_BASE + 0)
986 #define SYS_TOYWRITE (SYS_BASE + 4)
987 #define SYS_TOYMATCH0 (SYS_BASE + 8)
988 #define SYS_TOYMATCH1 (SYS_BASE + 0xC)
989 #define SYS_TOYMATCH2 (SYS_BASE + 0x10)
990 #define SYS_TOYREAD (SYS_BASE + 0x40)
992 /* Programmable Counter 1 Registers */
993 #define SYS_RTCTRIM (SYS_BASE + 0x44)
994 #define SYS_RTCWRITE (SYS_BASE + 0x48)
995 #define SYS_RTCMATCH0 (SYS_BASE + 0x4C)
996 #define SYS_RTCMATCH1 (SYS_BASE + 0x50)
997 #define SYS_RTCMATCH2 (SYS_BASE + 0x54)
998 #define SYS_RTCREAD (SYS_BASE + 0x58)
1000 /* I2S Controller */
1001 #define I2S_DATA 0xB1000000
1002 # define I2S_DATA_MASK 0xffffff
1003 #define I2S_CONFIG 0xB1000004
1004 # define I2S_CONFIG_XU (1 << 25)
1005 # define I2S_CONFIG_XO (1 << 24)
1006 # define I2S_CONFIG_RU (1 << 23)
1007 # define I2S_CONFIG_RO (1 << 22)
1008 # define I2S_CONFIG_TR (1 << 21)
1009 # define I2S_CONFIG_TE (1 << 20)
1010 # define I2S_CONFIG_TF (1 << 19)
1011 # define I2S_CONFIG_RR (1 << 18)
1012 # define I2S_CONFIG_RE (1 << 17)
1013 # define I2S_CONFIG_RF (1 << 16)
1014 # define I2S_CONFIG_PD (1 << 11)
1015 # define I2S_CONFIG_LB (1 << 10)
1016 # define I2S_CONFIG_IC (1 << 9)
1017 # define I2S_CONFIG_FM_BIT 7
1018 # define I2S_CONFIG_FM_MASK (0x3 << I2S_CONFIG_FM_BIT)
1019 # define I2S_CONFIG_FM_I2S (0x0 << I2S_CONFIG_FM_BIT)
1020 # define I2S_CONFIG_FM_LJ (0x1 << I2S_CONFIG_FM_BIT)
1021 # define I2S_CONFIG_FM_RJ (0x2 << I2S_CONFIG_FM_BIT)
1022 # define I2S_CONFIG_TN (1 << 6)
1023 # define I2S_CONFIG_RN (1 << 5)
1024 # define I2S_CONFIG_SZ_BIT 0
1025 # define I2S_CONFIG_SZ_MASK (0x1F << I2S_CONFIG_SZ_BIT)
1027 #define I2S_CONTROL 0xB1000008
1028 # define I2S_CONTROL_D (1 << 1)
1029 # define I2S_CONTROL_CE (1 << 0)
1031 /* USB Host Controller */
1032 #ifndef USB_OHCI_LEN
1033 #define USB_OHCI_LEN 0x00100000
1036 #ifndef CONFIG_SOC_AU1200
1038 /* USB Device Controller */
1039 #define USBD_EP0RD 0xB0200000
1040 #define USBD_EP0WR 0xB0200004
1041 #define USBD_EP2WR 0xB0200008
1042 #define USBD_EP3WR 0xB020000C
1043 #define USBD_EP4RD 0xB0200010
1044 #define USBD_EP5RD 0xB0200014
1045 #define USBD_INTEN 0xB0200018
1046 #define USBD_INTSTAT 0xB020001C
1047 # define USBDEV_INT_SOF (1 << 12)
1048 # define USBDEV_INT_HF_BIT 6
1049 # define USBDEV_INT_HF_MASK (0x3f << USBDEV_INT_HF_BIT)
1050 # define USBDEV_INT_CMPLT_BIT 0
1051 # define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
1052 #define USBD_CONFIG 0xB0200020
1053 #define USBD_EP0CS 0xB0200024
1054 #define USBD_EP2CS 0xB0200028
1055 #define USBD_EP3CS 0xB020002C
1056 #define USBD_EP4CS 0xB0200030
1057 #define USBD_EP5CS 0xB0200034
1058 # define USBDEV_CS_SU (1 << 14)
1059 # define USBDEV_CS_NAK (1 << 13)
1060 # define USBDEV_CS_ACK (1 << 12)
1061 # define USBDEV_CS_BUSY (1 << 11)
1062 # define USBDEV_CS_TSIZE_BIT 1
1063 # define USBDEV_CS_TSIZE_MASK (0x3ff << USBDEV_CS_TSIZE_BIT)
1064 # define USBDEV_CS_STALL (1 << 0)
1065 #define USBD_EP0RDSTAT 0xB0200040
1066 #define USBD_EP0WRSTAT 0xB0200044
1067 #define USBD_EP2WRSTAT 0xB0200048
1068 #define USBD_EP3WRSTAT 0xB020004C
1069 #define USBD_EP4RDSTAT 0xB0200050
1070 #define USBD_EP5RDSTAT 0xB0200054
1071 # define USBDEV_FSTAT_FLUSH (1 << 6)
1072 # define USBDEV_FSTAT_UF (1 << 5)
1073 # define USBDEV_FSTAT_OF (1 << 4)
1074 # define USBDEV_FSTAT_FCNT_BIT 0
1075 # define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
1076 #define USBD_ENABLE 0xB0200058
1077 # define USBDEV_ENABLE (1 << 1)
1078 # define USBDEV_CE (1 << 0)
1080 #endif /* !CONFIG_SOC_AU1200 */
1082 /* Ethernet Controllers */
1084 /* 4 byte offsets from AU1000_ETH_BASE */
1085 #define MAC_CONTROL 0x0
1086 # define MAC_RX_ENABLE (1 << 2)
1087 # define MAC_TX_ENABLE (1 << 3)
1088 # define MAC_DEF_CHECK (1 << 5)
1089 # define MAC_SET_BL(X) (((X) & 0x3) << 6)
1090 # define MAC_AUTO_PAD (1 << 8)
1091 # define MAC_DISABLE_RETRY (1 << 10)
1092 # define MAC_DISABLE_BCAST (1 << 11)
1093 # define MAC_LATE_COL (1 << 12)
1094 # define MAC_HASH_MODE (1 << 13)
1095 # define MAC_HASH_ONLY (1 << 15)
1096 # define MAC_PASS_ALL (1 << 16)
1097 # define MAC_INVERSE_FILTER (1 << 17)
1098 # define MAC_PROMISCUOUS (1 << 18)
1099 # define MAC_PASS_ALL_MULTI (1 << 19)
1100 # define MAC_FULL_DUPLEX (1 << 20)
1101 # define MAC_NORMAL_MODE 0
1102 # define MAC_INT_LOOPBACK (1 << 21)
1103 # define MAC_EXT_LOOPBACK (1 << 22)
1104 # define MAC_DISABLE_RX_OWN (1 << 23)
1105 # define MAC_BIG_ENDIAN (1 << 30)
1106 # define MAC_RX_ALL (1 << 31)
1107 #define MAC_ADDRESS_HIGH 0x4
1108 #define MAC_ADDRESS_LOW 0x8
1109 #define MAC_MCAST_HIGH 0xC
1110 #define MAC_MCAST_LOW 0x10
1111 #define MAC_MII_CNTRL 0x14
1112 # define MAC_MII_BUSY (1 << 0)
1113 # define MAC_MII_READ 0
1114 # define MAC_MII_WRITE (1 << 1)
1115 # define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
1116 # define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
1117 #define MAC_MII_DATA 0x18
1118 #define MAC_FLOW_CNTRL 0x1C
1119 # define MAC_FLOW_CNTRL_BUSY (1 << 0)
1120 # define MAC_FLOW_CNTRL_ENABLE (1 << 1)
1121 # define MAC_PASS_CONTROL (1 << 2)
1122 # define MAC_SET_PAUSE(X) (((X) & 0xffff) << 16)
1123 #define MAC_VLAN1_TAG 0x20
1124 #define MAC_VLAN2_TAG 0x24
1126 /* Ethernet Controller Enable */
1128 # define MAC_EN_CLOCK_ENABLE (1 << 0)
1129 # define MAC_EN_RESET0 (1 << 1)
1130 # define MAC_EN_TOSS (0 << 2)
1131 # define MAC_EN_CACHEABLE (1 << 3)
1132 # define MAC_EN_RESET1 (1 << 4)
1133 # define MAC_EN_RESET2 (1 << 5)
1134 # define MAC_DMA_RESET (1 << 6)
1136 /* Ethernet Controller DMA Channels */
1138 #define MAC0_TX_DMA_ADDR 0xB4004000
1139 #define MAC1_TX_DMA_ADDR 0xB4004200
1140 /* offsets from MAC_TX_RING_ADDR address */
1141 #define MAC_TX_BUFF0_STATUS 0x0
1142 # define TX_FRAME_ABORTED (1 << 0)
1143 # define TX_JAB_TIMEOUT (1 << 1)
1144 # define TX_NO_CARRIER (1 << 2)
1145 # define TX_LOSS_CARRIER (1 << 3)
1146 # define TX_EXC_DEF (1 << 4)
1147 # define TX_LATE_COLL_ABORT (1 << 5)
1148 # define TX_EXC_COLL (1 << 6)
1149 # define TX_UNDERRUN (1 << 7)
1150 # define TX_DEFERRED (1 << 8)
1151 # define TX_LATE_COLL (1 << 9)
1152 # define TX_COLL_CNT_MASK (0xF << 10)
1153 # define TX_PKT_RETRY (1 << 31)
1154 #define MAC_TX_BUFF0_ADDR 0x4
1155 # define TX_DMA_ENABLE (1 << 0)
1156 # define TX_T_DONE (1 << 1)
1157 # define TX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1158 #define MAC_TX_BUFF0_LEN 0x8
1159 #define MAC_TX_BUFF1_STATUS 0x10
1160 #define MAC_TX_BUFF1_ADDR 0x14
1161 #define MAC_TX_BUFF1_LEN 0x18
1162 #define MAC_TX_BUFF2_STATUS 0x20
1163 #define MAC_TX_BUFF2_ADDR 0x24
1164 #define MAC_TX_BUFF2_LEN 0x28
1165 #define MAC_TX_BUFF3_STATUS 0x30
1166 #define MAC_TX_BUFF3_ADDR 0x34
1167 #define MAC_TX_BUFF3_LEN 0x38
1169 #define MAC0_RX_DMA_ADDR 0xB4004100
1170 #define MAC1_RX_DMA_ADDR 0xB4004300
1171 /* offsets from MAC_RX_RING_ADDR */
1172 #define MAC_RX_BUFF0_STATUS 0x0
1173 # define RX_FRAME_LEN_MASK 0x3fff
1174 # define RX_WDOG_TIMER (1 << 14)
1175 # define RX_RUNT (1 << 15)
1176 # define RX_OVERLEN (1 << 16)
1177 # define RX_COLL (1 << 17)
1178 # define RX_ETHER (1 << 18)
1179 # define RX_MII_ERROR (1 << 19)
1180 # define RX_DRIBBLING (1 << 20)
1181 # define RX_CRC_ERROR (1 << 21)
1182 # define RX_VLAN1 (1 << 22)
1183 # define RX_VLAN2 (1 << 23)
1184 # define RX_LEN_ERROR (1 << 24)
1185 # define RX_CNTRL_FRAME (1 << 25)
1186 # define RX_U_CNTRL_FRAME (1 << 26)
1187 # define RX_MCAST_FRAME (1 << 27)
1188 # define RX_BCAST_FRAME (1 << 28)
1189 # define RX_FILTER_FAIL (1 << 29)
1190 # define RX_PACKET_FILTER (1 << 30)
1191 # define RX_MISSED_FRAME (1 << 31)
1193 # define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN | \
1194 RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
1195 RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
1196 #define MAC_RX_BUFF0_ADDR 0x4
1197 # define RX_DMA_ENABLE (1 << 0)
1198 # define RX_T_DONE (1 << 1)
1199 # define RX_GET_DMA_BUFFER(X) (((X) >> 2) & 0x3)
1200 # define RX_SET_BUFF_ADDR(X) ((X) & 0xffffffc0)
1201 #define MAC_RX_BUFF1_STATUS 0x10
1202 #define MAC_RX_BUFF1_ADDR 0x14
1203 #define MAC_RX_BUFF2_STATUS 0x20
1204 #define MAC_RX_BUFF2_ADDR 0x24
1205 #define MAC_RX_BUFF3_STATUS 0x30
1206 #define MAC_RX_BUFF3_ADDR 0x34
1208 #define UART_RX 0 /* Receive buffer */
1209 #define UART_TX 4 /* Transmit buffer */
1210 #define UART_IER 8 /* Interrupt Enable Register */
1211 #define UART_IIR 0xC /* Interrupt ID Register */
1212 #define UART_FCR 0x10 /* FIFO Control Register */
1213 #define UART_LCR 0x14 /* Line Control Register */
1214 #define UART_MCR 0x18 /* Modem Control Register */
1215 #define UART_LSR 0x1C /* Line Status Register */
1216 #define UART_MSR 0x20 /* Modem Status Register */
1217 #define UART_CLK 0x28 /* Baud Rate Clock Divider */
1218 #define UART_MOD_CNTRL 0x100 /* Module Control */
1221 #define SSI0_STATUS 0xB1600000
1222 # define SSI_STATUS_BF (1 << 4)
1223 # define SSI_STATUS_OF (1 << 3)
1224 # define SSI_STATUS_UF (1 << 2)
1225 # define SSI_STATUS_D (1 << 1)
1226 # define SSI_STATUS_B (1 << 0)
1227 #define SSI0_INT 0xB1600004
1228 # define SSI_INT_OI (1 << 3)
1229 # define SSI_INT_UI (1 << 2)
1230 # define SSI_INT_DI (1 << 1)
1231 #define SSI0_INT_ENABLE 0xB1600008
1232 # define SSI_INTE_OIE (1 << 3)
1233 # define SSI_INTE_UIE (1 << 2)
1234 # define SSI_INTE_DIE (1 << 1)
1235 #define SSI0_CONFIG 0xB1600020
1236 # define SSI_CONFIG_AO (1 << 24)
1237 # define SSI_CONFIG_DO (1 << 23)
1238 # define SSI_CONFIG_ALEN_BIT 20
1239 # define SSI_CONFIG_ALEN_MASK (0x7 << 20)
1240 # define SSI_CONFIG_DLEN_BIT 16
1241 # define SSI_CONFIG_DLEN_MASK (0x7 << 16)
1242 # define SSI_CONFIG_DD (1 << 11)
1243 # define SSI_CONFIG_AD (1 << 10)
1244 # define SSI_CONFIG_BM_BIT 8
1245 # define SSI_CONFIG_BM_MASK (0x3 << 8)
1246 # define SSI_CONFIG_CE (1 << 7)
1247 # define SSI_CONFIG_DP (1 << 6)
1248 # define SSI_CONFIG_DL (1 << 5)
1249 # define SSI_CONFIG_EP (1 << 4)
1250 #define SSI0_ADATA 0xB1600024
1251 # define SSI_AD_D (1 << 24)
1252 # define SSI_AD_ADDR_BIT 16
1253 # define SSI_AD_ADDR_MASK (0xff << 16)
1254 # define SSI_AD_DATA_BIT 0
1255 # define SSI_AD_DATA_MASK (0xfff << 0)
1256 #define SSI0_CLKDIV 0xB1600028
1257 #define SSI0_CONTROL 0xB1600100
1258 # define SSI_CONTROL_CD (1 << 1)
1259 # define SSI_CONTROL_E (1 << 0)
1262 #define SSI1_STATUS 0xB1680000
1263 #define SSI1_INT 0xB1680004
1264 #define SSI1_INT_ENABLE 0xB1680008
1265 #define SSI1_CONFIG 0xB1680020
1266 #define SSI1_ADATA 0xB1680024
1267 #define SSI1_CLKDIV 0xB1680028
1268 #define SSI1_ENABLE 0xB1680100
1271 * Register content definitions
1273 #define SSI_STATUS_BF (1 << 4)
1274 #define SSI_STATUS_OF (1 << 3)
1275 #define SSI_STATUS_UF (1 << 2)
1276 #define SSI_STATUS_D (1 << 1)
1277 #define SSI_STATUS_B (1 << 0)
1280 #define SSI_INT_OI (1 << 3)
1281 #define SSI_INT_UI (1 << 2)
1282 #define SSI_INT_DI (1 << 1)
1285 #define SSI_INTEN_OIE (1 << 3)
1286 #define SSI_INTEN_UIE (1 << 2)
1287 #define SSI_INTEN_DIE (1 << 1)
1289 #define SSI_CONFIG_AO (1 << 24)
1290 #define SSI_CONFIG_DO (1 << 23)
1291 #define SSI_CONFIG_ALEN (7 << 20)
1292 #define SSI_CONFIG_DLEN (15 << 16)
1293 #define SSI_CONFIG_DD (1 << 11)
1294 #define SSI_CONFIG_AD (1 << 10)
1295 #define SSI_CONFIG_BM (3 << 8)
1296 #define SSI_CONFIG_CE (1 << 7)
1297 #define SSI_CONFIG_DP (1 << 6)
1298 #define SSI_CONFIG_DL (1 << 5)
1299 #define SSI_CONFIG_EP (1 << 4)
1300 #define SSI_CONFIG_ALEN_N(N) ((N-1) << 20)
1301 #define SSI_CONFIG_DLEN_N(N) ((N-1) << 16)
1302 #define SSI_CONFIG_BM_HI (0 << 8)
1303 #define SSI_CONFIG_BM_LO (1 << 8)
1304 #define SSI_CONFIG_BM_CY (2 << 8)
1306 #define SSI_ADATA_D (1 << 24)
1307 #define SSI_ADATA_ADDR (0xFF << 16)
1308 #define SSI_ADATA_DATA 0x0FFF
1309 #define SSI_ADATA_ADDR_N(N) (N << 16)
1311 #define SSI_ENABLE_CD (1 << 1)
1312 #define SSI_ENABLE_E (1 << 0)
1314 /* IrDA Controller */
1315 #define IRDA_BASE 0xB0300000
1316 #define IR_RING_PTR_STATUS (IRDA_BASE + 0x00)
1317 #define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04)
1318 #define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08)
1319 #define IR_RING_SIZE (IRDA_BASE + 0x0C)
1320 #define IR_RING_PROMPT (IRDA_BASE + 0x10)
1321 #define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14)
1322 #define IR_INT_CLEAR (IRDA_BASE + 0x18)
1323 #define IR_CONFIG_1 (IRDA_BASE + 0x20)
1324 # define IR_RX_INVERT_LED (1 << 0)
1325 # define IR_TX_INVERT_LED (1 << 1)
1326 # define IR_ST (1 << 2)
1327 # define IR_SF (1 << 3)
1328 # define IR_SIR (1 << 4)
1329 # define IR_MIR (1 << 5)
1330 # define IR_FIR (1 << 6)
1331 # define IR_16CRC (1 << 7)
1332 # define IR_TD (1 << 8)
1333 # define IR_RX_ALL (1 << 9)
1334 # define IR_DMA_ENABLE (1 << 10)
1335 # define IR_RX_ENABLE (1 << 11)
1336 # define IR_TX_ENABLE (1 << 12)
1337 # define IR_LOOPBACK (1 << 14)
1338 # define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \
1339 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
1340 #define IR_SIR_FLAGS (IRDA_BASE + 0x24)
1341 #define IR_ENABLE (IRDA_BASE + 0x28)
1342 # define IR_RX_STATUS (1 << 9)
1343 # define IR_TX_STATUS (1 << 10)
1344 #define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C)
1345 #define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30)
1346 #define IR_MAX_PKT_LEN (IRDA_BASE + 0x34)
1347 #define IR_RX_BYTE_CNT (IRDA_BASE + 0x38)
1348 #define IR_CONFIG_2 (IRDA_BASE + 0x3C)
1349 # define IR_MODE_INV (1 << 0)
1350 # define IR_ONE_PIN (1 << 1)
1351 #define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40)
1354 #define SYS_PINFUNC 0xB190002C
1355 # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */
1356 # define SYS_PF_U3 (1 << 14) /* GPIO23/U3TXD */
1357 # define SYS_PF_U2 (1 << 13) /* GPIO22/U2TXD */
1358 # define SYS_PF_U1 (1 << 12) /* GPIO21/U1TXD */
1359 # define SYS_PF_SRC (1 << 11) /* GPIO6/SROMCKE */
1360 # define SYS_PF_CK5 (1 << 10) /* GPIO3/CLK5 */
1361 # define SYS_PF_CK4 (1 << 9) /* GPIO2/CLK4 */
1362 # define SYS_PF_IRF (1 << 8) /* GPIO15/IRFIRSEL */
1363 # define SYS_PF_UR3 (1 << 7) /* GPIO[14:9]/UART3 */
1364 # define SYS_PF_I2D (1 << 6) /* GPIO8/I2SDI */
1365 # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
1366 # define SYS_PF_NI2 (1 << 4) /* NI2/GPIO[24:28] */
1367 # define SYS_PF_U0 (1 << 3) /* U0TXD/GPIO20 */
1368 # define SYS_PF_RD (1 << 2) /* IRTXD/GPIO19 */
1369 # define SYS_PF_A97 (1 << 1) /* AC97/SSL1 */
1370 # define SYS_PF_S0 (1 << 0) /* SSI_0/GPIO[16:18] */
1373 # define SYS_PF_PC (1 << 18) /* PCMCIA/GPIO[207:204] */
1374 # define SYS_PF_LCD (1 << 17) /* extern lcd/GPIO[203:200] */
1375 # define SYS_PF_CS (1 << 16) /* EXTCLK0/32KHz to gpio2 */
1376 # define SYS_PF_EX0 (1 << 9) /* GPIO2/clock */
1378 /* Au1550 only. Redefines lots of pins */
1379 # define SYS_PF_PSC2_MASK (7 << 17)
1380 # define SYS_PF_PSC2_AC97 0
1381 # define SYS_PF_PSC2_SPI 0
1382 # define SYS_PF_PSC2_I2S (1 << 17)
1383 # define SYS_PF_PSC2_SMBUS (3 << 17)
1384 # define SYS_PF_PSC2_GPIO (7 << 17)
1385 # define SYS_PF_PSC3_MASK (7 << 20)
1386 # define SYS_PF_PSC3_AC97 0
1387 # define SYS_PF_PSC3_SPI 0
1388 # define SYS_PF_PSC3_I2S (1 << 20)
1389 # define SYS_PF_PSC3_SMBUS (3 << 20)
1390 # define SYS_PF_PSC3_GPIO (7 << 20)
1391 # define SYS_PF_PSC1_S1 (1 << 1)
1392 # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1395 #ifdef CONFIG_SOC_AU1200
1396 #define SYS_PINFUNC_DMA (1 << 31)
1397 #define SYS_PINFUNC_S0A (1 << 30)
1398 #define SYS_PINFUNC_S1A (1 << 29)
1399 #define SYS_PINFUNC_LP0 (1 << 28)
1400 #define SYS_PINFUNC_LP1 (1 << 27)
1401 #define SYS_PINFUNC_LD16 (1 << 26)
1402 #define SYS_PINFUNC_LD8 (1 << 25)
1403 #define SYS_PINFUNC_LD1 (1 << 24)
1404 #define SYS_PINFUNC_LD0 (1 << 23)
1405 #define SYS_PINFUNC_P1A (3 << 21)
1406 #define SYS_PINFUNC_P1B (1 << 20)
1407 #define SYS_PINFUNC_FS3 (1 << 19)
1408 #define SYS_PINFUNC_P0A (3 << 17)
1409 #define SYS_PINFUNC_CS (1 << 16)
1410 #define SYS_PINFUNC_CIM (1 << 15)
1411 #define SYS_PINFUNC_P1C (1 << 14)
1412 #define SYS_PINFUNC_U1T (1 << 12)
1413 #define SYS_PINFUNC_U1R (1 << 11)
1414 #define SYS_PINFUNC_EX1 (1 << 10)
1415 #define SYS_PINFUNC_EX0 (1 << 9)
1416 #define SYS_PINFUNC_U0R (1 << 8)
1417 #define SYS_PINFUNC_MC (1 << 7)
1418 #define SYS_PINFUNC_S0B (1 << 6)
1419 #define SYS_PINFUNC_S0C (1 << 5)
1420 #define SYS_PINFUNC_P0B (1 << 4)
1421 #define SYS_PINFUNC_U0T (1 << 3)
1422 #define SYS_PINFUNC_S1B (1 << 2)
1425 #define SYS_TRIOUTRD 0xB1900100
1426 #define SYS_TRIOUTCLR 0xB1900100
1427 #define SYS_OUTPUTRD 0xB1900108
1428 #define SYS_OUTPUTSET 0xB1900108
1429 #define SYS_OUTPUTCLR 0xB190010C
1430 #define SYS_PINSTATERD 0xB1900110
1431 #define SYS_PININPUTEN 0xB1900110
1433 /* GPIO2, Au1500, Au1550 only */
1434 #define GPIO2_BASE 0xB1700000
1435 #define GPIO2_DIR (GPIO2_BASE + 0)
1436 #define GPIO2_OUTPUT (GPIO2_BASE + 8)
1437 #define GPIO2_PINSTATE (GPIO2_BASE + 0xC)
1438 #define GPIO2_INTENABLE (GPIO2_BASE + 0x10)
1439 #define GPIO2_ENABLE (GPIO2_BASE + 0x14)
1441 /* Power Management */
1442 #define SYS_SCRATCH0 0xB1900018
1443 #define SYS_SCRATCH1 0xB190001C
1444 #define SYS_WAKEMSK 0xB1900034
1445 #define SYS_ENDIAN 0xB1900038
1446 #define SYS_POWERCTRL 0xB190003C
1447 #define SYS_WAKESRC 0xB190005C
1448 #define SYS_SLPPWR 0xB1900078
1449 #define SYS_SLEEP 0xB190007C
1451 #define SYS_WAKEMSK_D2 (1 << 9)
1452 #define SYS_WAKEMSK_M2 (1 << 8)
1453 #define SYS_WAKEMSK_GPIO(x) (1 << (x))
1455 /* Clock Controller */
1456 #define SYS_FREQCTRL0 0xB1900020
1457 # define SYS_FC_FRDIV2_BIT 22
1458 # define SYS_FC_FRDIV2_MASK (0xff << SYS_FC_FRDIV2_BIT)
1459 # define SYS_FC_FE2 (1 << 21)
1460 # define SYS_FC_FS2 (1 << 20)
1461 # define SYS_FC_FRDIV1_BIT 12
1462 # define SYS_FC_FRDIV1_MASK (0xff << SYS_FC_FRDIV1_BIT)
1463 # define SYS_FC_FE1 (1 << 11)
1464 # define SYS_FC_FS1 (1 << 10)
1465 # define SYS_FC_FRDIV0_BIT 2
1466 # define SYS_FC_FRDIV0_MASK (0xff << SYS_FC_FRDIV0_BIT)
1467 # define SYS_FC_FE0 (1 << 1)
1468 # define SYS_FC_FS0 (1 << 0)
1469 #define SYS_FREQCTRL1 0xB1900024
1470 # define SYS_FC_FRDIV5_BIT 22
1471 # define SYS_FC_FRDIV5_MASK (0xff << SYS_FC_FRDIV5_BIT)
1472 # define SYS_FC_FE5 (1 << 21)
1473 # define SYS_FC_FS5 (1 << 20)
1474 # define SYS_FC_FRDIV4_BIT 12
1475 # define SYS_FC_FRDIV4_MASK (0xff << SYS_FC_FRDIV4_BIT)
1476 # define SYS_FC_FE4 (1 << 11)
1477 # define SYS_FC_FS4 (1 << 10)
1478 # define SYS_FC_FRDIV3_BIT 2
1479 # define SYS_FC_FRDIV3_MASK (0xff << SYS_FC_FRDIV3_BIT)
1480 # define SYS_FC_FE3 (1 << 1)
1481 # define SYS_FC_FS3 (1 << 0)
1482 #define SYS_CLKSRC 0xB1900028
1483 # define SYS_CS_ME1_BIT 27
1484 # define SYS_CS_ME1_MASK (0x7 << SYS_CS_ME1_BIT)
1485 # define SYS_CS_DE1 (1 << 26)
1486 # define SYS_CS_CE1 (1 << 25)
1487 # define SYS_CS_ME0_BIT 22
1488 # define SYS_CS_ME0_MASK (0x7 << SYS_CS_ME0_BIT)
1489 # define SYS_CS_DE0 (1 << 21)
1490 # define SYS_CS_CE0 (1 << 20)
1491 # define SYS_CS_MI2_BIT 17
1492 # define SYS_CS_MI2_MASK (0x7 << SYS_CS_MI2_BIT)
1493 # define SYS_CS_DI2 (1 << 16)
1494 # define SYS_CS_CI2 (1 << 15)
1495 #ifdef CONFIG_SOC_AU1100
1496 # define SYS_CS_ML_BIT 7
1497 # define SYS_CS_ML_MASK (0x7 << SYS_CS_ML_BIT)
1498 # define SYS_CS_DL (1 << 6)
1499 # define SYS_CS_CL (1 << 5)
1501 # define SYS_CS_MUH_BIT 12
1502 # define SYS_CS_MUH_MASK (0x7 << SYS_CS_MUH_BIT)
1503 # define SYS_CS_DUH (1 << 11)
1504 # define SYS_CS_CUH (1 << 10)
1505 # define SYS_CS_MUD_BIT 7
1506 # define SYS_CS_MUD_MASK (0x7 << SYS_CS_MUD_BIT)
1507 # define SYS_CS_DUD (1 << 6)
1508 # define SYS_CS_CUD (1 << 5)
1510 # define SYS_CS_MIR_BIT 2
1511 # define SYS_CS_MIR_MASK (0x7 << SYS_CS_MIR_BIT)
1512 # define SYS_CS_DIR (1 << 1)
1513 # define SYS_CS_CIR (1 << 0)
1515 # define SYS_CS_MUX_AUX 0x1
1516 # define SYS_CS_MUX_FQ0 0x2
1517 # define SYS_CS_MUX_FQ1 0x3
1518 # define SYS_CS_MUX_FQ2 0x4
1519 # define SYS_CS_MUX_FQ3 0x5
1520 # define SYS_CS_MUX_FQ4 0x6
1521 # define SYS_CS_MUX_FQ5 0x7
1522 #define SYS_CPUPLL 0xB1900060
1523 #define SYS_AUXPLL 0xB1900064
1525 /* AC97 Controller */
1526 #define AC97C_CONFIG 0xB0000000
1527 # define AC97C_RECV_SLOTS_BIT 13
1528 # define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
1529 # define AC97C_XMIT_SLOTS_BIT 3
1530 # define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
1531 # define AC97C_SG (1 << 2)
1532 # define AC97C_SYNC (1 << 1)
1533 # define AC97C_RESET (1 << 0)
1534 #define AC97C_STATUS 0xB0000004
1535 # define AC97C_XU (1 << 11)
1536 # define AC97C_XO (1 << 10)
1537 # define AC97C_RU (1 << 9)
1538 # define AC97C_RO (1 << 8)
1539 # define AC97C_READY (1 << 7)
1540 # define AC97C_CP (1 << 6)
1541 # define AC97C_TR (1 << 5)
1542 # define AC97C_TE (1 << 4)
1543 # define AC97C_TF (1 << 3)
1544 # define AC97C_RR (1 << 2)
1545 # define AC97C_RE (1 << 1)
1546 # define AC97C_RF (1 << 0)
1547 #define AC97C_DATA 0xB0000008
1548 #define AC97C_CMD 0xB000000C
1549 # define AC97C_WD_BIT 16
1550 # define AC97C_READ (1 << 7)
1551 # define AC97C_INDEX_MASK 0x7f
1552 #define AC97C_CNTRL 0xB0000010
1553 # define AC97C_RS (1 << 1)
1554 # define AC97C_CE (1 << 0)
1556 /* Secure Digital (SD) Controller */
1557 #define SD0_XMIT_FIFO 0xB0600000
1558 #define SD0_RECV_FIFO 0xB0600004
1559 #define SD1_XMIT_FIFO 0xB0680000
1560 #define SD1_RECV_FIFO 0xB0680004
1562 #if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1563 /* Au1500 PCI Controller */
1564 #define Au1500_CFG_BASE 0xB4005000 /* virtual, KSEG1 addr */
1565 #define Au1500_PCI_CMEM (Au1500_CFG_BASE + 0)
1566 #define Au1500_PCI_CFG (Au1500_CFG_BASE + 4)
1567 # define PCI_ERROR ((1 << 22) | (1 << 23) | (1 << 24) | \
1568 (1 << 25) | (1 << 26) | (1 << 27))
1569 #define Au1500_PCI_B2BMASK_CCH (Au1500_CFG_BASE + 8)
1570 #define Au1500_PCI_B2B0_VID (Au1500_CFG_BASE + 0xC)
1571 #define Au1500_PCI_B2B1_ID (Au1500_CFG_BASE + 0x10)
1572 #define Au1500_PCI_MWMASK_DEV (Au1500_CFG_BASE + 0x14)
1573 #define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
1574 #define Au1500_PCI_ERR_ADDR (Au1500_CFG_BASE + 0x1C)
1575 #define Au1500_PCI_SPEC_INTACK (Au1500_CFG_BASE + 0x20)
1576 #define Au1500_PCI_ID (Au1500_CFG_BASE + 0x100)
1577 #define Au1500_PCI_STATCMD (Au1500_CFG_BASE + 0x104)
1578 #define Au1500_PCI_CLASSREV (Au1500_CFG_BASE + 0x108)
1579 #define Au1500_PCI_HDRTYPE (Au1500_CFG_BASE + 0x10C)
1580 #define Au1500_PCI_MBAR (Au1500_CFG_BASE + 0x110)
1582 #define Au1500_PCI_HDR 0xB4005100 /* virtual, KSEG1 addr */
1585 * All of our structures, like PCI resource, have 32-bit members.
1586 * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
1587 * hard to store 0x4 0000 0000 in a 32-bit type. We require a small patch
1588 * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
1589 * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
1590 * addresses. For PCI I/O, it's simpler because we get to do the ioremap
1591 * ourselves and then adjust the device's resources.
1593 #define Au1500_EXT_CFG 0x600000000ULL
1594 #define Au1500_EXT_CFG_TYPE1 0x680000000ULL
1595 #define Au1500_PCI_IO_START 0x500000000ULL
1596 #define Au1500_PCI_IO_END 0x5000FFFFFULL
1597 #define Au1500_PCI_MEM_START 0x440000000ULL
1598 #define Au1500_PCI_MEM_END 0x44FFFFFFFULL
1600 #define PCI_IO_START 0x00001000
1601 #define PCI_IO_END 0x000FFFFF
1602 #define PCI_MEM_START 0x40000000
1603 #define PCI_MEM_END 0x4FFFFFFF
1605 #define PCI_FIRST_DEVFN (0 << 3)
1606 #define PCI_LAST_DEVFN (19 << 3)
1608 #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */
1609 #define IOPORT_RESOURCE_END 0xffffffff
1610 #define IOMEM_RESOURCE_START 0x10000000
1611 #define IOMEM_RESOURCE_END 0xfffffffffULL
1613 #else /* Au1000 and Au1100 and Au1200 */
1615 /* Don't allow any legacy ports probing */
1616 #define IOPORT_RESOURCE_START 0x10000000
1617 #define IOPORT_RESOURCE_END 0xffffffff
1618 #define IOMEM_RESOURCE_START 0x10000000
1619 #define IOMEM_RESOURCE_END 0xfffffffffULL
1621 #define PCI_IO_START 0
1622 #define PCI_IO_END 0
1623 #define PCI_MEM_START 0
1624 #define PCI_MEM_END 0
1625 #define PCI_FIRST_DEVFN 0
1626 #define PCI_LAST_DEVFN 0