arch/mips/alchemy/common/platform.c

   1 /*
   2  * Platform device support for Au1x00 SoCs.
   3  *
   4  * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
   5  *
   6  * (C) Copyright Embedded Alley Solutions, Inc 2005
   7  * Author: Pantelis Antoniou <pantelis@embeddedalley.com>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2.  This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/dma-mapping.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/serial_8250.h>
  18 #include <linux/init.h>
  19
  20 #include <asm/mach-au1x00/au1xxx.h>
  21 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  22 #include <asm/mach-au1x00/au1100_mmc.h>
  23 #include <asm/mach-au1x00/au1xxx_eth.h>
  24
  25 #include <prom.h>
  26
  27 static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
  28                             unsigned int old_state)
  29 {
  30 #ifdef CONFIG_SERIAL_8250
  31         switch (state) {
  32         case 0:
  33                 alchemy_uart_enable(CPHYSADDR(port->membase));
  34                 serial8250_do_pm(port, state, old_state);
  35                 break;
  36         case 3:         /* power off */
  37                 serial8250_do_pm(port, state, old_state);
  38                 alchemy_uart_disable(CPHYSADDR(port->membase));
  39                 break;
  40         default:
  41                 serial8250_do_pm(port, state, old_state);
  42                 break;
  43         }
  44 #endif
  45 }
  46
  47 #define PORT(_base, _irq)                                       \
  48         {                                                       \
  49                 .mapbase        = _base,                        \
  50                 .irq            = _irq,                         \
  51                 .regshift       = 2,                            \
  52                 .iotype         = UPIO_AU,                      \
  53                 .flags          = UPF_SKIP_TEST | UPF_IOREMAP | \
  54                                   UPF_FIXED_TYPE,               \
  55                 .type           = PORT_16550A,                  \
  56                 .pm             = alchemy_8250_pm,              \
  57         }
  58
  59 static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = {
  60         [ALCHEMY_CPU_AU1000] = {
  61                 PORT(AU1000_UART0_PHYS_ADDR, AU1000_UART0_INT),
  62                 PORT(AU1000_UART1_PHYS_ADDR, AU1000_UART1_INT),
  63                 PORT(AU1000_UART2_PHYS_ADDR, AU1000_UART2_INT),
  64                 PORT(AU1000_UART3_PHYS_ADDR, AU1000_UART3_INT),
  65         },
  66         [ALCHEMY_CPU_AU1500] = {
  67                 PORT(AU1000_UART0_PHYS_ADDR, AU1500_UART0_INT),
  68                 PORT(AU1000_UART3_PHYS_ADDR, AU1500_UART3_INT),
  69         },
  70         [ALCHEMY_CPU_AU1100] = {
  71                 PORT(AU1000_UART0_PHYS_ADDR, AU1100_UART0_INT),
  72                 PORT(AU1000_UART1_PHYS_ADDR, AU1100_UART1_INT),
  73                 PORT(AU1000_UART3_PHYS_ADDR, AU1100_UART3_INT),
  74         },
  75         [ALCHEMY_CPU_AU1550] = {
  76                 PORT(AU1000_UART0_PHYS_ADDR, AU1550_UART0_INT),
  77                 PORT(AU1000_UART1_PHYS_ADDR, AU1550_UART1_INT),
  78                 PORT(AU1000_UART3_PHYS_ADDR, AU1550_UART3_INT),
  79         },
  80         [ALCHEMY_CPU_AU1200] = {
  81                 PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT),
  82                 PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT),
  83         },
  84 };
  85
  86 static struct platform_device au1xx0_uart_device = {
  87         .name                   = "serial8250",
  88         .id                     = PLAT8250_DEV_AU1X00,
  89 };
  90
  91 static void __init alchemy_setup_uarts(int ctype)
  92 {
  93         unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
  94         int s = sizeof(struct plat_serial8250_port);
  95         int c = alchemy_get_uarts(ctype);
  96         struct plat_serial8250_port *ports;
  97
  98         ports = kzalloc(s * (c + 1), GFP_KERNEL);
  99         if (!ports) {
 100                 printk(KERN_INFO "Alchemy: no memory for UART data\n");
 101                 return;
 102         }
 103         memcpy(ports, au1x00_uart_data[ctype], s * c);
 104         au1xx0_uart_device.dev.platform_data = ports;
 105
 106         /* Fill up uartclk. */
 107         for (s = 0; s < c; s++)
 108                 ports[s].uartclk = uartclk;
 109         if (platform_device_register(&au1xx0_uart_device))
 110                 printk(KERN_INFO "Alchemy: failed to register UARTs\n");
 111 }
 112
 113 /* OHCI (USB full speed host controller) */
 114 static struct resource au1xxx_usb_ohci_resources[] = {
 115         [0] = {
 116                 .start          = USB_OHCI_BASE,
 117                 .end            = USB_OHCI_BASE + USB_OHCI_LEN - 1,
 118                 .flags          = IORESOURCE_MEM,
 119         },
 120         [1] = {
 121                 .start          = FOR_PLATFORM_C_USB_HOST_INT,
 122                 .end            = FOR_PLATFORM_C_USB_HOST_INT,
 123                 .flags          = IORESOURCE_IRQ,
 124         },
 125 };
 126
 127 /* The dmamask must be set for OHCI to work */
 128 static u64 ohci_dmamask = DMA_BIT_MASK(32);
 129
 130 static struct platform_device au1xxx_usb_ohci_device = {
 131         .name           = "au1xxx-ohci",
 132         .id             = 0,
 133         .dev = {
 134                 .dma_mask               = &ohci_dmamask,
 135                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 136         },
 137         .num_resources  = ARRAY_SIZE(au1xxx_usb_ohci_resources),
 138         .resource       = au1xxx_usb_ohci_resources,
 139 };
 140
 141 /*** AU1100 LCD controller ***/
 142
 143 #ifdef CONFIG_FB_AU1100
 144 static struct resource au1100_lcd_resources[] = {
 145         [0] = {
 146                 .start          = LCD_PHYS_ADDR,
 147                 .end            = LCD_PHYS_ADDR + 0x800 - 1,
 148                 .flags          = IORESOURCE_MEM,
 149         },
 150         [1] = {
 151                 .start          = AU1100_LCD_INT,
 152                 .end            = AU1100_LCD_INT,
 153                 .flags          = IORESOURCE_IRQ,
 154         }
 155 };
 156
 157 static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
 158
 159 static struct platform_device au1100_lcd_device = {
 160         .name           = "au1100-lcd",
 161         .id             = 0,
 162         .dev = {
 163                 .dma_mask               = &au1100_lcd_dmamask,
 164                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 165         },
 166         .num_resources  = ARRAY_SIZE(au1100_lcd_resources),
 167         .resource       = au1100_lcd_resources,
 168 };
 169 #endif
 170
 171 #ifdef CONFIG_SOC_AU1200
 172 /* EHCI (USB high speed host controller) */
 173 static struct resource au1xxx_usb_ehci_resources[] = {
 174         [0] = {
 175                 .start          = USB_EHCI_BASE,
 176                 .end            = USB_EHCI_BASE + USB_EHCI_LEN - 1,
 177                 .flags          = IORESOURCE_MEM,
 178         },
 179         [1] = {
 180                 .start          = AU1200_USB_INT,
 181                 .end            = AU1200_USB_INT,
 182                 .flags          = IORESOURCE_IRQ,
 183         },
 184 };
 185
 186 static u64 ehci_dmamask = DMA_BIT_MASK(32);
 187
 188 static struct platform_device au1xxx_usb_ehci_device = {
 189         .name           = "au1xxx-ehci",
 190         .id             = 0,
 191         .dev = {
 192                 .dma_mask               = &ehci_dmamask,
 193                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 194         },
 195         .num_resources  = ARRAY_SIZE(au1xxx_usb_ehci_resources),
 196         .resource       = au1xxx_usb_ehci_resources,
 197 };
 198
 199 /* Au1200 UDC (USB gadget controller) */
 200 static struct resource au1xxx_usb_gdt_resources[] = {
 201         [0] = {
 202                 .start          = USB_UDC_BASE,
 203                 .end            = USB_UDC_BASE + USB_UDC_LEN - 1,
 204                 .flags          = IORESOURCE_MEM,
 205         },
 206         [1] = {
 207                 .start          = AU1200_USB_INT,
 208                 .end            = AU1200_USB_INT,
 209                 .flags          = IORESOURCE_IRQ,
 210         },
 211 };
 212
 213 static u64 udc_dmamask = DMA_BIT_MASK(32);
 214
 215 static struct platform_device au1xxx_usb_gdt_device = {
 216         .name           = "au1xxx-udc",
 217         .id             = 0,
 218         .dev = {
 219                 .dma_mask               = &udc_dmamask,
 220                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 221         },
 222         .num_resources  = ARRAY_SIZE(au1xxx_usb_gdt_resources),
 223         .resource       = au1xxx_usb_gdt_resources,
 224 };
 225
 226 /* Au1200 UOC (USB OTG controller) */
 227 static struct resource au1xxx_usb_otg_resources[] = {
 228         [0] = {
 229                 .start          = USB_UOC_BASE,
 230                 .end            = USB_UOC_BASE + USB_UOC_LEN - 1,
 231                 .flags          = IORESOURCE_MEM,
 232         },
 233         [1] = {
 234                 .start          = AU1200_USB_INT,
 235                 .end            = AU1200_USB_INT,
 236                 .flags          = IORESOURCE_IRQ,
 237         },
 238 };
 239
 240 static u64 uoc_dmamask = DMA_BIT_MASK(32);
 241
 242 static struct platform_device au1xxx_usb_otg_device = {
 243         .name           = "au1xxx-uoc",
 244         .id             = 0,
 245         .dev = {
 246                 .dma_mask               = &uoc_dmamask,
 247                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 248         },
 249         .num_resources  = ARRAY_SIZE(au1xxx_usb_otg_resources),
 250         .resource       = au1xxx_usb_otg_resources,
 251 };
 252
 253 static struct resource au1200_lcd_resources[] = {
 254         [0] = {
 255                 .start          = LCD_PHYS_ADDR,
 256                 .end            = LCD_PHYS_ADDR + 0x800 - 1,
 257                 .flags          = IORESOURCE_MEM,
 258         },
 259         [1] = {
 260                 .start          = AU1200_LCD_INT,
 261                 .end            = AU1200_LCD_INT,
 262                 .flags          = IORESOURCE_IRQ,
 263         }
 264 };
 265
 266 static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
 267
 268 static struct platform_device au1200_lcd_device = {
 269         .name           = "au1200-lcd",
 270         .id             = 0,
 271         .dev = {
 272                 .dma_mask               = &au1200_lcd_dmamask,
 273                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 274         },
 275         .num_resources  = ARRAY_SIZE(au1200_lcd_resources),
 276         .resource       = au1200_lcd_resources,
 277 };
 278
 279 static u64 au1xxx_mmc_dmamask =  DMA_BIT_MASK(32);
 280
 281 extern struct au1xmmc_platform_data au1xmmc_platdata[2];
 282
 283 static struct resource au1200_mmc0_resources[] = {
 284         [0] = {
 285                 .start          = SD0_PHYS_ADDR,
 286                 .end            = SD0_PHYS_ADDR + 0x7ffff,
 287                 .flags          = IORESOURCE_MEM,
 288         },
 289         [1] = {
 290                 .start          = AU1200_SD_INT,
 291                 .end            = AU1200_SD_INT,
 292                 .flags          = IORESOURCE_IRQ,
 293         },
 294         [2] = {
 295                 .start          = DSCR_CMD0_SDMS_TX0,
 296                 .end            = DSCR_CMD0_SDMS_TX0,
 297                 .flags          = IORESOURCE_DMA,
 298         },
 299         [3] = {
 300                 .start          = DSCR_CMD0_SDMS_RX0,
 301                 .end            = DSCR_CMD0_SDMS_RX0,
 302                 .flags          = IORESOURCE_DMA,
 303         }
 304 };
 305
 306 static struct platform_device au1200_mmc0_device = {
 307         .name = "au1xxx-mmc",
 308         .id = 0,
 309         .dev = {
 310                 .dma_mask               = &au1xxx_mmc_dmamask,
 311                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 312                 .platform_data          = &au1xmmc_platdata[0],
 313         },
 314         .num_resources  = ARRAY_SIZE(au1200_mmc0_resources),
 315         .resource       = au1200_mmc0_resources,
 316 };
 317
 318 #ifndef CONFIG_MIPS_DB1200
 319 static struct resource au1200_mmc1_resources[] = {
 320         [0] = {
 321                 .start          = SD1_PHYS_ADDR,
 322                 .end            = SD1_PHYS_ADDR + 0x7ffff,
 323                 .flags          = IORESOURCE_MEM,
 324         },
 325         [1] = {
 326                 .start          = AU1200_SD_INT,
 327                 .end            = AU1200_SD_INT,
 328                 .flags          = IORESOURCE_IRQ,
 329         },
 330         [2] = {
 331                 .start          = DSCR_CMD0_SDMS_TX1,
 332                 .end            = DSCR_CMD0_SDMS_TX1,
 333                 .flags          = IORESOURCE_DMA,
 334         },
 335         [3] = {
 336                 .start          = DSCR_CMD0_SDMS_RX1,
 337                 .end            = DSCR_CMD0_SDMS_RX1,
 338                 .flags          = IORESOURCE_DMA,
 339         }
 340 };
 341
 342 static struct platform_device au1200_mmc1_device = {
 343         .name = "au1xxx-mmc",
 344         .id = 1,
 345         .dev = {
 346                 .dma_mask               = &au1xxx_mmc_dmamask,
 347                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 348                 .platform_data          = &au1xmmc_platdata[1],
 349         },
 350         .num_resources  = ARRAY_SIZE(au1200_mmc1_resources),
 351         .resource       = au1200_mmc1_resources,
 352 };
 353 #endif /* #ifndef CONFIG_MIPS_DB1200 */
 354 #endif /* #ifdef CONFIG_SOC_AU1200 */
 355
 356 /* All Alchemy demoboards with I2C have this #define in their headers */
 357 #ifdef SMBUS_PSC_BASE
 358 static struct resource pbdb_smbus_resources[] = {
 359         {
 360                 .start  = CPHYSADDR(SMBUS_PSC_BASE),
 361                 .end    = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff),
 362                 .flags  = IORESOURCE_MEM,
 363         },
 364 };
 365
 366 static struct platform_device pbdb_smbus_device = {
 367         .name           = "au1xpsc_smbus",
 368         .id             = 0,    /* bus number */
 369         .num_resources  = ARRAY_SIZE(pbdb_smbus_resources),
 370         .resource       = pbdb_smbus_resources,
 371 };
 372 #endif
 373
 374 /* Macro to help defining the Ethernet MAC resources */
 375 #define MAC_RES(_base, _enable, _irq)                   \
 376         {                                               \
 377                 .start  = CPHYSADDR(_base),             \
 378                 .end    = CPHYSADDR(_base + 0xffff),    \
 379                 .flags  = IORESOURCE_MEM,               \
 380         },                                              \
 381         {                                               \
 382                 .start  = CPHYSADDR(_enable),           \
 383                 .end    = CPHYSADDR(_enable + 0x3),     \
 384                 .flags  = IORESOURCE_MEM,               \
 385         },                                              \
 386         {                                               \
 387                 .start  = _irq,                         \
 388                 .end    = _irq,                         \
 389                 .flags  = IORESOURCE_IRQ                \
 390         }
 391
 392 static struct resource au1xxx_eth0_resources[] = {
 393 #if defined(CONFIG_SOC_AU1000)
 394         MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT),
 395 #elif defined(CONFIG_SOC_AU1100)
 396         MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT),
 397 #elif defined(CONFIG_SOC_AU1550)
 398         MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT),
 399 #elif defined(CONFIG_SOC_AU1500)
 400         MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT),
 401 #endif
 402 };
 403
 404
 405 static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
 406         .phy1_search_mac0 = 1,
 407 };
 408
 409 static struct platform_device au1xxx_eth0_device = {
 410         .name           = "au1000-eth",
 411         .id             = 0,
 412         .num_resources  = ARRAY_SIZE(au1xxx_eth0_resources),
 413         .resource       = au1xxx_eth0_resources,
 414         .dev.platform_data = &au1xxx_eth0_platform_data,
 415 };
 416
 417 #ifndef CONFIG_SOC_AU1100
 418 static struct resource au1xxx_eth1_resources[] = {
 419 #if defined(CONFIG_SOC_AU1000)
 420         MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT),
 421 #elif defined(CONFIG_SOC_AU1550)
 422         MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT),
 423 #elif defined(CONFIG_SOC_AU1500)
 424         MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT),
 425 #endif
 426 };
 427
 428 static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
 429         .phy1_search_mac0 = 1,
 430 };
 431
 432 static struct platform_device au1xxx_eth1_device = {
 433         .name           = "au1000-eth",
 434         .id             = 1,
 435         .num_resources  = ARRAY_SIZE(au1xxx_eth1_resources),
 436         .resource       = au1xxx_eth1_resources,
 437         .dev.platform_data = &au1xxx_eth1_platform_data,
 438 };
 439 #endif
 440
 441 void __init au1xxx_override_eth_cfg(unsigned int port,
 442                         struct au1000_eth_platform_data *eth_data)
 443 {
 444         if (!eth_data || port > 1)
 445                 return;
 446
 447         if (port == 0)
 448                 memcpy(&au1xxx_eth0_platform_data, eth_data,
 449                         sizeof(struct au1000_eth_platform_data));
 450 #ifndef CONFIG_SOC_AU1100
 451         else
 452                 memcpy(&au1xxx_eth1_platform_data, eth_data,
 453                         sizeof(struct au1000_eth_platform_data));
 454 #endif
 455 }
 456
 457 static struct platform_device *au1xxx_platform_devices[] __initdata = {
 458         &au1xxx_usb_ohci_device,
 459 #ifdef CONFIG_FB_AU1100
 460         &au1100_lcd_device,
 461 #endif
 462 #ifdef CONFIG_SOC_AU1200
 463         &au1xxx_usb_ehci_device,
 464         &au1xxx_usb_gdt_device,
 465         &au1xxx_usb_otg_device,
 466         &au1200_lcd_device,
 467         &au1200_mmc0_device,
 468 #ifndef CONFIG_MIPS_DB1200
 469         &au1200_mmc1_device,
 470 #endif
 471 #endif
 472 #ifdef SMBUS_PSC_BASE
 473         &pbdb_smbus_device,
 474 #endif
 475         &au1xxx_eth0_device,
 476 };
 477
 478 static int __init au1xxx_platform_init(void)
 479 {
 480         int err, i, ctype = alchemy_get_cputype();
 481         unsigned char ethaddr[6];
 482
 483         alchemy_setup_uarts(ctype);
 484
 485         /* use firmware-provided mac addr if available and necessary */
 486         i = prom_get_ethernet_addr(ethaddr);
 487         if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
 488                 memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
 489
 490         err = platform_add_devices(au1xxx_platform_devices,
 491                                    ARRAY_SIZE(au1xxx_platform_devices));
 492 #ifndef CONFIG_SOC_AU1100
 493         ethaddr[5] += 1;        /* next addr for 2nd MAC */
 494         if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
 495                 memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
 496
 497         /* Register second MAC if enabled in pinfunc */
 498         if (!err && !(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2))
 499                 err = platform_device_register(&au1xxx_eth1_device);
 500 #endif
 501
 502         return err;
 503 }
 504
 505 arch_initcall(au1xxx_platform_init);