arch/arm/plat-omap/include/plat/dmtimer.h

   1 /*
   2  * arch/arm/plat-omap/include/plat/dmtimer.h
   3  *
   4  * OMAP Dual-Mode Timers
   5  *
   6  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
   7  * Tarun Kanti DebBarma <tarun.kanti@ti.com>
   8  * Thara Gopinath <thara@ti.com>
   9  *
  10  * Platform device conversion and hwmod support.
  11  *
  12  * Copyright (C) 2005 Nokia Corporation
  13  * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
  14  * PWM and clock framwork support by Timo Teras.
  15  *
  16  * This program is free software; you can redistribute it and/or modify it
  17  * under the terms of the GNU General Public License as published by the
  18  * Free Software Foundation; either version 2 of the License, or (at your
  19  * option) any later version.
  20  *
  21  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  22  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  24  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29  *
  30  * You should have received a copy of the  GNU General Public License along
  31  * with this program; if not, write  to the Free Software Foundation, Inc.,
  32  * 675 Mass Ave, Cambridge, MA 02139, USA.
  33  */
  34
  35 #include <linux/clk.h>
  36 #include <linux/delay.h>
  37 #include <linux/io.h>
  38 #include <linux/platform_device.h>
  39
  40 #ifndef __ASM_ARCH_DMTIMER_H
  41 #define __ASM_ARCH_DMTIMER_H
  42
  43 /* clock sources */
  44 #define OMAP_TIMER_SRC_SYS_CLK                  0x00
  45 #define OMAP_TIMER_SRC_32_KHZ                   0x01
  46 #define OMAP_TIMER_SRC_EXT_CLK                  0x02
  47
  48 /* timer interrupt enable bits */
  49 #define OMAP_TIMER_INT_CAPTURE                  (1 << 2)
  50 #define OMAP_TIMER_INT_OVERFLOW                 (1 << 1)
  51 #define OMAP_TIMER_INT_MATCH                    (1 << 0)
  52
  53 /* trigger types */
  54 #define OMAP_TIMER_TRIGGER_NONE                 0x00
  55 #define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
  56 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
  57
  58 /* timer capabilities used in hwmod database */
  59 #define OMAP_TIMER_SECURE                               0x80000000
  60 #define OMAP_TIMER_ALWON                                0x40000000
  61 #define OMAP_TIMER_HAS_PWM                              0x20000000
  62 #define OMAP_TIMER_NEEDS_RESET                          0x10000000
  63
  64 struct omap_timer_capability_dev_attr {
  65         u32 timer_capability;
  66 };
  67
  68 struct omap_dm_timer;
  69
  70 struct timer_regs {
  71         u32 tidr;
  72         u32 tistat;
  73         u32 tisr;
  74         u32 tier;
  75         u32 twer;
  76         u32 tclr;
  77         u32 tcrr;
  78         u32 tldr;
  79         u32 ttrg;
  80         u32 twps;
  81         u32 tmar;
  82         u32 tcar1;
  83         u32 tsicr;
  84         u32 tcar2;
  85         u32 tpir;
  86         u32 tnir;
  87         u32 tcvr;
  88         u32 tocr;
  89         u32 towr;
  90 };
  91
  92 struct dmtimer_platform_data {
  93         /* set_timer_src - Only used for OMAP1 devices */
  94         int (*set_timer_src)(struct platform_device *pdev, int source);
  95         u32 timer_capability;
  96 };
  97
  98 int omap_dm_timer_reserve_systimer(int id);
  99 struct omap_dm_timer *omap_dm_timer_request(void);
 100 struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
 101 int omap_dm_timer_free(struct omap_dm_timer *timer);
 102 void omap_dm_timer_enable(struct omap_dm_timer *timer);
 103 void omap_dm_timer_disable(struct omap_dm_timer *timer);
 104
 105 int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
 106
 107 u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
 108 struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
 109
 110 int omap_dm_timer_trigger(struct omap_dm_timer *timer);
 111 int omap_dm_timer_start(struct omap_dm_timer *timer);
 112 int omap_dm_timer_stop(struct omap_dm_timer *timer);
 113
 114 int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
 115 int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
 116 int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
 117 int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
 118 int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
 119 int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
 120
 121 int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
 122
 123 unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
 124 int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
 125 unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
 126 int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
 127
 128 int omap_dm_timers_active(void);
 129
 130 /*
 131  * Do not use the defines below, they are not needed. They should be only
 132  * used by dmtimer.c and sys_timer related code.
 133  */
 134
 135 /*
 136  * The interrupt registers are different between v1 and v2 ip.
 137  * These registers are offsets from timer->iobase.
 138  */
 139 #define OMAP_TIMER_ID_OFFSET            0x00
 140 #define OMAP_TIMER_OCP_CFG_OFFSET       0x10
 141
 142 #define OMAP_TIMER_V1_SYS_STAT_OFFSET   0x14
 143 #define OMAP_TIMER_V1_STAT_OFFSET       0x18
 144 #define OMAP_TIMER_V1_INT_EN_OFFSET     0x1c
 145
 146 #define OMAP_TIMER_V2_IRQSTATUS_RAW     0x24
 147 #define OMAP_TIMER_V2_IRQSTATUS         0x28
 148 #define OMAP_TIMER_V2_IRQENABLE_SET     0x2c
 149 #define OMAP_TIMER_V2_IRQENABLE_CLR     0x30
 150
 151 /*
 152  * The functional registers have a different base on v1 and v2 ip.
 153  * These registers are offsets from timer->func_base. The func_base
 154  * is samae as io_base for v1 and io_base + 0x14 for v2 ip.
 155  *
 156  */
 157 #define OMAP_TIMER_V2_FUNC_OFFSET               0x14
 158
 159 #define _OMAP_TIMER_WAKEUP_EN_OFFSET    0x20
 160 #define _OMAP_TIMER_CTRL_OFFSET         0x24
 161 #define         OMAP_TIMER_CTRL_GPOCFG          (1 << 14)
 162 #define         OMAP_TIMER_CTRL_CAPTMODE        (1 << 13)
 163 #define         OMAP_TIMER_CTRL_PT              (1 << 12)
 164 #define         OMAP_TIMER_CTRL_TCM_LOWTOHIGH   (0x1 << 8)
 165 #define         OMAP_TIMER_CTRL_TCM_HIGHTOLOW   (0x2 << 8)
 166 #define         OMAP_TIMER_CTRL_TCM_BOTHEDGES   (0x3 << 8)
 167 #define         OMAP_TIMER_CTRL_SCPWM           (1 << 7)
 168 #define         OMAP_TIMER_CTRL_CE              (1 << 6) /* compare enable */
 169 #define         OMAP_TIMER_CTRL_PRE             (1 << 5) /* prescaler enable */
 170 #define         OMAP_TIMER_CTRL_PTV_SHIFT       2 /* prescaler value shift */
 171 #define         OMAP_TIMER_CTRL_POSTED          (1 << 2)
 172 #define         OMAP_TIMER_CTRL_AR              (1 << 1) /* auto-reload enable */
 173 #define         OMAP_TIMER_CTRL_ST              (1 << 0) /* start timer */
 174 #define _OMAP_TIMER_COUNTER_OFFSET      0x28
 175 #define _OMAP_TIMER_LOAD_OFFSET         0x2c
 176 #define _OMAP_TIMER_TRIGGER_OFFSET      0x30
 177 #define _OMAP_TIMER_WRITE_PEND_OFFSET   0x34
 178 #define         WP_NONE                 0       /* no write pending bit */
 179 #define         WP_TCLR                 (1 << 0)
 180 #define         WP_TCRR                 (1 << 1)
 181 #define         WP_TLDR                 (1 << 2)
 182 #define         WP_TTGR                 (1 << 3)
 183 #define         WP_TMAR                 (1 << 4)
 184 #define         WP_TPIR                 (1 << 5)
 185 #define         WP_TNIR                 (1 << 6)
 186 #define         WP_TCVR                 (1 << 7)
 187 #define         WP_TOCR                 (1 << 8)
 188 #define         WP_TOWR                 (1 << 9)
 189 #define _OMAP_TIMER_MATCH_OFFSET        0x38
 190 #define _OMAP_TIMER_CAPTURE_OFFSET      0x3c
 191 #define _OMAP_TIMER_IF_CTRL_OFFSET      0x40
 192 #define _OMAP_TIMER_CAPTURE2_OFFSET             0x44    /* TCAR2, 34xx only */
 193 #define _OMAP_TIMER_TICK_POS_OFFSET             0x48    /* TPIR, 34xx only */
 194 #define _OMAP_TIMER_TICK_NEG_OFFSET             0x4c    /* TNIR, 34xx only */
 195 #define _OMAP_TIMER_TICK_COUNT_OFFSET           0x50    /* TCVR, 34xx only */
 196 #define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET    0x54    /* TOCR, 34xx only */
 197 #define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET  0x58    /* TOWR, 34xx only */
 198
 199 /* register offsets with the write pending bit encoded */
 200 #define WPSHIFT                                 16
 201
 202 #define OMAP_TIMER_WAKEUP_EN_REG                (_OMAP_TIMER_WAKEUP_EN_OFFSET \
 203                                                         | (WP_NONE << WPSHIFT))
 204
 205 #define OMAP_TIMER_CTRL_REG                     (_OMAP_TIMER_CTRL_OFFSET \
 206                                                         | (WP_TCLR << WPSHIFT))
 207
 208 #define OMAP_TIMER_COUNTER_REG                  (_OMAP_TIMER_COUNTER_OFFSET \
 209                                                         | (WP_TCRR << WPSHIFT))
 210
 211 #define OMAP_TIMER_LOAD_REG                     (_OMAP_TIMER_LOAD_OFFSET \
 212                                                         | (WP_TLDR << WPSHIFT))
 213
 214 #define OMAP_TIMER_TRIGGER_REG                  (_OMAP_TIMER_TRIGGER_OFFSET \
 215                                                         | (WP_TTGR << WPSHIFT))
 216
 217 #define OMAP_TIMER_WRITE_PEND_REG               (_OMAP_TIMER_WRITE_PEND_OFFSET \
 218                                                         | (WP_NONE << WPSHIFT))
 219
 220 #define OMAP_TIMER_MATCH_REG                    (_OMAP_TIMER_MATCH_OFFSET \
 221                                                         | (WP_TMAR << WPSHIFT))
 222
 223 #define OMAP_TIMER_CAPTURE_REG                  (_OMAP_TIMER_CAPTURE_OFFSET \
 224                                                         | (WP_NONE << WPSHIFT))
 225
 226 #define OMAP_TIMER_IF_CTRL_REG                  (_OMAP_TIMER_IF_CTRL_OFFSET \
 227                                                         | (WP_NONE << WPSHIFT))
 228
 229 #define OMAP_TIMER_CAPTURE2_REG                 (_OMAP_TIMER_CAPTURE2_OFFSET \
 230                                                         | (WP_NONE << WPSHIFT))
 231
 232 #define OMAP_TIMER_TICK_POS_REG                 (_OMAP_TIMER_TICK_POS_OFFSET \
 233                                                         | (WP_TPIR << WPSHIFT))
 234
 235 #define OMAP_TIMER_TICK_NEG_REG                 (_OMAP_TIMER_TICK_NEG_OFFSET \
 236                                                         | (WP_TNIR << WPSHIFT))
 237
 238 #define OMAP_TIMER_TICK_COUNT_REG               (_OMAP_TIMER_TICK_COUNT_OFFSET \
 239                                                         | (WP_TCVR << WPSHIFT))
 240
 241 #define OMAP_TIMER_TICK_INT_MASK_SET_REG                                \
 242                 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
 243
 244 #define OMAP_TIMER_TICK_INT_MASK_COUNT_REG                              \
 245                 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
 246
 247 struct omap_dm_timer {
 248         unsigned long phys_base;
 249         int id;
 250         int irq;
 251         struct clk *fclk;
 252
 253         void __iomem    *io_base;
 254         void __iomem    *sys_stat;      /* TISTAT timer status */
 255         void __iomem    *irq_stat;      /* TISR/IRQSTATUS interrupt status */
 256         void __iomem    *irq_ena;       /* irq enable */
 257         void __iomem    *irq_dis;       /* irq disable, only on v2 ip */
 258         void __iomem    *pend;          /* write pending */
 259         void __iomem    *func_base;     /* function register base */
 260
 261         unsigned long rate;
 262         unsigned reserved:1;
 263         unsigned posted:1;
 264         struct timer_regs context;
 265         int ctx_loss_count;
 266         int revision;
 267         u32 capability;
 268         struct platform_device *pdev;
 269         struct list_head node;
 270 };
 271
 272 int omap_dm_timer_prepare(struct omap_dm_timer *timer);
 273
 274 static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
 275                                                 int posted)
 276 {
 277         if (posted)
 278                 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
 279                         cpu_relax();
 280
 281         return __raw_readl(timer->func_base + (reg & 0xff));
 282 }
 283
 284 static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
 285                                         u32 reg, u32 val, int posted)
 286 {
 287         if (posted)
 288                 while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
 289                         cpu_relax();
 290
 291         __raw_writel(val, timer->func_base + (reg & 0xff));
 292 }
 293
 294 static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
 295 {
 296         u32 tidr;
 297
 298         /* Assume v1 ip if bits [31:16] are zero */
 299         tidr = __raw_readl(timer->io_base);
 300         if (!(tidr >> 16)) {
 301                 timer->revision = 1;
 302                 timer->sys_stat = timer->io_base +
 303                                 OMAP_TIMER_V1_SYS_STAT_OFFSET;
 304                 timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
 305                 timer->irq_ena = timer->io_base + OMAP_TIMER_V1_INT_EN_OFFSET;
 306                 timer->irq_dis = NULL;
 307                 timer->pend = timer->io_base + _OMAP_TIMER_WRITE_PEND_OFFSET;
 308                 timer->func_base = timer->io_base;
 309         } else {
 310                 timer->revision = 2;
 311                 timer->sys_stat = NULL;
 312                 timer->irq_stat = timer->io_base + OMAP_TIMER_V2_IRQSTATUS;
 313                 timer->irq_ena = timer->io_base + OMAP_TIMER_V2_IRQENABLE_SET;
 314                 timer->irq_dis = timer->io_base + OMAP_TIMER_V2_IRQENABLE_CLR;
 315                 timer->pend = timer->io_base +
 316                         _OMAP_TIMER_WRITE_PEND_OFFSET +
 317                                 OMAP_TIMER_V2_FUNC_OFFSET;
 318                 timer->func_base = timer->io_base + OMAP_TIMER_V2_FUNC_OFFSET;
 319         }
 320 }
 321
 322 /* Assumes the source clock has been set by caller */
 323 static inline void __omap_dm_timer_reset(struct omap_dm_timer *timer,
 324                                         int autoidle, int wakeup)
 325 {
 326         u32 l;
 327
 328         l = __raw_readl(timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
 329         l |= 0x02 << 3;  /* Set to smart-idle mode */
 330         l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
 331
 332         if (autoidle)
 333                 l |= 0x1 << 0;
 334
 335         if (wakeup)
 336                 l |= 1 << 2;
 337
 338         __raw_writel(l, timer->io_base + OMAP_TIMER_OCP_CFG_OFFSET);
 339
 340         /* Match hardware reset default of posted mode */
 341         __omap_dm_timer_write(timer, OMAP_TIMER_IF_CTRL_REG,
 342                                         OMAP_TIMER_CTRL_POSTED, 0);
 343 }
 344
 345 static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
 346                                                 struct clk *parent)
 347 {
 348         int ret;
 349
 350         clk_disable(timer_fck);
 351         ret = clk_set_parent(timer_fck, parent);
 352         clk_enable(timer_fck);
 353
 354         /*
 355          * When the functional clock disappears, too quick writes seem
 356          * to cause an abort. XXX Is this still necessary?
 357          */
 358         __delay(300000);
 359
 360         return ret;
 361 }
 362
 363 static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
 364                                         int posted, unsigned long rate)
 365 {
 366         u32 l;
 367
 368         l = __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
 369         if (l & OMAP_TIMER_CTRL_ST) {
 370                 l &= ~0x1;
 371                 __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, l, posted);
 372 #ifdef CONFIG_ARCH_OMAP2PLUS
 373                 /* Readback to make sure write has completed */
 374                 __omap_dm_timer_read(timer, OMAP_TIMER_CTRL_REG, posted);
 375                 /*
 376                  * Wait for functional clock period x 3.5 to make sure that
 377                  * timer is stopped
 378                  */
 379                 udelay(3500000 / rate + 1);
 380 #endif
 381         }
 382
 383         /* Ack possibly pending interrupt */
 384         __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
 385 }
 386
 387 static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
 388                                                 u32 ctrl, unsigned int load,
 389                                                 int posted)
 390 {
 391         __omap_dm_timer_write(timer, OMAP_TIMER_COUNTER_REG, load, posted);
 392         __omap_dm_timer_write(timer, OMAP_TIMER_CTRL_REG, ctrl, posted);
 393 }
 394
 395 static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
 396                                                 unsigned int value)
 397 {
 398         __raw_writel(value, timer->irq_ena);
 399         __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
 400 }
 401
 402 static inline unsigned int
 403 __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
 404 {
 405         return __omap_dm_timer_read(timer, OMAP_TIMER_COUNTER_REG, posted);
 406 }
 407
 408 static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
 409                                                 unsigned int value)
 410 {
 411         __raw_writel(value, timer->irq_stat);
 412 }
 413
 414 #endif /* __ASM_ARCH_DMTIMER_H */