1 /* linux/arch/arm/mach-s5pv210/clock.c
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
6 * S5PV210 - Clock support
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/errno.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/sysdev.h>
25 #include <plat/cpu-freq.h>
26 #include <mach/regs-clock.h>
27 #include <plat/clock.h>
30 #include <plat/s5p-clock.h>
31 #include <plat/clock-clksrc.h>
32 #include <plat/s5pv210.h>
34 static unsigned long xtal;
36 static struct clksrc_clk clk_mout_apll = {
40 .sources = &clk_src_apll,
41 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
44 static struct clksrc_clk clk_mout_epll = {
48 .sources = &clk_src_epll,
49 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
52 static struct clksrc_clk clk_mout_mpll = {
56 .sources = &clk_src_mpll,
57 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
60 static struct clk *clkset_armclk_list[] = {
61 [0] = &clk_mout_apll.clk,
62 [1] = &clk_mout_mpll.clk,
65 static struct clksrc_sources clkset_armclk = {
66 .sources = clkset_armclk_list,
67 .nr_sources = ARRAY_SIZE(clkset_armclk_list),
70 static struct clksrc_clk clk_armclk = {
74 .sources = &clkset_armclk,
75 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
76 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 3 },
79 static struct clksrc_clk clk_hclk_msys = {
82 .parent = &clk_armclk.clk,
84 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
87 static struct clksrc_clk clk_pclk_msys = {
90 .parent = &clk_hclk_msys.clk,
92 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
95 static struct clksrc_clk clk_sclk_a2m = {
98 .parent = &clk_mout_apll.clk,
100 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
103 static struct clk *clkset_hclk_sys_list[] = {
104 [0] = &clk_mout_mpll.clk,
105 [1] = &clk_sclk_a2m.clk,
108 static struct clksrc_sources clkset_hclk_sys = {
109 .sources = clkset_hclk_sys_list,
110 .nr_sources = ARRAY_SIZE(clkset_hclk_sys_list),
113 static struct clksrc_clk clk_hclk_dsys = {
117 .sources = &clkset_hclk_sys,
118 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
119 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 4 },
122 static struct clksrc_clk clk_pclk_dsys = {
125 .parent = &clk_hclk_dsys.clk,
127 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
130 static struct clksrc_clk clk_hclk_psys = {
134 .sources = &clkset_hclk_sys,
135 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
136 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 24, .size = 4 },
139 static struct clksrc_clk clk_pclk_psys = {
142 .parent = &clk_hclk_psys.clk,
144 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
147 static int s5pv210_clk_ip0_ctrl(struct clk *clk, int enable)
149 return s5p_gatectrl(S5P_CLKGATE_IP0, clk, enable);
152 static int s5pv210_clk_ip1_ctrl(struct clk *clk, int enable)
154 return s5p_gatectrl(S5P_CLKGATE_IP1, clk, enable);
157 static int s5pv210_clk_ip2_ctrl(struct clk *clk, int enable)
159 return s5p_gatectrl(S5P_CLKGATE_IP2, clk, enable);
162 static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
164 return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
167 static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
169 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
172 static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
174 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
177 static struct clk clk_sclk_hdmi27m = {
178 .name = "sclk_hdmi27m",
182 static struct clk clk_sclk_hdmiphy = {
183 .name = "sclk_hdmiphy",
186 static struct clk clk_sclk_usbphy0 = {
187 .name = "sclk_usbphy0",
190 static struct clk clk_sclk_usbphy1 = {
191 .name = "sclk_usbphy1",
194 static struct clk clk_pcmcdclk0 = {
198 static struct clk clk_pcmcdclk1 = {
202 static struct clk clk_pcmcdclk2 = {
206 static struct clk dummy_apb_pclk = {
211 static struct clk *clkset_vpllsrc_list[] = {
213 [1] = &clk_sclk_hdmi27m,
216 static struct clksrc_sources clkset_vpllsrc = {
217 .sources = clkset_vpllsrc_list,
218 .nr_sources = ARRAY_SIZE(clkset_vpllsrc_list),
221 static struct clksrc_clk clk_vpllsrc = {
224 .enable = s5pv210_clk_mask0_ctrl,
227 .sources = &clkset_vpllsrc,
228 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 28, .size = 1 },
231 static struct clk *clkset_sclk_vpll_list[] = {
232 [0] = &clk_vpllsrc.clk,
233 [1] = &clk_fout_vpll,
236 static struct clksrc_sources clkset_sclk_vpll = {
237 .sources = clkset_sclk_vpll_list,
238 .nr_sources = ARRAY_SIZE(clkset_sclk_vpll_list),
241 static struct clksrc_clk clk_sclk_vpll = {
245 .sources = &clkset_sclk_vpll,
246 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
249 static struct clk *clkset_moutdmc0src_list[] = {
250 [0] = &clk_sclk_a2m.clk,
251 [1] = &clk_mout_mpll.clk,
256 static struct clksrc_sources clkset_moutdmc0src = {
257 .sources = clkset_moutdmc0src_list,
258 .nr_sources = ARRAY_SIZE(clkset_moutdmc0src_list),
261 static struct clksrc_clk clk_mout_dmc0 = {
265 .sources = &clkset_moutdmc0src,
266 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
269 static struct clksrc_clk clk_sclk_dmc0 = {
272 .parent = &clk_mout_dmc0.clk,
274 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
277 static unsigned long s5pv210_clk_imem_get_rate(struct clk *clk)
279 return clk_get_rate(clk->parent) / 2;
282 static struct clk_ops clk_hclk_imem_ops = {
283 .get_rate = s5pv210_clk_imem_get_rate,
286 static unsigned long s5pv210_clk_fout_apll_get_rate(struct clk *clk)
288 return s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
291 static struct clk_ops clk_fout_apll_ops = {
292 .get_rate = s5pv210_clk_fout_apll_get_rate,
295 static struct clk init_clocks_off[] = {
298 .devname = "s3c-pl330.0",
299 .parent = &clk_hclk_psys.clk,
300 .enable = s5pv210_clk_ip0_ctrl,
304 .devname = "s3c-pl330.1",
305 .parent = &clk_hclk_psys.clk,
306 .enable = s5pv210_clk_ip0_ctrl,
310 .parent = &clk_hclk_dsys.clk,
311 .enable = s5pv210_clk_ip0_ctrl,
315 .devname = "s5pv210-fimc.0",
316 .parent = &clk_hclk_dsys.clk,
317 .enable = s5pv210_clk_ip0_ctrl,
318 .ctrlbit = (1 << 24),
321 .devname = "s5pv210-fimc.1",
322 .parent = &clk_hclk_dsys.clk,
323 .enable = s5pv210_clk_ip0_ctrl,
324 .ctrlbit = (1 << 25),
327 .devname = "s5pv210-fimc.2",
328 .parent = &clk_hclk_dsys.clk,
329 .enable = s5pv210_clk_ip0_ctrl,
330 .ctrlbit = (1 << 26),
333 .devname = "s5p-mfc",
334 .parent = &clk_pclk_psys.clk,
335 .enable = s5pv210_clk_ip0_ctrl,
336 .ctrlbit = (1 << 16),
339 .parent = &clk_hclk_psys.clk,
340 .enable = s5pv210_clk_ip1_ctrl,
344 .parent = &clk_hclk_psys.clk,
345 .enable = s5pv210_clk_ip1_ctrl,
349 .parent = &clk_hclk_dsys.clk,
350 .enable = s5pv210_clk_ip1_ctrl,
354 .parent = &clk_hclk_psys.clk,
355 .enable = s5pv210_clk_ip1_ctrl,
359 .devname = "s3c-sdhci.0",
360 .parent = &clk_hclk_psys.clk,
361 .enable = s5pv210_clk_ip2_ctrl,
365 .devname = "s3c-sdhci.1",
366 .parent = &clk_hclk_psys.clk,
367 .enable = s5pv210_clk_ip2_ctrl,
371 .devname = "s3c-sdhci.2",
372 .parent = &clk_hclk_psys.clk,
373 .enable = s5pv210_clk_ip2_ctrl,
377 .devname = "s3c-sdhci.3",
378 .parent = &clk_hclk_psys.clk,
379 .enable = s5pv210_clk_ip2_ctrl,
383 .parent = &clk_pclk_psys.clk,
384 .enable = s5pv210_clk_ip3_ctrl,
388 .parent = &clk_pclk_psys.clk,
389 .enable = s5pv210_clk_ip3_ctrl,
393 .parent = &clk_pclk_psys.clk,
394 .enable = s5pv210_clk_ip3_ctrl,
398 .devname = "s3c2440-i2c.0",
399 .parent = &clk_pclk_psys.clk,
400 .enable = s5pv210_clk_ip3_ctrl,
404 .devname = "s3c2440-i2c.1",
405 .parent = &clk_pclk_psys.clk,
406 .enable = s5pv210_clk_ip3_ctrl,
407 .ctrlbit = (1 << 10),
410 .devname = "s3c2440-i2c.2",
411 .parent = &clk_pclk_psys.clk,
412 .enable = s5pv210_clk_ip3_ctrl,
416 .devname = "s3c64xx-spi.0",
417 .parent = &clk_pclk_psys.clk,
418 .enable = s5pv210_clk_ip3_ctrl,
422 .devname = "s3c64xx-spi.1",
423 .parent = &clk_pclk_psys.clk,
424 .enable = s5pv210_clk_ip3_ctrl,
428 .devname = "s3c64xx-spi.2",
429 .parent = &clk_pclk_psys.clk,
430 .enable = s5pv210_clk_ip3_ctrl,
434 .parent = &clk_pclk_psys.clk,
435 .enable = s5pv210_clk_ip3_ctrl,
439 .parent = &clk_pclk_psys.clk,
440 .enable = s5pv210_clk_ip3_ctrl,
444 .parent = &clk_pclk_psys.clk,
445 .enable = s5pv210_clk_ip3_ctrl,
449 .devname = "samsung-i2s.0",
451 .enable = s5pv210_clk_ip3_ctrl,
455 .devname = "samsung-i2s.1",
457 .enable = s5pv210_clk_ip3_ctrl,
461 .devname = "samsung-i2s.2",
463 .enable = s5pv210_clk_ip3_ctrl,
468 .enable = s5pv210_clk_ip3_ctrl,
473 static struct clk init_clocks[] = {
476 .parent = &clk_hclk_msys.clk,
478 .enable = s5pv210_clk_ip0_ctrl,
479 .ops = &clk_hclk_imem_ops,
482 .devname = "s5pv210-uart.0",
483 .parent = &clk_pclk_psys.clk,
484 .enable = s5pv210_clk_ip3_ctrl,
485 .ctrlbit = (1 << 17),
488 .devname = "s5pv210-uart.1",
489 .parent = &clk_pclk_psys.clk,
490 .enable = s5pv210_clk_ip3_ctrl,
491 .ctrlbit = (1 << 18),
494 .devname = "s5pv210-uart.2",
495 .parent = &clk_pclk_psys.clk,
496 .enable = s5pv210_clk_ip3_ctrl,
497 .ctrlbit = (1 << 19),
500 .devname = "s5pv210-uart.3",
501 .parent = &clk_pclk_psys.clk,
502 .enable = s5pv210_clk_ip3_ctrl,
503 .ctrlbit = (1 << 20),
506 .parent = &clk_hclk_psys.clk,
507 .enable = s5pv210_clk_ip1_ctrl,
508 .ctrlbit = (1 << 26),
512 static struct clk *clkset_uart_list[] = {
513 [6] = &clk_mout_mpll.clk,
514 [7] = &clk_mout_epll.clk,
517 static struct clksrc_sources clkset_uart = {
518 .sources = clkset_uart_list,
519 .nr_sources = ARRAY_SIZE(clkset_uart_list),
522 static struct clk *clkset_group1_list[] = {
523 [0] = &clk_sclk_a2m.clk,
524 [1] = &clk_mout_mpll.clk,
525 [2] = &clk_mout_epll.clk,
526 [3] = &clk_sclk_vpll.clk,
529 static struct clksrc_sources clkset_group1 = {
530 .sources = clkset_group1_list,
531 .nr_sources = ARRAY_SIZE(clkset_group1_list),
534 static struct clk *clkset_sclk_onenand_list[] = {
535 [0] = &clk_hclk_psys.clk,
536 [1] = &clk_hclk_dsys.clk,
539 static struct clksrc_sources clkset_sclk_onenand = {
540 .sources = clkset_sclk_onenand_list,
541 .nr_sources = ARRAY_SIZE(clkset_sclk_onenand_list),
544 static struct clk *clkset_sclk_dac_list[] = {
545 [0] = &clk_sclk_vpll.clk,
546 [1] = &clk_sclk_hdmiphy,
549 static struct clksrc_sources clkset_sclk_dac = {
550 .sources = clkset_sclk_dac_list,
551 .nr_sources = ARRAY_SIZE(clkset_sclk_dac_list),
554 static struct clksrc_clk clk_sclk_dac = {
557 .enable = s5pv210_clk_mask0_ctrl,
560 .sources = &clkset_sclk_dac,
561 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
564 static struct clksrc_clk clk_sclk_pixel = {
566 .name = "sclk_pixel",
567 .parent = &clk_sclk_vpll.clk,
569 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
572 static struct clk *clkset_sclk_hdmi_list[] = {
573 [0] = &clk_sclk_pixel.clk,
574 [1] = &clk_sclk_hdmiphy,
577 static struct clksrc_sources clkset_sclk_hdmi = {
578 .sources = clkset_sclk_hdmi_list,
579 .nr_sources = ARRAY_SIZE(clkset_sclk_hdmi_list),
582 static struct clksrc_clk clk_sclk_hdmi = {
585 .enable = s5pv210_clk_mask0_ctrl,
588 .sources = &clkset_sclk_hdmi,
589 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
592 static struct clk *clkset_sclk_mixer_list[] = {
593 [0] = &clk_sclk_dac.clk,
594 [1] = &clk_sclk_hdmi.clk,
597 static struct clksrc_sources clkset_sclk_mixer = {
598 .sources = clkset_sclk_mixer_list,
599 .nr_sources = ARRAY_SIZE(clkset_sclk_mixer_list),
602 static struct clk *clkset_sclk_audio0_list[] = {
603 [0] = &clk_ext_xtal_mux,
604 [1] = &clk_pcmcdclk0,
605 [2] = &clk_sclk_hdmi27m,
606 [3] = &clk_sclk_usbphy0,
607 [4] = &clk_sclk_usbphy1,
608 [5] = &clk_sclk_hdmiphy,
609 [6] = &clk_mout_mpll.clk,
610 [7] = &clk_mout_epll.clk,
611 [8] = &clk_sclk_vpll.clk,
614 static struct clksrc_sources clkset_sclk_audio0 = {
615 .sources = clkset_sclk_audio0_list,
616 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
619 static struct clksrc_clk clk_sclk_audio0 = {
621 .name = "sclk_audio",
622 .devname = "soc-audio.0",
623 .enable = s5pv210_clk_mask0_ctrl,
624 .ctrlbit = (1 << 24),
626 .sources = &clkset_sclk_audio0,
627 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
628 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 0, .size = 4 },
631 static struct clk *clkset_sclk_audio1_list[] = {
632 [0] = &clk_ext_xtal_mux,
633 [1] = &clk_pcmcdclk1,
634 [2] = &clk_sclk_hdmi27m,
635 [3] = &clk_sclk_usbphy0,
636 [4] = &clk_sclk_usbphy1,
637 [5] = &clk_sclk_hdmiphy,
638 [6] = &clk_mout_mpll.clk,
639 [7] = &clk_mout_epll.clk,
640 [8] = &clk_sclk_vpll.clk,
643 static struct clksrc_sources clkset_sclk_audio1 = {
644 .sources = clkset_sclk_audio1_list,
645 .nr_sources = ARRAY_SIZE(clkset_sclk_audio1_list),
648 static struct clksrc_clk clk_sclk_audio1 = {
650 .name = "sclk_audio",
651 .devname = "soc-audio.1",
652 .enable = s5pv210_clk_mask0_ctrl,
653 .ctrlbit = (1 << 25),
655 .sources = &clkset_sclk_audio1,
656 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
657 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 4, .size = 4 },
660 static struct clk *clkset_sclk_audio2_list[] = {
661 [0] = &clk_ext_xtal_mux,
662 [1] = &clk_pcmcdclk0,
663 [2] = &clk_sclk_hdmi27m,
664 [3] = &clk_sclk_usbphy0,
665 [4] = &clk_sclk_usbphy1,
666 [5] = &clk_sclk_hdmiphy,
667 [6] = &clk_mout_mpll.clk,
668 [7] = &clk_mout_epll.clk,
669 [8] = &clk_sclk_vpll.clk,
672 static struct clksrc_sources clkset_sclk_audio2 = {
673 .sources = clkset_sclk_audio2_list,
674 .nr_sources = ARRAY_SIZE(clkset_sclk_audio2_list),
677 static struct clksrc_clk clk_sclk_audio2 = {
679 .name = "sclk_audio",
680 .devname = "soc-audio.2",
681 .enable = s5pv210_clk_mask0_ctrl,
682 .ctrlbit = (1 << 26),
684 .sources = &clkset_sclk_audio2,
685 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
686 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 8, .size = 4 },
689 static struct clk *clkset_sclk_spdif_list[] = {
690 [0] = &clk_sclk_audio0.clk,
691 [1] = &clk_sclk_audio1.clk,
692 [2] = &clk_sclk_audio2.clk,
695 static struct clksrc_sources clkset_sclk_spdif = {
696 .sources = clkset_sclk_spdif_list,
697 .nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
700 static struct clksrc_clk clk_sclk_spdif = {
702 .name = "sclk_spdif",
703 .enable = s5pv210_clk_mask0_ctrl,
704 .ctrlbit = (1 << 27),
705 .ops = &s5p_sclk_spdif_ops,
707 .sources = &clkset_sclk_spdif,
708 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
711 static struct clk *clkset_group2_list[] = {
712 [0] = &clk_ext_xtal_mux,
714 [2] = &clk_sclk_hdmi27m,
715 [3] = &clk_sclk_usbphy0,
716 [4] = &clk_sclk_usbphy1,
717 [5] = &clk_sclk_hdmiphy,
718 [6] = &clk_mout_mpll.clk,
719 [7] = &clk_mout_epll.clk,
720 [8] = &clk_sclk_vpll.clk,
723 static struct clksrc_sources clkset_group2 = {
724 .sources = clkset_group2_list,
725 .nr_sources = ARRAY_SIZE(clkset_group2_list),
728 static struct clksrc_clk clksrcs[] = {
733 .sources = &clkset_group1,
734 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
735 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
738 .name = "sclk_onenand",
740 .sources = &clkset_sclk_onenand,
741 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
742 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 12, .size = 3 },
746 .devname = "s5pv210-uart.0",
747 .enable = s5pv210_clk_mask0_ctrl,
748 .ctrlbit = (1 << 12),
750 .sources = &clkset_uart,
751 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
752 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
756 .devname = "s5pv210-uart.1",
757 .enable = s5pv210_clk_mask0_ctrl,
758 .ctrlbit = (1 << 13),
760 .sources = &clkset_uart,
761 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
762 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
766 .devname = "s5pv210-uart.2",
767 .enable = s5pv210_clk_mask0_ctrl,
768 .ctrlbit = (1 << 14),
770 .sources = &clkset_uart,
771 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
772 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
776 .devname = "s5pv210-uart.3",
777 .enable = s5pv210_clk_mask0_ctrl,
778 .ctrlbit = (1 << 15),
780 .sources = &clkset_uart,
781 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
782 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
785 .name = "sclk_mixer",
786 .enable = s5pv210_clk_mask0_ctrl,
789 .sources = &clkset_sclk_mixer,
790 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
794 .devname = "s5pv210-fimc.0",
795 .enable = s5pv210_clk_mask1_ctrl,
798 .sources = &clkset_group2,
799 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
800 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
804 .devname = "s5pv210-fimc.1",
805 .enable = s5pv210_clk_mask1_ctrl,
808 .sources = &clkset_group2,
809 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
810 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
814 .devname = "s5pv210-fimc.2",
815 .enable = s5pv210_clk_mask1_ctrl,
818 .sources = &clkset_group2,
819 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
820 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
824 .enable = s5pv210_clk_mask0_ctrl,
827 .sources = &clkset_group2,
828 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
829 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
833 .enable = s5pv210_clk_mask0_ctrl,
836 .sources = &clkset_group2,
837 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
838 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
842 .enable = s5pv210_clk_mask0_ctrl,
845 .sources = &clkset_group2,
846 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
847 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
851 .devname = "s3c-sdhci.0",
852 .enable = s5pv210_clk_mask0_ctrl,
855 .sources = &clkset_group2,
856 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
857 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
861 .devname = "s3c-sdhci.1",
862 .enable = s5pv210_clk_mask0_ctrl,
865 .sources = &clkset_group2,
866 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
867 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
871 .devname = "s3c-sdhci.2",
872 .enable = s5pv210_clk_mask0_ctrl,
873 .ctrlbit = (1 << 10),
875 .sources = &clkset_group2,
876 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
877 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
881 .devname = "s3c-sdhci.3",
882 .enable = s5pv210_clk_mask0_ctrl,
883 .ctrlbit = (1 << 11),
885 .sources = &clkset_group2,
886 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
887 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
891 .devname = "s5p-mfc",
892 .enable = s5pv210_clk_ip0_ctrl,
893 .ctrlbit = (1 << 16),
895 .sources = &clkset_group1,
896 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
897 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
901 .enable = s5pv210_clk_ip0_ctrl,
902 .ctrlbit = (1 << 12),
904 .sources = &clkset_group1,
905 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
906 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
910 .enable = s5pv210_clk_ip0_ctrl,
913 .sources = &clkset_group1,
914 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
915 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
919 .enable = s5pv210_clk_mask0_ctrl,
922 .sources = &clkset_group2,
923 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
924 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
928 .devname = "s3c64xx-spi.0",
929 .enable = s5pv210_clk_mask0_ctrl,
930 .ctrlbit = (1 << 16),
932 .sources = &clkset_group2,
933 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
934 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
938 .devname = "s3c64xx-spi.1",
939 .enable = s5pv210_clk_mask0_ctrl,
940 .ctrlbit = (1 << 17),
942 .sources = &clkset_group2,
943 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
944 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
948 .enable = s5pv210_clk_mask0_ctrl,
949 .ctrlbit = (1 << 29),
951 .sources = &clkset_group2,
952 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
953 .reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
957 .enable = s5pv210_clk_mask0_ctrl,
958 .ctrlbit = (1 << 19),
960 .sources = &clkset_group2,
961 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
962 .reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
966 /* Clock initialisation code */
967 static struct clksrc_clk *sysclks[] = {
992 static u32 epll_div[][6] = {
993 { 48000000, 0, 48, 3, 3, 0 },
994 { 96000000, 0, 48, 3, 2, 0 },
995 { 144000000, 1, 72, 3, 2, 0 },
996 { 192000000, 0, 48, 3, 1, 0 },
997 { 288000000, 1, 72, 3, 1, 0 },
998 { 32750000, 1, 65, 3, 4, 35127 },
999 { 32768000, 1, 65, 3, 4, 35127 },
1000 { 45158400, 0, 45, 3, 3, 10355 },
1001 { 45000000, 0, 45, 3, 3, 10355 },
1002 { 45158000, 0, 45, 3, 3, 10355 },
1003 { 49125000, 0, 49, 3, 3, 9961 },
1004 { 49152000, 0, 49, 3, 3, 9961 },
1005 { 67737600, 1, 67, 3, 3, 48366 },
1006 { 67738000, 1, 67, 3, 3, 48366 },
1007 { 73800000, 1, 73, 3, 3, 47710 },
1008 { 73728000, 1, 73, 3, 3, 47710 },
1009 { 36000000, 1, 32, 3, 4, 0 },
1010 { 60000000, 1, 60, 3, 3, 0 },
1011 { 72000000, 1, 72, 3, 3, 0 },
1012 { 80000000, 1, 80, 3, 3, 0 },
1013 { 84000000, 0, 42, 3, 2, 0 },
1014 { 50000000, 0, 50, 3, 3, 0 },
1017 static int s5pv210_epll_set_rate(struct clk *clk, unsigned long rate)
1019 unsigned int epll_con, epll_con_k;
1022 /* Return if nothing changed */
1023 if (clk->rate == rate)
1026 epll_con = __raw_readl(S5P_EPLL_CON);
1027 epll_con_k = __raw_readl(S5P_EPLL_CON1);
1029 epll_con_k &= ~PLL46XX_KDIV_MASK;
1030 epll_con &= ~(1 << 27 |
1031 PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT |
1032 PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT |
1033 PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
1035 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
1036 if (epll_div[i][0] == rate) {
1037 epll_con_k |= epll_div[i][5] << 0;
1038 epll_con |= (epll_div[i][1] << 27 |
1039 epll_div[i][2] << PLL46XX_MDIV_SHIFT |
1040 epll_div[i][3] << PLL46XX_PDIV_SHIFT |
1041 epll_div[i][4] << PLL46XX_SDIV_SHIFT);
1046 if (i == ARRAY_SIZE(epll_div)) {
1047 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
1052 __raw_writel(epll_con, S5P_EPLL_CON);
1053 __raw_writel(epll_con_k, S5P_EPLL_CON1);
1055 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
1063 static struct clk_ops s5pv210_epll_ops = {
1064 .set_rate = s5pv210_epll_set_rate,
1065 .get_rate = s5p_epll_get_rate,
1068 void __init_or_cpufreq s5pv210_setup_clocks(void)
1070 struct clk *xtal_clk;
1071 unsigned long vpllsrc;
1072 unsigned long armclk;
1073 unsigned long hclk_msys;
1074 unsigned long hclk_dsys;
1075 unsigned long hclk_psys;
1076 unsigned long pclk_msys;
1077 unsigned long pclk_dsys;
1078 unsigned long pclk_psys;
1084 u32 clkdiv0, clkdiv1;
1086 /* Set functions for clk_fout_epll */
1087 clk_fout_epll.enable = s5p_epll_enable;
1088 clk_fout_epll.ops = &s5pv210_epll_ops;
1090 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1092 clkdiv0 = __raw_readl(S5P_CLK_DIV0);
1093 clkdiv1 = __raw_readl(S5P_CLK_DIV1);
1095 printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
1096 __func__, clkdiv0, clkdiv1);
1098 xtal_clk = clk_get(NULL, "xtal");
1099 BUG_ON(IS_ERR(xtal_clk));
1101 xtal = clk_get_rate(xtal_clk);
1104 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1106 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508);
1107 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
1108 epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON),
1109 __raw_readl(S5P_EPLL_CON1), pll_4600);
1110 vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
1111 vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502);
1113 clk_fout_apll.ops = &clk_fout_apll_ops;
1114 clk_fout_mpll.rate = mpll;
1115 clk_fout_epll.rate = epll;
1116 clk_fout_vpll.rate = vpll;
1118 printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
1119 apll, mpll, epll, vpll);
1121 armclk = clk_get_rate(&clk_armclk.clk);
1122 hclk_msys = clk_get_rate(&clk_hclk_msys.clk);
1123 hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk);
1124 hclk_psys = clk_get_rate(&clk_hclk_psys.clk);
1125 pclk_msys = clk_get_rate(&clk_pclk_msys.clk);
1126 pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk);
1127 pclk_psys = clk_get_rate(&clk_pclk_psys.clk);
1129 printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n"
1130 "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n",
1131 armclk, hclk_msys, hclk_dsys, hclk_psys,
1132 pclk_msys, pclk_dsys, pclk_psys);
1134 clk_f.rate = armclk;
1135 clk_h.rate = hclk_psys;
1136 clk_p.rate = pclk_psys;
1138 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1139 s3c_set_clksrc(&clksrcs[ptr], true);
1142 static struct clk *clks[] __initdata = {
1152 void __init s5pv210_register_clocks(void)
1156 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1158 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1159 s3c_register_clksrc(sysclks[ptr], 1);
1161 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1162 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1164 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1165 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1167 s3c24xx_register_clock(&dummy_apb_pclk);