arch/arm/mach-omap2/pm34xx.c

   1 /*
   2  * OMAP3 Power Management Routines
   3  *
   4  * Copyright (C) 2006-2008 Nokia Corporation
   5  * Tony Lindgren <tony@atomide.com>
   6  * Jouni Hogander
   7  *
   8  * Copyright (C) 2007 Texas Instruments, Inc.
   9  * Rajendra Nayak <rnayak@ti.com>
  10  *
  11  * Copyright (C) 2005 Texas Instruments, Inc.
  12  * Richard Woodruff <r-woodruff2@ti.com>
  13  *
  14  * Based on pm.c for omap1
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License version 2 as
  18  * published by the Free Software Foundation.
  19  */
  20
  21 #include <linux/pm.h>
  22 #include <linux/suspend.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/list.h>
  26 #include <linux/err.h>
  27 #include <linux/gpio.h>
  28 #include <linux/clk.h>
  29 #include <linux/delay.h>
  30 #include <linux/slab.h>
  31 #include <linux/console.h>
  32 #include <trace/events/power.h>
  33
  34 #include <plat/sram.h>
  35 #include "clockdomain.h"
  36 #include "powerdomain.h"
  37 #include <plat/serial.h>
  38 #include <plat/sdrc.h>
  39 #include <plat/prcm.h>
  40 #include <plat/gpmc.h>
  41 #include <plat/dma.h>
  42
  43 #include "cm2xxx_3xxx.h"
  44 #include "cm-regbits-34xx.h"
  45 #include "prm-regbits-34xx.h"
  46
  47 #include "prm2xxx_3xxx.h"
  48 #include "pm.h"
  49 #include "sdrc.h"
  50 #include "control.h"
  51
  52 #ifdef CONFIG_SUSPEND
  53 static suspend_state_t suspend_state = PM_SUSPEND_ON;
  54 static inline bool is_suspending(void)
  55 {
  56         return (suspend_state != PM_SUSPEND_ON);
  57 }
  58 #else
  59 static inline bool is_suspending(void)
  60 {
  61         return false;
  62 }
  63 #endif
  64
  65 /* pm34xx errata defined in pm.h */
  66 u16 pm34xx_errata;
  67
  68 struct power_state {
  69         struct powerdomain *pwrdm;
  70         u32 next_state;
  71 #ifdef CONFIG_SUSPEND
  72         u32 saved_state;
  73 #endif
  74         struct list_head node;
  75 };
  76
  77 static LIST_HEAD(pwrst_list);
  78
  79 static void (*_omap_sram_idle)(u32 *addr, int save_state);
  80
  81 static int (*_omap_save_secure_sram)(u32 *addr);
  82
  83 static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
  84 static struct powerdomain *core_pwrdm, *per_pwrdm;
  85 static struct powerdomain *cam_pwrdm;
  86
  87 static inline void omap3_per_save_context(void)
  88 {
  89         omap_gpio_save_context();
  90 }
  91
  92 static inline void omap3_per_restore_context(void)
  93 {
  94         omap_gpio_restore_context();
  95 }
  96
  97 static void omap3_enable_io_chain(void)
  98 {
  99         int timeout = 0;
 100
 101         if (omap_rev() >= OMAP3430_REV_ES3_1) {
 102                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 103                                      PM_WKEN);
 104                 /* Do a readback to assure write has been done */
 105                 omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 106
 107                 while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
 108                          OMAP3430_ST_IO_CHAIN_MASK)) {
 109                         timeout++;
 110                         if (timeout > 1000) {
 111                                 printk(KERN_ERR "Wake up daisy chain "
 112                                        "activation failed.\n");
 113                                 return;
 114                         }
 115                         omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
 116                                              WKUP_MOD, PM_WKEN);
 117                 }
 118         }
 119 }
 120
 121 static void omap3_disable_io_chain(void)
 122 {
 123         if (omap_rev() >= OMAP3430_REV_ES3_1)
 124                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
 125                                        PM_WKEN);
 126 }
 127
 128 static void omap3_core_save_context(void)
 129 {
 130         omap3_ctrl_save_padconf();
 131
 132         /*
 133          * Force write last pad into memory, as this can fail in some
 134          * cases according to errata 1.157, 1.185
 135          */
 136         omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
 137                 OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
 138
 139         /* Save the Interrupt controller context */
 140         omap_intc_save_context();
 141         /* Save the GPMC context */
 142         omap3_gpmc_save_context();
 143         /* Save the system control module context, padconf already save above*/
 144         omap3_control_save_context();
 145         omap_dma_global_context_save();
 146 }
 147
 148 static void omap3_core_restore_context(void)
 149 {
 150         /* Restore the control module context, padconf restored by h/w */
 151         omap3_control_restore_context();
 152         /* Restore the GPMC context */
 153         omap3_gpmc_restore_context();
 154         /* Restore the interrupt controller context */
 155         omap_intc_restore_context();
 156         omap_dma_global_context_restore();
 157 }
 158
 159 /*
 160  * FIXME: This function should be called before entering off-mode after
 161  * OMAP3 secure services have been accessed. Currently it is only called
 162  * once during boot sequence, but this works as we are not using secure
 163  * services.
 164  */
 165 static void omap3_save_secure_ram_context(void)
 166 {
 167         u32 ret;
 168         int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 169
 170         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 171                 /*
 172                  * MPU next state must be set to POWER_ON temporarily,
 173                  * otherwise the WFI executed inside the ROM code
 174                  * will hang the system.
 175                  */
 176                 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
 177                 ret = _omap_save_secure_sram((u32 *)
 178                                 __pa(omap3_secure_ram_storage));
 179                 pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
 180                 /* Following is for error tracking, it should not happen */
 181                 if (ret) {
 182                         printk(KERN_ERR "save_secure_sram() returns %08x\n",
 183                                 ret);
 184                         while (1)
 185                                 ;
 186                 }
 187         }
 188 }
 189
 190 /*
 191  * PRCM Interrupt Handler Helper Function
 192  *
 193  * The purpose of this function is to clear any wake-up events latched
 194  * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 195  * may occur whilst attempting to clear a PM_WKST_x register and thus
 196  * set another bit in this register. A while loop is used to ensure
 197  * that any peripheral wake-up events occurring while attempting to
 198  * clear the PM_WKST_x are detected and cleared.
 199  */
 200 static int prcm_clear_mod_irqs(s16 module, u8 regs)
 201 {
 202         u32 wkst, fclk, iclk, clken;
 203         u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
 204         u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
 205         u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
 206         u16 grpsel_off = (regs == 3) ?
 207                 OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
 208         int c = 0;
 209
 210         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 211         wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
 212         if (wkst) {
 213                 iclk = omap2_cm_read_mod_reg(module, iclk_off);
 214                 fclk = omap2_cm_read_mod_reg(module, fclk_off);
 215                 while (wkst) {
 216                         clken = wkst;
 217                         omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
 218                         /*
 219                          * For USBHOST, we don't know whether HOST1 or
 220                          * HOST2 woke us up, so enable both f-clocks
 221                          */
 222                         if (module == OMAP3430ES2_USBHOST_MOD)
 223                                 clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
 224                         omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
 225                         omap2_prm_write_mod_reg(wkst, module, wkst_off);
 226                         wkst = omap2_prm_read_mod_reg(module, wkst_off);
 227                         c++;
 228                 }
 229                 omap2_cm_write_mod_reg(iclk, module, iclk_off);
 230                 omap2_cm_write_mod_reg(fclk, module, fclk_off);
 231         }
 232
 233         return c;
 234 }
 235
 236 static int _prcm_int_handle_wakeup(void)
 237 {
 238         int c;
 239
 240         c = prcm_clear_mod_irqs(WKUP_MOD, 1);
 241         c += prcm_clear_mod_irqs(CORE_MOD, 1);
 242         c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1);
 243         if (omap_rev() > OMAP3430_REV_ES1_0) {
 244                 c += prcm_clear_mod_irqs(CORE_MOD, 3);
 245                 c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1);
 246         }
 247
 248         return c;
 249 }
 250
 251 /*
 252  * PRCM Interrupt Handler
 253  *
 254  * The PRM_IRQSTATUS_MPU register indicates if there are any pending
 255  * interrupts from the PRCM for the MPU. These bits must be cleared in
 256  * order to clear the PRCM interrupt. The PRCM interrupt handler is
 257  * implemented to simply clear the PRM_IRQSTATUS_MPU in order to clear
 258  * the PRCM interrupt. Please note that bit 0 of the PRM_IRQSTATUS_MPU
 259  * register indicates that a wake-up event is pending for the MPU and
 260  * this bit can only be cleared if the all the wake-up events latched
 261  * in the various PM_WKST_x registers have been cleared. The interrupt
 262  * handler is implemented using a do-while loop so that if a wake-up
 263  * event occurred during the processing of the prcm interrupt handler
 264  * (setting a bit in the corresponding PM_WKST_x register and thus
 265  * preventing us from clearing bit 0 of the PRM_IRQSTATUS_MPU register)
 266  * this would be handled.
 267  */
 268 static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id)
 269 {
 270         u32 irqenable_mpu, irqstatus_mpu;
 271         int c = 0;
 272
 273         irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 274                                          OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 275         irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 276                                          OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 277         irqstatus_mpu &= irqenable_mpu;
 278
 279         do {
 280                 if (irqstatus_mpu & (OMAP3430_WKUP_ST_MASK |
 281                                      OMAP3430_IO_ST_MASK)) {
 282                         c = _prcm_int_handle_wakeup();
 283
 284                         /*
 285                          * Is the MPU PRCM interrupt handler racing with the
 286                          * IVA2 PRCM interrupt handler ?
 287                          */
 288                         WARN(c == 0, "prcm: WARNING: PRCM indicated MPU wakeup "
 289                              "but no wakeup sources are marked\n");
 290                 } else {
 291                         /* XXX we need to expand our PRCM interrupt handler */
 292                         WARN(1, "prcm: WARNING: PRCM interrupt received, but "
 293                              "no code to handle it (%08x)\n", irqstatus_mpu);
 294                 }
 295
 296                 omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD,
 297                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 298
 299                 irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD,
 300                                         OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 301                 irqstatus_mpu &= irqenable_mpu;
 302
 303         } while (irqstatus_mpu);
 304
 305         return IRQ_HANDLED;
 306 }
 307
 308 static void omap34xx_do_sram_idle(unsigned long save_state)
 309 {
 310         _omap_sram_idle(omap3_arm_context, save_state);
 311 }
 312
 313 void omap_sram_idle(void)
 314 {
 315         /* Variable to tell what needs to be saved and restored
 316          * in omap_sram_idle*/
 317         /* save_state = 0 => Nothing to save and restored */
 318         /* save_state = 1 => Only L1 and logic lost */
 319         /* save_state = 2 => Only L2 lost */
 320         /* save_state = 3 => L1, L2 and logic lost */
 321         int save_state = 0;
 322         int mpu_next_state = PWRDM_POWER_ON;
 323         int per_next_state = PWRDM_POWER_ON;
 324         int core_next_state = PWRDM_POWER_ON;
 325         int per_going_off;
 326         int core_prev_state, per_prev_state;
 327         u32 sdrc_pwr = 0;
 328
 329         if (!_omap_sram_idle)
 330                 return;
 331
 332         pwrdm_clear_all_prev_pwrst(mpu_pwrdm);
 333         pwrdm_clear_all_prev_pwrst(neon_pwrdm);
 334         pwrdm_clear_all_prev_pwrst(core_pwrdm);
 335         pwrdm_clear_all_prev_pwrst(per_pwrdm);
 336
 337         mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
 338         switch (mpu_next_state) {
 339         case PWRDM_POWER_ON:
 340         case PWRDM_POWER_RET:
 341                 /* No need to save context */
 342                 save_state = 0;
 343                 break;
 344         case PWRDM_POWER_OFF:
 345                 save_state = 3;
 346                 break;
 347         default:
 348                 /* Invalid state */
 349                 printk(KERN_ERR "Invalid mpu state in sram_idle\n");
 350                 return;
 351         }
 352         pwrdm_pre_transition();
 353
 354         /* NEON control */
 355         if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
 356                 pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
 357
 358         /* Enable IO-PAD and IO-CHAIN wakeups */
 359         per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
 360         core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
 361         if (omap3_has_io_wakeup() &&
 362             (per_next_state < PWRDM_POWER_ON ||
 363              core_next_state < PWRDM_POWER_ON)) {
 364                 omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
 365                 omap3_enable_io_chain();
 366         }
 367
 368         /* Block console output in case it is on one of the OMAP UARTs */
 369         if (!is_suspending())
 370                 if (per_next_state < PWRDM_POWER_ON ||
 371                     core_next_state < PWRDM_POWER_ON)
 372                         if (!console_trylock())
 373                                 goto console_still_active;
 374
 375         /* PER */
 376         if (per_next_state < PWRDM_POWER_ON) {
 377                 per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
 378                 omap_uart_prepare_idle(2);
 379                 omap_uart_prepare_idle(3);
 380                 omap2_gpio_prepare_for_idle(per_going_off);
 381                 if (per_next_state == PWRDM_POWER_OFF)
 382                                 omap3_per_save_context();
 383         }
 384
 385         /* CORE */
 386         if (core_next_state < PWRDM_POWER_ON) {
 387                 omap_uart_prepare_idle(0);
 388                 omap_uart_prepare_idle(1);
 389                 if (core_next_state == PWRDM_POWER_OFF) {
 390                         omap3_core_save_context();
 391                         omap3_cm_save_context();
 392                 }
 393         }
 394
 395         omap3_intc_prepare_idle();
 396
 397         /*
 398         * On EMU/HS devices ROM code restores a SRDC value
 399         * from scratchpad which has automatic self refresh on timeout
 400         * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
 401         * Hence store/restore the SDRC_POWER register here.
 402         */
 403         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 404             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 405             core_next_state == PWRDM_POWER_OFF)
 406                 sdrc_pwr = sdrc_read_reg(SDRC_POWER);
 407
 408         /*
 409          * omap3_arm_context is the location where some ARM context
 410          * get saved. The rest is placed on the stack, and restored
 411          * from there before resuming.
 412          */
 413         if (save_state == 1 || save_state == 3)
 414                 cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, save_state,
 415                             omap34xx_do_sram_idle);
 416         else
 417                 omap34xx_do_sram_idle(save_state);
 418
 419         /* Restore normal SDRC POWER settings */
 420         if (omap_rev() >= OMAP3430_REV_ES3_0 &&
 421             omap_type() != OMAP2_DEVICE_TYPE_GP &&
 422             core_next_state == PWRDM_POWER_OFF)
 423                 sdrc_write_reg(sdrc_pwr, SDRC_POWER);
 424
 425         /* CORE */
 426         if (core_next_state < PWRDM_POWER_ON) {
 427                 core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
 428                 if (core_prev_state == PWRDM_POWER_OFF) {
 429                         omap3_core_restore_context();
 430                         omap3_cm_restore_context();
 431                         omap3_sram_restore_context();
 432                         omap2_sms_restore_context();
 433                 }
 434                 omap_uart_resume_idle(0);
 435                 omap_uart_resume_idle(1);
 436                 if (core_next_state == PWRDM_POWER_OFF)
 437                         omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
 438                                                OMAP3430_GR_MOD,
 439                                                OMAP3_PRM_VOLTCTRL_OFFSET);
 440         }
 441         omap3_intc_resume_idle();
 442
 443         /* PER */
 444         if (per_next_state < PWRDM_POWER_ON) {
 445                 per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
 446                 omap2_gpio_resume_after_idle();
 447                 if (per_prev_state == PWRDM_POWER_OFF)
 448                         omap3_per_restore_context();
 449                 omap_uart_resume_idle(2);
 450                 omap_uart_resume_idle(3);
 451         }
 452
 453         if (!is_suspending())
 454                 console_unlock();
 455
 456 console_still_active:
 457         /* Disable IO-PAD and IO-CHAIN wakeup */
 458         if (omap3_has_io_wakeup() &&
 459             (per_next_state < PWRDM_POWER_ON ||
 460              core_next_state < PWRDM_POWER_ON)) {
 461                 omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
 462                                              PM_WKEN);
 463                 omap3_disable_io_chain();
 464         }
 465
 466         pwrdm_post_transition();
 467
 468         clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
 469 }
 470
 471 int omap3_can_sleep(void)
 472 {
 473         if (!sleep_while_idle)
 474                 return 0;
 475         if (!omap_uart_can_sleep())
 476                 return 0;
 477         return 1;
 478 }
 479
 480 static void omap3_pm_idle(void)
 481 {
 482         local_irq_disable();
 483         local_fiq_disable();
 484
 485         if (!omap3_can_sleep())
 486                 goto out;
 487
 488         if (omap_irq_pending() || need_resched())
 489                 goto out;
 490
 491         trace_power_start(POWER_CSTATE, 1, smp_processor_id());
 492         trace_cpu_idle(1, smp_processor_id());
 493
 494         omap_sram_idle();
 495
 496         trace_power_end(smp_processor_id());
 497         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
 498
 499 out:
 500         local_fiq_enable();
 501         local_irq_enable();
 502 }
 503
 504 #ifdef CONFIG_SUSPEND
 505 static int omap3_pm_suspend(void)
 506 {
 507         struct power_state *pwrst;
 508         int state, ret = 0;
 509
 510         if (wakeup_timer_seconds || wakeup_timer_milliseconds)
 511                 omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
 512                                          wakeup_timer_milliseconds);
 513
 514         /* Read current next_pwrsts */
 515         list_for_each_entry(pwrst, &pwrst_list, node)
 516                 pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
 517         /* Set ones wanted by suspend */
 518         list_for_each_entry(pwrst, &pwrst_list, node) {
 519                 if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
 520                         goto restore;
 521                 if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
 522                         goto restore;
 523         }
 524
 525         omap_uart_prepare_suspend();
 526         omap3_intc_suspend();
 527
 528         omap_sram_idle();
 529
 530 restore:
 531         /* Restore next_pwrsts */
 532         list_for_each_entry(pwrst, &pwrst_list, node) {
 533                 state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
 534                 if (state > pwrst->next_state) {
 535                         printk(KERN_INFO "Powerdomain (%s) didn't enter "
 536                                "target state %d\n",
 537                                pwrst->pwrdm->name, pwrst->next_state);
 538                         ret = -1;
 539                 }
 540                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
 541         }
 542         if (ret)
 543                 printk(KERN_ERR "Could not enter target state in pm_suspend\n");
 544         else
 545                 printk(KERN_INFO "Successfully put all powerdomains "
 546                        "to target state\n");
 547
 548         return ret;
 549 }
 550
 551 static int omap3_pm_enter(suspend_state_t unused)
 552 {
 553         int ret = 0;
 554
 555         switch (suspend_state) {
 556         case PM_SUSPEND_STANDBY:
 557         case PM_SUSPEND_MEM:
 558                 ret = omap3_pm_suspend();
 559                 break;
 560         default:
 561                 ret = -EINVAL;
 562         }
 563
 564         return ret;
 565 }
 566
 567 /* Hooks to enable / disable UART interrupts during suspend */
 568 static int omap3_pm_begin(suspend_state_t state)
 569 {
 570         disable_hlt();
 571         suspend_state = state;
 572         omap_uart_enable_irqs(0);
 573         return 0;
 574 }
 575
 576 static void omap3_pm_end(void)
 577 {
 578         suspend_state = PM_SUSPEND_ON;
 579         omap_uart_enable_irqs(1);
 580         enable_hlt();
 581         return;
 582 }
 583
 584 static const struct platform_suspend_ops omap_pm_ops = {
 585         .begin          = omap3_pm_begin,
 586         .end            = omap3_pm_end,
 587         .enter          = omap3_pm_enter,
 588         .valid          = suspend_valid_only_mem,
 589 };
 590 #endif /* CONFIG_SUSPEND */
 591
 592
 593 /**
 594  * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 595  *                   retention
 596  *
 597  * In cases where IVA2 is activated by bootcode, it may prevent
 598  * full-chip retention or off-mode because it is not idle.  This
 599  * function forces the IVA2 into idle state so it can go
 600  * into retention/off and thus allow full-chip retention/off.
 601  *
 602  **/
 603 static void __init omap3_iva_idle(void)
 604 {
 605         /* ensure IVA2 clock is disabled */
 606         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 607
 608         /* if no clock activity, nothing else to do */
 609         if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
 610               OMAP3430_CLKACTIVITY_IVA2_MASK))
 611                 return;
 612
 613         /* Reset IVA2 */
 614         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 615                           OMAP3430_RST2_IVA2_MASK |
 616                           OMAP3430_RST3_IVA2_MASK,
 617                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 618
 619         /* Enable IVA2 clock */
 620         omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
 621                          OMAP3430_IVA2_MOD, CM_FCLKEN);
 622
 623         /* Set IVA2 boot mode to 'idle' */
 624         omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
 625                          OMAP343X_CONTROL_IVA2_BOOTMOD);
 626
 627         /* Un-reset IVA2 */
 628         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 629
 630         /* Disable IVA2 clock */
 631         omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
 632
 633         /* Reset IVA2 */
 634         omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
 635                           OMAP3430_RST2_IVA2_MASK |
 636                           OMAP3430_RST3_IVA2_MASK,
 637                           OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
 638 }
 639
 640 static void __init omap3_d2d_idle(void)
 641 {
 642         u16 mask, padconf;
 643
 644         /* In a stand alone OMAP3430 where there is not a stacked
 645          * modem for the D2D Idle Ack and D2D MStandby must be pulled
 646          * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
 647          * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
 648         mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
 649         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
 650         padconf |= mask;
 651         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);
 652
 653         padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
 654         padconf |= mask;
 655         omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);
 656
 657         /* reset modem */
 658         omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
 659                           OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
 660                           CORE_MOD, OMAP2_RM_RSTCTRL);
 661         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
 662 }
 663
 664 static void __init prcm_setup_regs(void)
 665 {
 666         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
 667                                         OMAP3630_EN_UART4_MASK : 0;
 668         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
 669                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 670
 671         /* XXX This should be handled by hwmod code or SCM init code */
 672         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 673
 674         /*
 675          * Enable control of expternal oscillator through
 676          * sys_clkreq. In the long run clock framework should
 677          * take care of this.
 678          */
 679         omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
 680                              1 << OMAP_AUTOEXTCLKMODE_SHIFT,
 681                              OMAP3430_GR_MOD,
 682                              OMAP3_PRM_CLKSRC_CTRL_OFFSET);
 683
 684         /* setup wakup source */
 685         omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
 686                           OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
 687                           WKUP_MOD, PM_WKEN);
 688         /* No need to write EN_IO, that is always enabled */
 689         omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
 690                           OMAP3430_GRPSEL_GPT1_MASK |
 691                           OMAP3430_GRPSEL_GPT12_MASK,
 692                           WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
 693         /* For some reason IO doesn't generate wakeup event even if
 694          * it is selected to mpu wakeup goup */
 695         omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK,
 696                           OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET);
 697
 698         /* Enable PM_WKEN to support DSS LPR */
 699         omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
 700                                 OMAP3430_DSS_MOD, PM_WKEN);
 701
 702         /* Enable wakeups in PER */
 703         omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
 704                           OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
 705                           OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
 706                           OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
 707                           OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
 708                           OMAP3430_EN_MCBSP4_MASK,
 709                           OMAP3430_PER_MOD, PM_WKEN);
 710         /* and allow them to wake up MPU */
 711         omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
 712                           OMAP3430_GRPSEL_GPIO2_MASK |
 713                           OMAP3430_GRPSEL_GPIO3_MASK |
 714                           OMAP3430_GRPSEL_GPIO4_MASK |
 715                           OMAP3430_GRPSEL_GPIO5_MASK |
 716                           OMAP3430_GRPSEL_GPIO6_MASK |
 717                           OMAP3430_GRPSEL_UART3_MASK |
 718                           OMAP3430_GRPSEL_MCBSP2_MASK |
 719                           OMAP3430_GRPSEL_MCBSP3_MASK |
 720                           OMAP3430_GRPSEL_MCBSP4_MASK,
 721                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 722
 723         /* Don't attach IVA interrupts */
 724         omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
 725         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
 726         omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
 727         omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
 728
 729         /* Clear any pending 'reset' flags */
 730         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
 731         omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
 732         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
 733         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
 734         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
 735         omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
 736         omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
 737
 738         /* Clear any pending PRCM interrupts */
 739         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 740
 741         omap3_iva_idle();
 742         omap3_d2d_idle();
 743 }
 744
 745 void omap3_pm_off_mode_enable(int enable)
 746 {
 747         struct power_state *pwrst;
 748         u32 state;
 749
 750         if (enable)
 751                 state = PWRDM_POWER_OFF;
 752         else
 753                 state = PWRDM_POWER_RET;
 754
 755         list_for_each_entry(pwrst, &pwrst_list, node) {
 756                 if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
 757                                 pwrst->pwrdm == core_pwrdm &&
 758                                 state == PWRDM_POWER_OFF) {
 759                         pwrst->next_state = PWRDM_POWER_RET;
 760                         pr_warn("%s: Core OFF disabled due to errata i583\n",
 761                                 __func__);
 762                 } else {
 763                         pwrst->next_state = state;
 764                 }
 765                 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 766         }
 767 }
 768
 769 int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
 770 {
 771         struct power_state *pwrst;
 772
 773         list_for_each_entry(pwrst, &pwrst_list, node) {
 774                 if (pwrst->pwrdm == pwrdm)
 775                         return pwrst->next_state;
 776         }
 777         return -EINVAL;
 778 }
 779
 780 int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
 781 {
 782         struct power_state *pwrst;
 783
 784         list_for_each_entry(pwrst, &pwrst_list, node) {
 785                 if (pwrst->pwrdm == pwrdm) {
 786                         pwrst->next_state = state;
 787                         return 0;
 788                 }
 789         }
 790         return -EINVAL;
 791 }
 792
 793 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
 794 {
 795         struct power_state *pwrst;
 796
 797         if (!pwrdm->pwrsts)
 798                 return 0;
 799
 800         pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
 801         if (!pwrst)
 802                 return -ENOMEM;
 803         pwrst->pwrdm = pwrdm;
 804         pwrst->next_state = PWRDM_POWER_RET;
 805         list_add(&pwrst->node, &pwrst_list);
 806
 807         if (pwrdm_has_hdwr_sar(pwrdm))
 808                 pwrdm_enable_hdwr_sar(pwrdm);
 809
 810         return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
 811 }
 812
 813 /*
 814  * Enable hw supervised mode for all clockdomains if it's
 815  * supported. Initiate sleep transition for other clockdomains, if
 816  * they are not used
 817  */
 818 static int __init clkdms_setup(struct clockdomain *clkdm, void *unused)
 819 {
 820         if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
 821                 clkdm_allow_idle(clkdm);
 822         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
 823                  atomic_read(&clkdm->usecount) == 0)
 824                 clkdm_sleep(clkdm);
 825         return 0;
 826 }
 827
 828 void omap_push_sram_idle(void)
 829 {
 830         _omap_sram_idle = omap_sram_push(omap34xx_cpu_suspend,
 831                                         omap34xx_cpu_suspend_sz);
 832         if (omap_type() != OMAP2_DEVICE_TYPE_GP)
 833                 _omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
 834                                 save_secure_ram_context_sz);
 835 }
 836
 837 static void __init pm_errata_configure(void)
 838 {
 839         if (cpu_is_omap3630()) {
 840                 pm34xx_errata |= PM_RTA_ERRATUM_i608;
 841                 /* Enable the l2 cache toggling in sleep logic */
 842                 enable_omap3630_toggle_l2_on_restore();
 843                 if (omap_rev() < OMAP3630_REV_ES1_2)
 844                         pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
 845         }
 846 }
 847
 848 static int __init omap3_pm_init(void)
 849 {
 850         struct power_state *pwrst, *tmp;
 851         struct clockdomain *neon_clkdm, *per_clkdm, *mpu_clkdm, *core_clkdm;
 852         int ret;
 853
 854         if (!cpu_is_omap34xx())
 855                 return -ENODEV;
 856
 857         pm_errata_configure();
 858
 859         /* XXX prcm_setup_regs needs to be before enabling hw
 860          * supervised mode for powerdomains */
 861         prcm_setup_regs();
 862
 863         ret = request_irq(INT_34XX_PRCM_MPU_IRQ,
 864                           (irq_handler_t)prcm_interrupt_handler,
 865                           IRQF_DISABLED, "prcm", NULL);
 866         if (ret) {
 867                 printk(KERN_ERR "request_irq failed to register for 0x%x\n",
 868                        INT_34XX_PRCM_MPU_IRQ);
 869                 goto err1;
 870         }
 871
 872         ret = pwrdm_for_each(pwrdms_setup, NULL);
 873         if (ret) {
 874                 printk(KERN_ERR "Failed to setup powerdomains\n");
 875                 goto err2;
 876         }
 877
 878         (void) clkdm_for_each(clkdms_setup, NULL);
 879
 880         mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
 881         if (mpu_pwrdm == NULL) {
 882                 printk(KERN_ERR "Failed to get mpu_pwrdm\n");
 883                 goto err2;
 884         }
 885
 886         neon_pwrdm = pwrdm_lookup("neon_pwrdm");
 887         per_pwrdm = pwrdm_lookup("per_pwrdm");
 888         core_pwrdm = pwrdm_lookup("core_pwrdm");
 889         cam_pwrdm = pwrdm_lookup("cam_pwrdm");
 890
 891         neon_clkdm = clkdm_lookup("neon_clkdm");
 892         mpu_clkdm = clkdm_lookup("mpu_clkdm");
 893         per_clkdm = clkdm_lookup("per_clkdm");
 894         core_clkdm = clkdm_lookup("core_clkdm");
 895
 896         omap_push_sram_idle();
 897 #ifdef CONFIG_SUSPEND
 898         suspend_set_ops(&omap_pm_ops);
 899 #endif /* CONFIG_SUSPEND */
 900
 901         pm_idle = omap3_pm_idle;
 902         omap3_idle_init();
 903
 904         /*
 905          * RTA is disabled during initialization as per erratum i608
 906          * it is safer to disable RTA by the bootloader, but we would like
 907          * to be doubly sure here and prevent any mishaps.
 908          */
 909         if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
 910                 omap3630_ctrl_disable_rta();
 911
 912         clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
 913         if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
 914                 omap3_secure_ram_storage =
 915                         kmalloc(0x803F, GFP_KERNEL);
 916                 if (!omap3_secure_ram_storage)
 917                         printk(KERN_ERR "Memory allocation failed when"
 918                                         "allocating for secure sram context\n");
 919
 920                 local_irq_disable();
 921                 local_fiq_disable();
 922
 923                 omap_dma_global_context_save();
 924                 omap3_save_secure_ram_context();
 925                 omap_dma_global_context_restore();
 926
 927                 local_irq_enable();
 928                 local_fiq_enable();
 929         }
 930
 931         omap3_save_scratchpad_contents();
 932 err1:
 933         return ret;
 934 err2:
 935         free_irq(INT_34XX_PRCM_MPU_IRQ, NULL);
 936         list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
 937                 list_del(&pwrst->node);
 938                 kfree(pwrst);
 939         }
 940         return ret;
 941 }
 942
 943 late_initcall(omap3_pm_init);