2 * linux/arch/arm/mach-omap2/id.c
4 * OMAP2 CPU identification code
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * Copyright (C) 2009-11 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
21 #include <linux/slab.h>
24 #include <linux/sys_soc.h>
25 #include <linux/err.h>
28 #include <asm/cputype.h>
30 #include <plat/common.h>
37 #define OMAP_SOC_MAX_NAME_LENGTH 16
39 static unsigned int omap_revision;
40 static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
41 static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
44 unsigned int omap_rev(void)
48 EXPORT_SYMBOL(omap_rev);
56 if (cpu_is_omap24xx()) {
57 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
58 } else if (cpu_is_omap34xx()) {
59 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
60 } else if (cpu_is_omap44xx()) {
61 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
63 pr_err("Cannot detect omap type!\n");
67 val &= OMAP2_DEVICETYPE_MASK;
73 EXPORT_SYMBOL(omap_type);
76 /*----------------------------------------------------------------------------*/
78 #define OMAP_TAP_IDCODE 0x0204
79 #define OMAP_TAP_DIE_ID_0 0x0218
80 #define OMAP_TAP_DIE_ID_1 0x021C
81 #define OMAP_TAP_DIE_ID_2 0x0220
82 #define OMAP_TAP_DIE_ID_3 0x0224
84 #define OMAP_TAP_DIE_ID_44XX_0 0x0200
85 #define OMAP_TAP_DIE_ID_44XX_1 0x0208
86 #define OMAP_TAP_DIE_ID_44XX_2 0x020c
87 #define OMAP_TAP_DIE_ID_44XX_3 0x0210
89 #define read_tap_reg(reg) __raw_readl(tap_base + (reg))
92 u16 hawkeye; /* Silicon type (Hawkeye id) */
93 u8 dev; /* Device type from production_id reg */
94 u32 type; /* Combined type id copied to omap_revision */
97 /* Register values to detect the OMAP version */
98 static struct omap_id omap_ids[] __initdata = {
99 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
100 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
101 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
102 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
103 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
104 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
107 static void __iomem *tap_base;
108 static u16 tap_prod_id;
110 void omap_get_die_id(struct omap_die_id *odi)
112 if (cpu_is_omap44xx()) {
113 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
114 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
115 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
116 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
120 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
121 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
122 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
123 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
126 void __init omap2xxx_check_revision(void)
132 struct omap_die_id odi;
134 idcode = read_tap_reg(OMAP_TAP_IDCODE);
135 prod_id = read_tap_reg(tap_prod_id);
136 hawkeye = (idcode >> 12) & 0xffff;
137 rev = (idcode >> 28) & 0x0f;
138 dev_type = (prod_id >> 16) & 0x0f;
139 omap_get_die_id(&odi);
141 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
142 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
143 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
144 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
145 odi.id_1, (odi.id_1 >> 28) & 0xf);
146 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
147 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
148 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
151 /* Check hawkeye ids */
152 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
153 if (hawkeye == omap_ids[i].hawkeye)
157 if (i == ARRAY_SIZE(omap_ids)) {
158 printk(KERN_ERR "Unknown OMAP CPU id\n");
162 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
163 if (dev_type == omap_ids[j].dev)
167 if (j == ARRAY_SIZE(omap_ids)) {
168 printk(KERN_ERR "Unknown OMAP device type. "
169 "Handling it as OMAP%04x\n",
170 omap_ids[i].type >> 16);
174 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
175 sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
177 pr_info("%s", soc_name);
178 if ((omap_rev() >> 8) & 0x0f)
179 pr_info("%s", soc_rev);
183 #define OMAP3_SHOW_FEATURE(feat) \
184 if (omap3_has_ ##feat()) \
187 static void __init omap3_cpuinfo(void)
189 const char *cpu_name;
192 * OMAP3430 and OMAP3530 are assumed to be same.
194 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
195 * on available features. Upon detection, update the CPU id
196 * and CPU class bits.
198 if (cpu_is_omap3630()) {
199 cpu_name = "OMAP3630";
200 } else if (cpu_is_omap3517()) {
202 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
203 } else if (cpu_is_ti816x()) {
205 } else if (omap3_has_iva() && omap3_has_sgx()) {
206 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
207 cpu_name = "OMAP3430/3530";
208 } else if (omap3_has_iva()) {
209 cpu_name = "OMAP3525";
210 } else if (omap3_has_sgx()) {
211 cpu_name = "OMAP3515";
213 cpu_name = "OMAP3503";
216 sprintf(soc_name, "%s", cpu_name);
218 /* Print verbose information */
219 pr_info("%s %s (", soc_name, soc_rev);
221 OMAP3_SHOW_FEATURE(l2cache);
222 OMAP3_SHOW_FEATURE(iva);
223 OMAP3_SHOW_FEATURE(sgx);
224 OMAP3_SHOW_FEATURE(neon);
225 OMAP3_SHOW_FEATURE(isp);
226 OMAP3_SHOW_FEATURE(192mhz_clk);
231 #define OMAP3_CHECK_FEATURE(status,feat) \
232 if (((status & OMAP3_ ##feat## _MASK) \
233 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
234 omap_features |= OMAP3_HAS_ ##feat; \
237 void __init omap3xxx_check_features(void)
243 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
245 OMAP3_CHECK_FEATURE(status, L2CACHE);
246 OMAP3_CHECK_FEATURE(status, IVA);
247 OMAP3_CHECK_FEATURE(status, SGX);
248 OMAP3_CHECK_FEATURE(status, NEON);
249 OMAP3_CHECK_FEATURE(status, ISP);
250 if (cpu_is_omap3630())
251 omap_features |= OMAP3_HAS_192MHZ_CLK;
252 if (cpu_is_omap3430() || cpu_is_omap3630())
253 omap_features |= OMAP3_HAS_IO_WAKEUP;
254 if (cpu_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
255 omap_rev() == OMAP3430_REV_ES3_1_2)
256 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
258 omap_features |= OMAP3_HAS_SDRC;
261 * TODO: Get additional info (where applicable)
262 * e.g. Size of L2 cache.
268 void __init omap4xxx_check_features(void)
272 if (cpu_is_omap443x())
273 omap_features |= OMAP4_HAS_MPU_1GHZ;
276 if (cpu_is_omap446x()) {
278 read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
279 switch ((si_type & (3 << 16)) >> 16) {
281 /* High performance device */
282 omap_features |= OMAP4_HAS_MPU_1_5GHZ;
286 /* Standard device */
287 omap_features |= OMAP4_HAS_MPU_1_2GHZ;
293 void __init ti81xx_check_features(void)
295 omap_features = OMAP3_HAS_NEON;
299 void __init omap3xxx_check_revision(void)
307 * We cannot access revision registers on ES1.0.
308 * If the processor type is Cortex-A8 and the revision is 0x0
309 * it means its Cortex r0p0 which is 3430 ES1.0.
311 cpuid = read_cpuid(CPUID_ID);
312 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
313 omap_revision = OMAP3430_REV_ES1_0;
319 * Detection for 34xx ES2.0 and above can be done with just
320 * hawkeye and rev. See TRM 1.5.2 Device Identification.
321 * Note that rev does not map directly to our defined processor
322 * revision numbers as ES1.0 uses value 0.
324 idcode = read_tap_reg(OMAP_TAP_IDCODE);
325 hawkeye = (idcode >> 12) & 0xffff;
326 rev = (idcode >> 28) & 0xff;
330 /* Handle 34xx/35xx devices */
332 case 0: /* Take care of early samples */
334 omap_revision = OMAP3430_REV_ES2_0;
338 omap_revision = OMAP3430_REV_ES2_1;
342 omap_revision = OMAP3430_REV_ES3_0;
346 omap_revision = OMAP3430_REV_ES3_1;
352 /* Use the latest known revision as default */
353 omap_revision = OMAP3430_REV_ES3_1_2;
359 * Handle OMAP/AM 3505/3517 devices
361 * Set the device to be OMAP3517 here. Actual device
362 * is identified later based on the features.
366 omap_revision = OMAP3517_REV_ES1_0;
372 omap_revision = OMAP3517_REV_ES1_1;
377 /* Handle 36xx devices */
380 case 0: /* Take care of early samples */
381 omap_revision = OMAP3630_REV_ES1_0;
385 omap_revision = OMAP3630_REV_ES1_1;
391 omap_revision = OMAP3630_REV_ES1_2;
398 omap_revision = TI8168_REV_ES1_0;
404 omap_revision = TI8168_REV_ES1_1;
410 /* Unknown default to latest silicon rev as default */
411 omap_revision = OMAP3630_REV_ES1_2;
413 pr_warn("Warning: unknown chip type; assuming OMAP3630ES1.2\n");
415 sprintf(soc_rev, "ES%s", cpu_rev);
418 void __init omap4xxx_check_revision(void)
425 * The IC rev detection is done with hawkeye and rev.
426 * Note that rev does not map directly to defined processor
427 * revision numbers as ES1.0 uses value 0.
429 idcode = read_tap_reg(OMAP_TAP_IDCODE);
430 hawkeye = (idcode >> 12) & 0xffff;
431 rev = (idcode >> 28) & 0xf;
434 * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
435 * Use ARM register to detect the correct ES version
437 if (!rev && (hawkeye != 0xb94e)) {
438 idcode = read_cpuid(CPUID_ID);
439 rev = (idcode & 0xf) - 1;
446 omap_revision = OMAP4430_REV_ES1_0;
450 omap_revision = OMAP4430_REV_ES2_0;
456 omap_revision = OMAP4430_REV_ES2_1;
460 omap_revision = OMAP4430_REV_ES2_2;
467 omap_revision = OMAP4460_REV_ES1_0;
472 /* Unknown default to latest silicon rev as default */
473 omap_revision = OMAP4430_REV_ES2_2;
476 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
477 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
478 (omap_rev() >> 8) & 0xf);
479 pr_info("%s %s\n", soc_name, soc_rev);
483 * Set up things for map_io and processor detection later on. Gets called
484 * pretty much first thing from board init. For multi-omap, this gets
485 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
486 * detect the exact revision later on in omap2_detect_revision() once map_io
489 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
491 omap_revision = omap2_globals->class;
492 tap_base = omap2_globals->tap;
494 if (cpu_is_omap34xx())
495 tap_prod_id = 0x0210;
497 tap_prod_id = 0x0208;
500 #ifdef CONFIG_SOC_BUS
502 static const char const *omap_types[] = {
503 [OMAP2_DEVICE_TYPE_TEST] = "TST",
504 [OMAP2_DEVICE_TYPE_EMU] = "EMU",
505 [OMAP2_DEVICE_TYPE_SEC] = "HS",
506 [OMAP2_DEVICE_TYPE_GP] = "GP",
507 [OMAP2_DEVICE_TYPE_BAD] = "BAD",
510 static const char * __init omap_get_family(void)
512 if (cpu_is_omap24xx())
513 return kasprintf(GFP_KERNEL, "OMAP2");
514 else if (cpu_is_omap34xx())
515 return kasprintf(GFP_KERNEL, "OMAP3");
516 else if (cpu_is_omap44xx())
517 return kasprintf(GFP_KERNEL, "OMAP4");
519 return kasprintf(GFP_KERNEL, "Unknown");
522 static ssize_t omap_get_type(struct device *dev,
523 struct device_attribute *attr,
526 return sprintf(buf, "%s\n", omap_types[omap_type()]);
529 static struct device_attribute omap_soc_attr =
530 __ATTR(type, S_IRUGO, omap_get_type, NULL);
532 int __init omap_soc_device_init(void)
534 struct device *parent;
535 struct soc_device *soc_dev;
536 struct soc_device_attribute *soc_dev_attr;
539 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
543 soc_dev_attr->machine = soc_name;
544 soc_dev_attr->family = omap_get_family();
545 soc_dev_attr->revision = soc_rev;
547 soc_dev = soc_device_register(soc_dev_attr);
548 if (IS_ERR_OR_NULL(soc_dev)) {
553 parent = soc_device_to_device(soc_dev);
554 if (!IS_ERR_OR_NULL(parent))
555 ret = device_create_file(parent, &omap_soc_attr);
559 late_initcall(omap_soc_device_init);
561 #endif /* CONFIG_SOC_BUS */