2 * linux/arch/arm/mach-omap2/id.c
4 * OMAP2 CPU identification code
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
22 #include <asm/cputype.h>
24 #include <plat/common.h>
25 #include <plat/control.h>
28 static struct omap_chip_id omap_chip;
29 static unsigned int omap_revision;
33 unsigned int omap_rev(void)
37 EXPORT_SYMBOL(omap_rev);
40 * omap_chip_is - test whether currently running OMAP matches a chip type
41 * @oc: omap_chip_t to test against
43 * Test whether the currently-running OMAP chip matches the supplied
44 * chip type 'oc'. Returns 1 upon a match; 0 upon failure.
46 int omap_chip_is(struct omap_chip_id oci)
48 return (oci.oc & omap_chip.oc) ? 1 : 0;
50 EXPORT_SYMBOL(omap_chip_is);
56 if (cpu_is_omap24xx()) {
57 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
58 } else if (cpu_is_omap34xx()) {
59 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
61 pr_err("Cannot detect omap type!\n");
65 val &= OMAP2_DEVICETYPE_MASK;
71 EXPORT_SYMBOL(omap_type);
74 /*----------------------------------------------------------------------------*/
76 #define OMAP_TAP_IDCODE 0x0204
77 #define OMAP_TAP_DIE_ID_0 0x0218
78 #define OMAP_TAP_DIE_ID_1 0x021C
79 #define OMAP_TAP_DIE_ID_2 0x0220
80 #define OMAP_TAP_DIE_ID_3 0x0224
82 #define read_tap_reg(reg) __raw_readl(tap_base + (reg))
85 u16 hawkeye; /* Silicon type (Hawkeye id) */
86 u8 dev; /* Device type from production_id reg */
87 u32 type; /* Combined type id copied to omap_revision */
90 /* Register values to detect the OMAP version */
91 static struct omap_id omap_ids[] __initdata = {
92 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
93 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
94 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
95 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
96 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
97 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
100 static void __iomem *tap_base;
101 static u16 tap_prod_id;
103 void __init omap24xx_check_revision(void)
110 idcode = read_tap_reg(OMAP_TAP_IDCODE);
111 prod_id = read_tap_reg(tap_prod_id);
112 hawkeye = (idcode >> 12) & 0xffff;
113 rev = (idcode >> 28) & 0x0f;
114 dev_type = (prod_id >> 16) & 0x0f;
116 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
117 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
118 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
119 read_tap_reg(OMAP_TAP_DIE_ID_0));
120 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
121 read_tap_reg(OMAP_TAP_DIE_ID_1),
122 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
123 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
124 read_tap_reg(OMAP_TAP_DIE_ID_2));
125 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
126 read_tap_reg(OMAP_TAP_DIE_ID_3));
127 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
130 /* Check hawkeye ids */
131 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
132 if (hawkeye == omap_ids[i].hawkeye)
136 if (i == ARRAY_SIZE(omap_ids)) {
137 printk(KERN_ERR "Unknown OMAP CPU id\n");
141 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
142 if (dev_type == omap_ids[j].dev)
146 if (j == ARRAY_SIZE(omap_ids)) {
147 printk(KERN_ERR "Unknown OMAP device type. "
148 "Handling it as OMAP%04x\n",
149 omap_ids[i].type >> 16);
153 pr_info("OMAP%04x", omap_rev() >> 16);
154 if ((omap_rev() >> 8) & 0x0f)
155 pr_info("ES%x", (omap_rev() >> 12) & 0xf);
159 #define OMAP3_CHECK_FEATURE(status,feat) \
160 if (((status & OMAP3_ ##feat## _MASK) \
161 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
162 omap3_features |= OMAP3_HAS_ ##feat; \
165 void __init omap3_check_features(void)
171 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
173 OMAP3_CHECK_FEATURE(status, L2CACHE);
174 OMAP3_CHECK_FEATURE(status, IVA);
175 OMAP3_CHECK_FEATURE(status, SGX);
176 OMAP3_CHECK_FEATURE(status, NEON);
177 OMAP3_CHECK_FEATURE(status, ISP);
180 * TODO: Get additional info (where applicable)
181 * e.g. Size of L2 cache.
185 void __init omap3_check_revision(void)
191 omap_chip.oc = CHIP_IS_OMAP3430;
194 * We cannot access revision registers on ES1.0.
195 * If the processor type is Cortex-A8 and the revision is 0x0
196 * it means its Cortex r0p0 which is 3430 ES1.0.
198 cpuid = read_cpuid(CPUID_ID);
199 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
200 omap_revision = OMAP3430_REV_ES1_0;
201 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
206 * Detection for 34xx ES2.0 and above can be done with just
207 * hawkeye and rev. See TRM 1.5.2 Device Identification.
208 * Note that rev does not map directly to our defined processor
209 * revision numbers as ES1.0 uses value 0.
211 idcode = read_tap_reg(OMAP_TAP_IDCODE);
212 hawkeye = (idcode >> 12) & 0xffff;
213 rev = (idcode >> 28) & 0xff;
217 /* Handle 34xx/35xx devices */
219 case 0: /* Take care of early samples */
221 omap_revision = OMAP3430_REV_ES2_0;
222 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
225 omap_revision = OMAP3430_REV_ES2_1;
226 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
229 omap_revision = OMAP3430_REV_ES3_0;
230 omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
233 omap_revision = OMAP3430_REV_ES3_1;
234 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
239 /* Use the latest known revision as default */
240 omap_revision = OMAP3430_REV_ES3_1_2;
242 /* REVISIT: Add CHIP_IS_OMAP3430ES3_1_2? */
243 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
247 /* Handle OMAP35xx/AM35xx devices
249 * Set the device to be OMAP3505 here. Actual device
250 * is identified later based on the features.
252 * REVISIT: AM3505/AM3517 should have their own CHIP_IS
254 omap_revision = OMAP3505_REV(rev);
255 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
260 /* Unknown default to latest silicon rev as default*/
261 omap_revision = OMAP3630_REV_ES1_0;
262 omap_chip.oc |= CHIP_IS_OMAP3630ES1;
266 void __init omap4_check_revision(void)
271 char *rev_name = "ES1.0";
274 * The IC rev detection is done with hawkeye and rev.
275 * Note that rev does not map directly to defined processor
276 * revision numbers as ES1.0 uses value 0.
278 idcode = read_tap_reg(OMAP_TAP_IDCODE);
279 hawkeye = (idcode >> 12) & 0xffff;
280 rev = (idcode >> 28) & 0xff;
282 if ((hawkeye == 0xb852) && (rev == 0x0)) {
283 omap_revision = OMAP4430_REV_ES1_0;
284 pr_info("OMAP%04x %s\n", omap_rev() >> 16, rev_name);
288 pr_err("Unknown OMAP4 CPU id\n");
291 #define OMAP3_SHOW_FEATURE(feat) \
292 if (omap3_has_ ##feat()) \
295 void __init omap3_cpuinfo(void)
297 u8 rev = GET_OMAP_REVISION();
298 char cpu_name[16], cpu_rev[16];
300 /* OMAP3430 and OMAP3530 are assumed to be same.
302 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
303 * on available features. Upon detection, update the CPU id
304 * and CPU class bits.
306 if (cpu_is_omap3630()) {
307 strcpy(cpu_name, "OMAP3630");
308 } else if (cpu_is_omap3505()) {
312 if (omap3_has_sgx()) {
313 omap_revision = OMAP3517_REV(rev);
314 strcpy(cpu_name, "AM3517");
316 /* Already set in omap3_check_revision() */
317 strcpy(cpu_name, "AM3505");
319 } else if (omap3_has_iva() && omap3_has_sgx()) {
320 /* OMAP3430, OMAP3525, OMAP3515, OMAP3503 devices */
321 strcpy(cpu_name, "OMAP3430/3530");
322 } else if (omap3_has_iva()) {
323 omap_revision = OMAP3525_REV(rev);
324 strcpy(cpu_name, "OMAP3525");
325 } else if (omap3_has_sgx()) {
326 omap_revision = OMAP3515_REV(rev);
327 strcpy(cpu_name, "OMAP3515");
329 omap_revision = OMAP3503_REV(rev);
330 strcpy(cpu_name, "OMAP3503");
334 case OMAP_REVBITS_00:
335 strcpy(cpu_rev, "1.0");
337 case OMAP_REVBITS_10:
338 strcpy(cpu_rev, "2.0");
340 case OMAP_REVBITS_20:
341 strcpy(cpu_rev, "2.1");
343 case OMAP_REVBITS_30:
344 strcpy(cpu_rev, "3.0");
346 case OMAP_REVBITS_40:
349 /* Use the latest known revision as default */
350 strcpy(cpu_rev, "3.1");
353 /* Print verbose information */
354 pr_info("%s ES%s (", cpu_name, cpu_rev);
356 OMAP3_SHOW_FEATURE(l2cache);
357 OMAP3_SHOW_FEATURE(iva);
358 OMAP3_SHOW_FEATURE(sgx);
359 OMAP3_SHOW_FEATURE(neon);
360 OMAP3_SHOW_FEATURE(isp);
366 * Try to detect the exact revision of the omap we're running on
368 void __init omap2_check_revision(void)
371 * At this point we have an idea about the processor revision set
372 * earlier with omap2_set_globals_tap().
374 if (cpu_is_omap24xx()) {
375 omap24xx_check_revision();
376 } else if (cpu_is_omap34xx()) {
377 omap3_check_revision();
378 omap3_check_features();
381 } else if (cpu_is_omap44xx()) {
382 omap4_check_revision();
385 pr_err("OMAP revision unknown, please fix!\n");
389 * OK, now we know the exact revision. Initialize omap_chip bits
390 * for powerdowmain and clockdomain code.
392 if (cpu_is_omap243x()) {
393 /* Currently only supports 2430ES2.1 and 2430-all */
394 omap_chip.oc |= CHIP_IS_OMAP2430;
396 } else if (cpu_is_omap242x()) {
397 /* Currently only supports 2420ES2.1.1 and 2420-all */
398 omap_chip.oc |= CHIP_IS_OMAP2420;
402 pr_err("Uninitialized omap_chip, please fix!\n");
406 * Set up things for map_io and processor detection later on. Gets called
407 * pretty much first thing from board init. For multi-omap, this gets
408 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
409 * detect the exact revision later on in omap2_detect_revision() once map_io
412 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
414 omap_revision = omap2_globals->class;
415 tap_base = omap2_globals->tap;
417 if (cpu_is_omap34xx())
418 tap_prod_id = 0x0210;
420 tap_prod_id = 0x0208;