2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/init.h>
21 #include <linux/err.h>
23 #include <asm/pgtable.h>
24 #include <asm/hardware/cache-l2x0.h>
25 #include <asm/mach/map.h>
27 #include <mach/common.h>
28 #include <mach/devices-common.h>
29 #include <mach/hardware.h>
30 #include <mach/iomux-v3.h>
31 #include <mach/irqs.h>
33 static void imx3_idle(void)
35 unsigned long reg = 0;
37 /* disable I and D cache */
38 "mrc p15, 0, %0, c1, c0, 0\n"
39 "bic %0, %0, #0x00001000\n"
40 "bic %0, %0, #0x00000004\n"
41 "mcr p15, 0, %0, c1, c0, 0\n"
42 /* invalidate I cache */
44 "mcr p15, 0, %0, c7, c5, 0\n"
45 /* clear and invalidate D cache */
47 "mcr p15, 0, %0, c7, c14, 0\n"
50 "mcr p15, 0, %0, c7, c0, 4\n"
51 "nop\n" "nop\n" "nop\n" "nop\n"
52 "nop\n" "nop\n" "nop\n"
53 /* enable I and D cache */
54 "mrc p15, 0, %0, c1, c0, 0\n"
55 "orr %0, %0, #0x00001000\n"
56 "orr %0, %0, #0x00000004\n"
57 "mcr p15, 0, %0, c1, c0, 0\n"
61 void imx3_init_l2x0(void)
63 void __iomem *l2x0_base;
64 void __iomem *clkctl_base;
67 * First of all, we must repair broken chip settings. There are some
68 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
69 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
70 * Workaraound is to setup the correct register setting prior enabling the
71 * L2 cache. This should not hurt already working CPUs, as they are using the
74 #define L2_MEM_VAL 0x10
76 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
77 if (clkctl_base != NULL) {
78 writel(0x00000515, clkctl_base + L2_MEM_VAL);
81 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
84 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
85 if (IS_ERR(l2x0_base)) {
86 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
91 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
94 static struct map_desc mx31_io_desc[] __initdata = {
95 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
96 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
97 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
98 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
99 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
103 * This function initializes the memory map. It is called during the
104 * system startup to create static physical to virtual memory mappings
105 * for the IO modules.
107 void __init mx31_map_io(void)
109 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
112 static struct map_desc mx35_io_desc[] __initdata = {
113 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
114 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
115 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
116 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
117 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
120 void __init mx35_map_io(void)
122 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
125 void __init imx31_init_early(void)
127 mxc_set_cpu_type(MXC_CPU_MX31);
128 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
129 imx_idle = imx3_idle;
132 void __init imx35_init_early(void)
134 mxc_set_cpu_type(MXC_CPU_MX35);
135 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
136 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
137 imx_idle = imx3_idle;
140 void __init mx31_init_irq(void)
142 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
145 void __init mx35_init_irq(void)
147 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
150 static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
151 .per_2_per_addr = 1677,
154 static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
157 .bp_2_ap_addr = 1029,
160 static struct sdma_platform_data imx31_sdma_pdata __initdata = {
161 .fw_name = "sdma-imx31-to2.bin",
162 .script_addrs = &imx31_to2_sdma_script,
165 void __init imx31_soc_init(void)
167 int to_version = mx31_revision() >> 4;
171 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
172 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
173 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
175 if (to_version == 1) {
176 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
177 strlen(imx31_sdma_pdata.fw_name));
178 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
181 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
184 static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
186 .uart_2_mcu_addr = 817,
187 .mcu_2_app_addr = 747,
188 .uartsh_2_mcu_addr = 1183,
189 .per_2_shp_addr = 1033,
190 .mcu_2_shp_addr = 961,
191 .ata_2_mcu_addr = 1333,
192 .mcu_2_ata_addr = 1252,
193 .app_2_mcu_addr = 683,
194 .shp_2_per_addr = 1111,
195 .shp_2_mcu_addr = 892,
198 static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
200 .uart_2_mcu_addr = 904,
201 .per_2_app_addr = 1597,
202 .mcu_2_app_addr = 834,
203 .uartsh_2_mcu_addr = 1270,
204 .per_2_shp_addr = 1120,
205 .mcu_2_shp_addr = 1048,
206 .ata_2_mcu_addr = 1429,
207 .mcu_2_ata_addr = 1339,
208 .app_2_per_addr = 1531,
209 .app_2_mcu_addr = 770,
210 .shp_2_per_addr = 1198,
211 .shp_2_mcu_addr = 979,
214 static struct sdma_platform_data imx35_sdma_pdata __initdata = {
215 .fw_name = "sdma-imx35-to2.bin",
216 .script_addrs = &imx35_to2_sdma_script,
219 void __init imx35_soc_init(void)
221 int to_version = mx35_revision() >> 4;
225 /* i.mx35 has the i.mx31 type gpio */
226 mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
227 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
228 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
230 if (to_version == 1) {
231 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
232 strlen(imx35_sdma_pdata.fw_name));
233 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
236 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);