arm/imx: remove cpu_is_xxx() from arch_idle()
authorShawn Guo <shawn.guo@linaro.org>
Wed, 28 Sep 2011 09:16:06 +0000 (17:16 +0800)
committerSascha Hauer <s.hauer@pengutronix.de>
Tue, 4 Oct 2011 08:55:06 +0000 (10:55 +0200)
This patch adds an idle hook imx_idle to be called in arch_idle().
Any soc that needs a customized idle implementation other than
cpu_do_idle() can set up this hook in soc specific call.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
arch/arm/mach-imx/mm-imx3.c
arch/arm/mach-imx/pm-imx27.c
arch/arm/mach-mx5/mm.c
arch/arm/mach-mx5/pm-imx5.c
arch/arm/mach-mx5/system.c
arch/arm/plat-mxc/include/mach/common.h
arch/arm/plat-mxc/include/mach/mxc.h
arch/arm/plat-mxc/include/mach/system.h
arch/arm/plat-mxc/system.c

index ffa33b4..6fad0d6 100644 (file)
 #include <mach/iomux-v3.h>
 #include <mach/irqs.h>
 
+static void imx3_idle(void)
+{
+       unsigned long reg = 0;
+       __asm__ __volatile__(
+               /* disable I and D cache */
+               "mrc p15, 0, %0, c1, c0, 0\n"
+               "bic %0, %0, #0x00001000\n"
+               "bic %0, %0, #0x00000004\n"
+               "mcr p15, 0, %0, c1, c0, 0\n"
+               /* invalidate I cache */
+               "mov %0, #0\n"
+               "mcr p15, 0, %0, c7, c5, 0\n"
+               /* clear and invalidate D cache */
+               "mov %0, #0\n"
+               "mcr p15, 0, %0, c7, c14, 0\n"
+               /* WFI */
+               "mov %0, #0\n"
+               "mcr p15, 0, %0, c7, c0, 4\n"
+               "nop\n" "nop\n" "nop\n" "nop\n"
+               "nop\n" "nop\n" "nop\n"
+               /* enable I and D cache */
+               "mrc p15, 0, %0, c1, c0, 0\n"
+               "orr %0, %0, #0x00001000\n"
+               "orr %0, %0, #0x00000004\n"
+               "mcr p15, 0, %0, c1, c0, 0\n"
+               : "=r" (reg));
+}
+
 void imx3_init_l2x0(void)
 {
        void __iomem *l2x0_base;
@@ -98,6 +126,7 @@ void __init imx31_init_early(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX31);
        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
+       imx_idle = imx3_idle;
 }
 
 void __init imx35_init_early(void)
@@ -105,6 +134,7 @@ void __init imx35_init_early(void)
        mxc_set_cpu_type(MXC_CPU_MX35);
        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
+       imx_idle = imx3_idle;
 }
 
 void __init mx31_init_irq(void)
index acf1769..e455d2f 100644 (file)
@@ -11,7 +11,7 @@
 #include <linux/suspend.h>
 #include <linux/io.h>
 #include <mach/system.h>
-#include <mach/mx27.h>
+#include <mach/hardware.h>
 
 static int mx27_suspend_enter(suspend_state_t state)
 {
index baea6e5..379593e 100644 (file)
 #include <mach/devices-common.h>
 #include <mach/iomux-v3.h>
 
+static void imx5_idle(void)
+{
+       mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+}
+
 /*
  * Define the MX51 memory map.
  */
@@ -56,6 +61,7 @@ void __init imx51_init_early(void)
        mxc_set_cpu_type(MXC_CPU_MX51);
        mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
        mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
+       imx_idle = imx5_idle;
 }
 
 void __init mx53_map_io(void)
index e4529af..0624fb8 100644 (file)
@@ -14,7 +14,8 @@
 #include <linux/err.h>
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
-#include <mach/system.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
 #include "crm_regs.h"
 
 static struct clk *gpc_dvfs_clk;
index 76ae8dc..144ebeb 100644 (file)
@@ -13,6 +13,7 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
+#include <mach/common.h>
 #include "crm_regs.h"
 
 /* set cpu low power mode before WFI instruction. This function is called
index 4e3d978..afaa967 100644 (file)
@@ -72,4 +72,15 @@ extern void mxc_arch_reset_init(void __iomem *);
 extern void mx51_efikamx_reset(void);
 extern int mx53_revision(void);
 extern int mx53_display_revision(void);
+
+enum mxc_cpu_pwr_mode {
+       WAIT_CLOCKED,           /* wfi only */
+       WAIT_UNCLOCKED,         /* WAIT */
+       WAIT_UNCLOCKED_POWER_OFF,       /* WAIT + SRPG */
+       STOP_POWER_ON,          /* just STOP */
+       STOP_POWER_OFF,         /* STOP + SRPG */
+};
+
+extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
+extern void (*imx_idle)(void);
 #endif
index 0987923..00a7819 100644 (file)
@@ -183,13 +183,6 @@ struct cpu_op {
 };
 
 int tzic_enable_wake(int is_idle);
-enum mxc_cpu_pwr_mode {
-       WAIT_CLOCKED,           /* wfi only */
-       WAIT_UNCLOCKED,         /* WAIT */
-       WAIT_UNCLOCKED_POWER_OFF,       /* WAIT + SRPG */
-       STOP_POWER_ON,          /* just STOP */
-       STOP_POWER_OFF,         /* STOP + SRPG */
-};
 
 extern struct cpu_op *(*get_cpu_op)(int *op);
 #endif
index 51f02a9..cf88b35 100644 (file)
 #ifndef __ASM_ARCH_MXC_SYSTEM_H__
 #define __ASM_ARCH_MXC_SYSTEM_H__
 
-#include <mach/hardware.h>
-#include <mach/common.h>
-
-extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
+extern void (*imx_idle)(void);
 
 static inline void arch_idle(void)
 {
-       /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
-       if (cpu_is_mx31() || cpu_is_mx35()) {
-               unsigned long reg = 0;
-               __asm__ __volatile__(
-                       /* disable I and D cache */
-                       "mrc p15, 0, %0, c1, c0, 0\n"
-                       "bic %0, %0, #0x00001000\n"
-                       "bic %0, %0, #0x00000004\n"
-                       "mcr p15, 0, %0, c1, c0, 0\n"
-                       /* invalidate I cache */
-                       "mov %0, #0\n"
-                       "mcr p15, 0, %0, c7, c5, 0\n"
-                       /* clear and invalidate D cache */
-                       "mov %0, #0\n"
-                       "mcr p15, 0, %0, c7, c14, 0\n"
-                       /* WFI */
-                       "mov %0, #0\n"
-                       "mcr p15, 0, %0, c7, c0, 4\n"
-                       "nop\n" "nop\n" "nop\n" "nop\n"
-                       "nop\n" "nop\n" "nop\n"
-                       /* enable I and D cache */
-                       "mrc p15, 0, %0, c1, c0, 0\n"
-                       "orr %0, %0, #0x00001000\n"
-                       "orr %0, %0, #0x00000004\n"
-                       "mcr p15, 0, %0, c1, c0, 0\n"
-                       : "=r" (reg));
-       } else if (cpu_is_mx51())
-               mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+       if (imx_idle != NULL)
+               (imx_idle)();
        else
                cpu_do_idle();
 }
index 8024f2a..5fa03e7 100644 (file)
@@ -28,6 +28,8 @@
 #include <asm/system.h>
 #include <asm/mach-types.h>
 
+void (*imx_idle)(void) = NULL;
+
 static void __iomem *wdog_base;
 
 /*