arch/arm/boot/dts/tegra20.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra20";
   5         interrupt-parent = <&intc>;
   6
   7         aliases {
   8                 serial0 = &uarta;
   9                 serial1 = &uartb;
  10                 serial2 = &uartc;
  11                 serial3 = &uartd;
  12                 serial4 = &uarte;
  13         };
  14
  15         host1x {
  16                 compatible = "nvidia,tegra20-host1x", "simple-bus";
  17                 reg = <0x50000000 0x00024000>;
  18                 interrupts = <0 65 0x04   /* mpcore syncpt */
  19                               0 67 0x04>; /* mpcore general */
  20                 clocks = <&tegra_car 28>;
  21
  22                 #address-cells = <1>;
  23                 #size-cells = <1>;
  24
  25                 ranges = <0x54000000 0x54000000 0x04000000>;
  26
  27                 mpe {
  28                         compatible = "nvidia,tegra20-mpe";
  29                         reg = <0x54040000 0x00040000>;
  30                         interrupts = <0 68 0x04>;
  31                         clocks = <&tegra_car 60>;
  32                 };
  33
  34                 vi {
  35                         compatible = "nvidia,tegra20-vi";
  36                         reg = <0x54080000 0x00040000>;
  37                         interrupts = <0 69 0x04>;
  38                         clocks = <&tegra_car 100>;
  39                 };
  40
  41                 epp {
  42                         compatible = "nvidia,tegra20-epp";
  43                         reg = <0x540c0000 0x00040000>;
  44                         interrupts = <0 70 0x04>;
  45                         clocks = <&tegra_car 19>;
  46                 };
  47
  48                 isp {
  49                         compatible = "nvidia,tegra20-isp";
  50                         reg = <0x54100000 0x00040000>;
  51                         interrupts = <0 71 0x04>;
  52                         clocks = <&tegra_car 23>;
  53                 };
  54
  55                 gr2d {
  56                         compatible = "nvidia,tegra20-gr2d";
  57                         reg = <0x54140000 0x00040000>;
  58                         interrupts = <0 72 0x04>;
  59                         clocks = <&tegra_car 21>;
  60                 };
  61
  62                 gr3d {
  63                         compatible = "nvidia,tegra20-gr3d";
  64                         reg = <0x54180000 0x00040000>;
  65                         clocks = <&tegra_car 24>;
  66                 };
  67
  68                 dc@54200000 {
  69                         compatible = "nvidia,tegra20-dc";
  70                         reg = <0x54200000 0x00040000>;
  71                         interrupts = <0 73 0x04>;
  72                         clocks = <&tegra_car 27>, <&tegra_car 121>;
  73                         clock-names = "disp1", "parent";
  74
  75                         rgb {
  76                                 status = "disabled";
  77                         };
  78                 };
  79
  80                 dc@54240000 {
  81                         compatible = "nvidia,tegra20-dc";
  82                         reg = <0x54240000 0x00040000>;
  83                         interrupts = <0 74 0x04>;
  84                         clocks = <&tegra_car 26>, <&tegra_car 121>;
  85                         clock-names = "disp2", "parent";
  86
  87                         rgb {
  88                                 status = "disabled";
  89                         };
  90                 };
  91
  92                 hdmi {
  93                         compatible = "nvidia,tegra20-hdmi";
  94                         reg = <0x54280000 0x00040000>;
  95                         interrupts = <0 75 0x04>;
  96                         clocks = <&tegra_car 51>, <&tegra_car 117>;
  97                         clock-names = "hdmi", "parent";
  98                         status = "disabled";
  99                 };
 100
 101                 tvo {
 102                         compatible = "nvidia,tegra20-tvo";
 103                         reg = <0x542c0000 0x00040000>;
 104                         interrupts = <0 76 0x04>;
 105                         clocks = <&tegra_car 102>;
 106                         status = "disabled";
 107                 };
 108
 109                 dsi {
 110                         compatible = "nvidia,tegra20-dsi";
 111                         reg = <0x54300000 0x00040000>;
 112                         clocks = <&tegra_car 48>;
 113                         status = "disabled";
 114                 };
 115         };
 116
 117         timer@50004600 {
 118                 compatible = "arm,cortex-a9-twd-timer";
 119                 reg = <0x50040600 0x20>;
 120                 interrupts = <1 13 0x304>;
 121         };
 122
 123         intc: interrupt-controller {
 124                 compatible = "arm,cortex-a9-gic";
 125                 reg = <0x50041000 0x1000
 126                        0x50040100 0x0100>;
 127                 interrupt-controller;
 128                 #interrupt-cells = <3>;
 129         };
 130
 131         cache-controller {
 132                 compatible = "arm,pl310-cache";
 133                 reg = <0x50043000 0x1000>;
 134                 arm,data-latency = <5 5 2>;
 135                 arm,tag-latency = <4 4 2>;
 136                 cache-unified;
 137                 cache-level = <2>;
 138         };
 139
 140         timer@60005000 {
 141                 compatible = "nvidia,tegra20-timer";
 142                 reg = <0x60005000 0x60>;
 143                 interrupts = <0 0 0x04
 144                               0 1 0x04
 145                               0 41 0x04
 146                               0 42 0x04>;
 147         };
 148
 149         tegra_car: clock {
 150                 compatible = "nvidia,tegra20-car";
 151                 reg = <0x60006000 0x1000>;
 152                 #clock-cells = <1>;
 153         };
 154
 155         apbdma: dma {
 156                 compatible = "nvidia,tegra20-apbdma";
 157                 reg = <0x6000a000 0x1200>;
 158                 interrupts = <0 104 0x04
 159                               0 105 0x04
 160                               0 106 0x04
 161                               0 107 0x04
 162                               0 108 0x04
 163                               0 109 0x04
 164                               0 110 0x04
 165                               0 111 0x04
 166                               0 112 0x04
 167                               0 113 0x04
 168                               0 114 0x04
 169                               0 115 0x04
 170                               0 116 0x04
 171                               0 117 0x04
 172                               0 118 0x04
 173                               0 119 0x04>;
 174                 clocks = <&tegra_car 34>;
 175         };
 176
 177         ahb {
 178                 compatible = "nvidia,tegra20-ahb";
 179                 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
 180         };
 181
 182         gpio: gpio {
 183                 compatible = "nvidia,tegra20-gpio";
 184                 reg = <0x6000d000 0x1000>;
 185                 interrupts = <0 32 0x04
 186                               0 33 0x04
 187                               0 34 0x04
 188                               0 35 0x04
 189                               0 55 0x04
 190                               0 87 0x04
 191                               0 89 0x04>;
 192                 #gpio-cells = <2>;
 193                 gpio-controller;
 194                 #interrupt-cells = <2>;
 195                 interrupt-controller;
 196         };
 197
 198         pinmux: pinmux {
 199                 compatible = "nvidia,tegra20-pinmux";
 200                 reg = <0x70000014 0x10   /* Tri-state registers */
 201                        0x70000080 0x20   /* Mux registers */
 202                        0x700000a0 0x14   /* Pull-up/down registers */
 203                        0x70000868 0xa8>; /* Pad control registers */
 204         };
 205
 206         das {
 207                 compatible = "nvidia,tegra20-das";
 208                 reg = <0x70000c00 0x80>;
 209         };
 210
 211         tegra_ac97: ac97 {
 212                 compatible = "nvidia,tegra20-ac97";
 213                 reg = <0x70002000 0x200>;
 214                 interrupts = <0 81 0x04>;
 215                 nvidia,dma-request-selector = <&apbdma 12>;
 216                 clocks = <&tegra_car 3>;
 217                 status = "disabled";
 218         };
 219
 220         tegra_i2s1: i2s@70002800 {
 221                 compatible = "nvidia,tegra20-i2s";
 222                 reg = <0x70002800 0x200>;
 223                 interrupts = <0 13 0x04>;
 224                 nvidia,dma-request-selector = <&apbdma 2>;
 225                 clocks = <&tegra_car 11>;
 226                 status = "disabled";
 227         };
 228
 229         tegra_i2s2: i2s@70002a00 {
 230                 compatible = "nvidia,tegra20-i2s";
 231                 reg = <0x70002a00 0x200>;
 232                 interrupts = <0 3 0x04>;
 233                 nvidia,dma-request-selector = <&apbdma 1>;
 234                 clocks = <&tegra_car 18>;
 235                 status = "disabled";
 236         };
 237
 238         /*
 239          * There are two serial driver i.e. 8250 based simple serial
 240          * driver and APB DMA based serial driver for higher baudrate
 241          * and performace. To enable the 8250 based driver, the compatible
 242          * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
 243          * driver, the comptible is "nvidia,tegra20-hsuart".
 244          */
 245         uarta: serial@70006000 {
 246                 compatible = "nvidia,tegra20-uart";
 247                 reg = <0x70006000 0x40>;
 248                 reg-shift = <2>;
 249                 interrupts = <0 36 0x04>;
 250                 nvidia,dma-request-selector = <&apbdma 8>;
 251                 clocks = <&tegra_car 6>;
 252                 status = "disabled";
 253         };
 254
 255         uartb: serial@70006040 {
 256                 compatible = "nvidia,tegra20-uart";
 257                 reg = <0x70006040 0x40>;
 258                 reg-shift = <2>;
 259                 interrupts = <0 37 0x04>;
 260                 nvidia,dma-request-selector = <&apbdma 9>;
 261                 clocks = <&tegra_car 96>;
 262                 status = "disabled";
 263         };
 264
 265         uartc: serial@70006200 {
 266                 compatible = "nvidia,tegra20-uart";
 267                 reg = <0x70006200 0x100>;
 268                 reg-shift = <2>;
 269                 interrupts = <0 46 0x04>;
 270                 nvidia,dma-request-selector = <&apbdma 10>;
 271                 clocks = <&tegra_car 55>;
 272                 status = "disabled";
 273         };
 274
 275         uartd: serial@70006300 {
 276                 compatible = "nvidia,tegra20-uart";
 277                 reg = <0x70006300 0x100>;
 278                 reg-shift = <2>;
 279                 interrupts = <0 90 0x04>;
 280                 nvidia,dma-request-selector = <&apbdma 19>;
 281                 clocks = <&tegra_car 65>;
 282                 status = "disabled";
 283         };
 284
 285         uarte: serial@70006400 {
 286                 compatible = "nvidia,tegra20-uart";
 287                 reg = <0x70006400 0x100>;
 288                 reg-shift = <2>;
 289                 interrupts = <0 91 0x04>;
 290                 nvidia,dma-request-selector = <&apbdma 20>;
 291                 clocks = <&tegra_car 66>;
 292                 status = "disabled";
 293         };
 294
 295         pwm: pwm {
 296                 compatible = "nvidia,tegra20-pwm";
 297                 reg = <0x7000a000 0x100>;
 298                 #pwm-cells = <2>;
 299                 clocks = <&tegra_car 17>;
 300         };
 301
 302         rtc {
 303                 compatible = "nvidia,tegra20-rtc";
 304                 reg = <0x7000e000 0x100>;
 305                 interrupts = <0 2 0x04>;
 306         };
 307
 308         i2c@7000c000 {
 309                 compatible = "nvidia,tegra20-i2c";
 310                 reg = <0x7000c000 0x100>;
 311                 interrupts = <0 38 0x04>;
 312                 #address-cells = <1>;
 313                 #size-cells = <0>;
 314                 clocks = <&tegra_car 12>, <&tegra_car 124>;
 315                 clock-names = "div-clk", "fast-clk";
 316                 status = "disabled";
 317         };
 318
 319         spi@7000c380 {
 320                 compatible = "nvidia,tegra20-sflash";
 321                 reg = <0x7000c380 0x80>;
 322                 interrupts = <0 39 0x04>;
 323                 nvidia,dma-request-selector = <&apbdma 11>;
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 clocks = <&tegra_car 43>;
 327                 status = "disabled";
 328         };
 329
 330         i2c@7000c400 {
 331                 compatible = "nvidia,tegra20-i2c";
 332                 reg = <0x7000c400 0x100>;
 333                 interrupts = <0 84 0x04>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 clocks = <&tegra_car 54>, <&tegra_car 124>;
 337                 clock-names = "div-clk", "fast-clk";
 338                 status = "disabled";
 339         };
 340
 341         i2c@7000c500 {
 342                 compatible = "nvidia,tegra20-i2c";
 343                 reg = <0x7000c500 0x100>;
 344                 interrupts = <0 92 0x04>;
 345                 #address-cells = <1>;
 346                 #size-cells = <0>;
 347                 clocks = <&tegra_car 67>, <&tegra_car 124>;
 348                 clock-names = "div-clk", "fast-clk";
 349                 status = "disabled";
 350         };
 351
 352         i2c@7000d000 {
 353                 compatible = "nvidia,tegra20-i2c-dvc";
 354                 reg = <0x7000d000 0x200>;
 355                 interrupts = <0 53 0x04>;
 356                 #address-cells = <1>;
 357                 #size-cells = <0>;
 358                 clocks = <&tegra_car 47>, <&tegra_car 124>;
 359                 clock-names = "div-clk", "fast-clk";
 360                 status = "disabled";
 361         };
 362
 363         spi@7000d400 {
 364                 compatible = "nvidia,tegra20-slink";
 365                 reg = <0x7000d400 0x200>;
 366                 interrupts = <0 59 0x04>;
 367                 nvidia,dma-request-selector = <&apbdma 15>;
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 clocks = <&tegra_car 41>;
 371                 status = "disabled";
 372         };
 373
 374         spi@7000d600 {
 375                 compatible = "nvidia,tegra20-slink";
 376                 reg = <0x7000d600 0x200>;
 377                 interrupts = <0 82 0x04>;
 378                 nvidia,dma-request-selector = <&apbdma 16>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 clocks = <&tegra_car 44>;
 382                 status = "disabled";
 383         };
 384
 385         spi@7000d800 {
 386                 compatible = "nvidia,tegra20-slink";
 387                 reg = <0x7000d480 0x200>;
 388                 interrupts = <0 83 0x04>;
 389                 nvidia,dma-request-selector = <&apbdma 17>;
 390                 #address-cells = <1>;
 391                 #size-cells = <0>;
 392                 clocks = <&tegra_car 46>;
 393                 status = "disabled";
 394         };
 395
 396         spi@7000da00 {
 397                 compatible = "nvidia,tegra20-slink";
 398                 reg = <0x7000da00 0x200>;
 399                 interrupts = <0 93 0x04>;
 400                 nvidia,dma-request-selector = <&apbdma 18>;
 401                 #address-cells = <1>;
 402                 #size-cells = <0>;
 403                 clocks = <&tegra_car 68>;
 404                 status = "disabled";
 405         };
 406
 407         pmc {
 408                 compatible = "nvidia,tegra20-pmc";
 409                 reg = <0x7000e400 0x400>;
 410         };
 411
 412         memory-controller@7000f000 {
 413                 compatible = "nvidia,tegra20-mc";
 414                 reg = <0x7000f000 0x024
 415                        0x7000f03c 0x3c4>;
 416                 interrupts = <0 77 0x04>;
 417         };
 418
 419         gart {
 420                 compatible = "nvidia,tegra20-gart";
 421                 reg = <0x7000f024 0x00000018    /* controller registers */
 422                        0x58000000 0x02000000>;  /* GART aperture */
 423         };
 424
 425         memory-controller@7000f400 {
 426                 compatible = "nvidia,tegra20-emc";
 427                 reg = <0x7000f400 0x200>;
 428                 #address-cells = <1>;
 429                 #size-cells = <0>;
 430         };
 431
 432         phy1: usb-phy@c5000400 {
 433                 compatible = "nvidia,tegra20-usb-phy";
 434                 reg = <0xc5000400 0x3c00>;
 435                 phy_type = "utmi";
 436                 nvidia,has-legacy-mode;
 437                 clocks = <&tegra_car 22>, <&tegra_car 127>;
 438                 clock-names = "phy", "pll_u";
 439         };
 440
 441         phy2: usb-phy@c5004400 {
 442                 compatible = "nvidia,tegra20-usb-phy";
 443                 reg = <0xc5004400 0x3c00>;
 444                 phy_type = "ulpi";
 445                 clocks = <&tegra_car 94>, <&tegra_car 127>;
 446                 clock-names = "phy", "pll_u";
 447         };
 448
 449         phy3: usb-phy@c5008400 {
 450                 compatible = "nvidia,tegra20-usb-phy";
 451                 reg = <0xc5008400 0x3C00>;
 452                 phy_type = "utmi";
 453                 clocks = <&tegra_car 22>, <&tegra_car 127>;
 454                 clock-names = "phy", "pll_u";
 455         };
 456
 457         usb@c5000000 {
 458                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 459                 reg = <0xc5000000 0x4000>;
 460                 interrupts = <0 20 0x04>;
 461                 phy_type = "utmi";
 462                 nvidia,has-legacy-mode;
 463                 clocks = <&tegra_car 22>;
 464                 nvidia,needs-double-reset;
 465                 nvidia,phy = <&phy1>;
 466                 status = "disabled";
 467         };
 468
 469         usb@c5004000 {
 470                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 471                 reg = <0xc5004000 0x4000>;
 472                 interrupts = <0 21 0x04>;
 473                 phy_type = "ulpi";
 474                 clocks = <&tegra_car 58>;
 475                 nvidia,phy = <&phy2>;
 476                 status = "disabled";
 477         };
 478
 479         usb@c5008000 {
 480                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 481                 reg = <0xc5008000 0x4000>;
 482                 interrupts = <0 97 0x04>;
 483                 phy_type = "utmi";
 484                 clocks = <&tegra_car 59>;
 485                 nvidia,phy = <&phy3>;
 486                 status = "disabled";
 487         };
 488
 489         sdhci@c8000000 {
 490                 compatible = "nvidia,tegra20-sdhci";
 491                 reg = <0xc8000000 0x200>;
 492                 interrupts = <0 14 0x04>;
 493                 clocks = <&tegra_car 14>;
 494                 status = "disabled";
 495         };
 496
 497         sdhci@c8000200 {
 498                 compatible = "nvidia,tegra20-sdhci";
 499                 reg = <0xc8000200 0x200>;
 500                 interrupts = <0 15 0x04>;
 501                 clocks = <&tegra_car 9>;
 502                 status = "disabled";
 503         };
 504
 505         sdhci@c8000400 {
 506                 compatible = "nvidia,tegra20-sdhci";
 507                 reg = <0xc8000400 0x200>;
 508                 interrupts = <0 19 0x04>;
 509                 clocks = <&tegra_car 69>;
 510                 status = "disabled";
 511         };
 512
 513         sdhci@c8000600 {
 514                 compatible = "nvidia,tegra20-sdhci";
 515                 reg = <0xc8000600 0x200>;
 516                 interrupts = <0 31 0x04>;
 517                 clocks = <&tegra_car 15>;
 518                 status = "disabled";
 519         };
 520
 521         cpus {
 522                 #address-cells = <1>;
 523                 #size-cells = <0>;
 524
 525                 cpu@0 {
 526                         device_type = "cpu";
 527                         compatible = "arm,cortex-a9";
 528                         reg = <0>;
 529                 };
 530
 531                 cpu@1 {
 532                         device_type = "cpu";
 533                         compatible = "arm,cortex-a9";
 534                         reg = <1>;
 535                 };
 536         };
 537
 538         pmu {
 539                 compatible = "arm,cortex-a9-pmu";
 540                 interrupts = <0 56 0x04
 541                               0 57 0x04>;
 542         };
 543 };