ARM: tegra: swap cache-/interrupt-ctrlr nodes in DT

This ensures nodes are sorted in order of reg address. This makes it
easier to compare against e.g. the U-Boot device trees, and is simply
consistent and clean.

While we're at it, remove the unit address from the cache-controller
node name, since it's unique without it.

Reported-by: Allen Martin <amartin@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 584596a..c4c0bb7 100644 (file)
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -120,15 +120,6 @@
                interrupts = <1 13 0x304>;
        };
 
-       cache-controller@50043000 {
-               compatible = "arm,pl310-cache";
-               reg = <0x50043000 0x1000>;
-               arm,data-latency = <5 5 2>;
-               arm,tag-latency = <4 4 2>;
-               cache-unified;
-               cache-level = <2>;
-       };
-
        intc: interrupt-controller {
                compatible = "arm,cortex-a9-gic";
                reg = <0x50041000 0x1000
@@ -137,6 +128,15 @@
                #interrupt-cells = <3>;
        };
 
+       cache-controller {
+               compatible = "arm,pl310-cache";
+               reg = <0x50043000 0x1000>;
+               arm,data-latency = <5 5 2>;
+               arm,tag-latency = <4 4 2>;
+               cache-unified;
+               cache-level = <2>;
+       };
+
        timer@60005000 {
                compatible = "nvidia,tegra20-timer";
                reg = <0x60005000 0x60>;

diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index e55c991..a67fc13 100644 (file)
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -121,15 +121,6 @@
                interrupts = <1 13 0xf04>;
        };
 
-       cache-controller@50043000 {
-               compatible = "arm,pl310-cache";
-               reg = <0x50043000 0x1000>;
-               arm,data-latency = <6 6 2>;
-               arm,tag-latency = <5 5 2>;
-               cache-unified;
-               cache-level = <2>;
-       };
-
        intc: interrupt-controller {
                compatible = "arm,cortex-a9-gic";
                reg = <0x50041000 0x1000
@@ -138,6 +129,15 @@
                #interrupt-cells = <3>;
        };
 
+       cache-controller {
+               compatible = "arm,pl310-cache";
+               reg = <0x50043000 0x1000>;
+               arm,data-latency = <6 6 2>;
+               arm,tag-latency = <5 5 2>;
+               cache-unified;
+               cache-level = <2>;
+       };
+
        timer@60005000 {
                compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
                reg = <0x60005000 0x400>;