{
PVR_DPF((PVR_DBG_MESSAGE, "SysDevicePrePowerState: SGX Entering state D3"));
DisableSGXClocks(gpsSysData);
+ PVRSRVSetDCState(DC_STATE_SUSPEND_COMMANDS);
}
#else
PVR_UNREFERENCED_PARAMETER(eNewPowerState );
if (eCurrentPowerState == PVRSRV_POWER_STATE_D3)
{
PVR_DPF((PVR_DBG_MESSAGE, "SysDevicePostPowerState: SGX Leaving state D3"));
+ PVRSRVSetDCState(DC_STATE_RESUME_COMMANDS);
eError = EnableSGXClocks(gpsSysData);
}
#else
#define SYS_OMAP3430_VDD2_OPP2_SGX_CLOCK_SPEED (SYS_SGX_CLOCK_SPEED / 2)
#define SYS_OMAP3430_SGX_REGS_SYS_PHYS_BASE 0x50000000
-#define SYS_OMAP3430_SGX_REGS_SIZE 0x4000
+#define SYS_OMAP3430_SGX_REGS_SIZE 0x10000
#define SYS_OMAP3430_SGX_IRQ 21
#define SGX_PARENT_CLOCK "core_ck"
#endif
+#undef SYS_SGX_CLOCK_SPEED
+#define SYS_SGX_CLOCK_SPEED sgx_clock_speed
+static int sgx_clock_speed;
+
#if !defined(PDUMP) && !defined(NO_HARDWARE)
static IMG_BOOL PowerLockWrappedOnCPU(SYS_SPECIFIC_DATA *psSysSpecData)
{
{
bPowerLock = IMG_FALSE;
+ sgx_clock_speed = cpu_is_omap3630() ? 200000000 : 110666666;
+
spin_lock_init(&psSysSpecData->sPowerLock);
atomic_set(&psSysSpecData->sPowerLockCPU, -1);
spin_lock_init(&psSysSpecData->sNotifyLock);