pvr/sgxinfokm.h

   1 /**********************************************************************
   2  *
   3  * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful but, except
  10  * as otherwise stated in writing, without any warranty; without even the
  11  * implied warranty of merchantability or fitness for a particular purpose.
  12  * See the GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * Imagination Technologies Ltd. <gpl-support@imgtec.com>
  23  * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
  24  *
  25  ******************************************************************************/
  26
  27 #ifndef __SGXINFOKM_H__
  28 #define __SGXINFOKM_H__
  29
  30 #include <linux/workqueue.h>
  31 #include "sgxdefs.h"
  32 #include "device.h"
  33 #include "sysconfig.h"
  34 #include "sgxscript.h"
  35 #include "sgxinfo.h"
  36
  37
  38 #define SGX_HOSTPORT_PRESENT                                    0x00000001UL
  39
  40 #define PVRSRV_USSE_EDM_POWMAN_IDLE_COMPLETE                    (1UL << 2)
  41 #define PVRSRV_USSE_EDM_POWMAN_POWEROFF_COMPLETE                (1UL << 3)
  42 #define PVRSRV_USSE_EDM_POWMAN_POWEROFF_RESTART_IMMEDIATE       (1UL << 4)
  43 #define PVRSRV_USSE_EDM_POWMAN_NO_WORK                          (1UL << 5)
  44
  45 #define PVRSRV_USSE_EDM_INTERRUPT_HWR                           (1UL << 0)
  46 #define PVRSRV_USSE_EDM_INTERRUPT_ACTIVE_POWER                  (1UL << 1)
  47
  48 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_RT_REQUEST               0x01UL
  49 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_RC_REQUEST               0x02UL
  50 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_TC_REQUEST               0x04UL
  51 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_2DC_REQUEST              0x08UL
  52 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_SHAREDPBDESC             0x10UL
  53 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_INVALPD                  0x20UL
  54 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_INVALPT                  0x40UL
  55 #define PVRSRV_USSE_EDM_RESMAN_CLEANUP_COMPLETE                 0x80UL
  56
  57 #define PVRSRV_USSE_MISCINFO_READY                              0x1UL
  58
  59 struct PVRSRV_SGX_CCB_INFO;
  60
  61 struct PVRSRV_SGXDEV_INFO {
  62         enum PVRSRV_DEVICE_TYPE eDeviceType;
  63         enum PVRSRV_DEVICE_CLASS eDeviceClass;
  64
  65         u8 ui8VersionMajor;
  66         u8 ui8VersionMinor;
  67         u32 ui32CoreConfig;
  68         u32 ui32CoreFlags;
  69
  70         void __iomem *pvRegsBaseKM;
  71
  72         void *hRegMapping;
  73
  74         struct IMG_SYS_PHYADDR sRegsPhysBase;
  75
  76         u32 ui32RegSize;
  77
  78         u32 ui32CoreClockSpeed;
  79         u32 ui32uKernelTimerClock;
  80
  81         void *psStubPBDescListKM;
  82
  83         struct IMG_DEV_PHYADDR sKernelPDDevPAddr;
  84
  85         void *pvDeviceMemoryHeap;
  86         struct PVRSRV_KERNEL_MEM_INFO *psKernelCCBMemInfo;
  87         struct PVRSRV_SGX_KERNEL_CCB *psKernelCCB;
  88         struct PVRSRV_SGX_CCB_INFO *psKernelCCBInfo;
  89         struct PVRSRV_KERNEL_MEM_INFO *psKernelCCBCtlMemInfo;
  90         struct PVRSRV_SGX_CCB_CTL *psKernelCCBCtl;
  91         struct PVRSRV_KERNEL_MEM_INFO *psKernelCCBEventKickerMemInfo;
  92         u32 *pui32KernelCCBEventKicker;
  93         struct PVRSRV_KERNEL_MEM_INFO *psKernelSGXMiscMemInfo;
  94         u32 ui32HostKickAddress;
  95         u32 ui32GetMiscInfoAddress;
  96         u32 ui32KickTACounter;
  97         u32 ui32KickTARenderCounter;
  98         struct PVRSRV_KERNEL_MEM_INFO *psKernelHWPerfCBMemInfo;
  99         struct PVRSRV_SGXDEV_DIFF_INFO sDiffInfo;
 100         u32 ui32HWGroupRequested;
 101         u32 ui32HWReset;
 102 #ifdef PVRSRV_USSE_EDM_STATUS_DEBUG
 103         /*!< Meminfo for EDM status buffer */
 104         struct PVRSRV_KERNEL_MEM_INFO *psKernelEDMStatusBufferMemInfo;
 105 #endif
 106
 107         u32 ui32ClientRefCount;
 108
 109         u32 ui32CacheControl;
 110
 111         void *pvMMUContextList;
 112
 113         IMG_BOOL bForcePTOff;
 114
 115         u32 ui32EDMTaskReg0;
 116         u32 ui32EDMTaskReg1;
 117
 118         u32 ui32ClkGateStatusReg;
 119         u32 ui32ClkGateStatusMask;
 120         struct SGX_INIT_SCRIPTS sScripts;
 121
 122         void *hBIFResetPDOSMemHandle;
 123         struct IMG_DEV_PHYADDR sBIFResetPDDevPAddr;
 124         struct IMG_DEV_PHYADDR sBIFResetPTDevPAddr;
 125         struct IMG_DEV_PHYADDR sBIFResetPageDevPAddr;
 126         u32 *pui32BIFResetPD;
 127         u32 *pui32BIFResetPT;
 128
 129         void *hTimer;
 130         u32 ui32TimeStamp;
 131         u32 ui32NumResets;
 132
 133         unsigned long long last_idle;
 134         unsigned long long burst_start;
 135         int burst_size;
 136         int burst_cnt;
 137         int power_down_delay;
 138
 139         struct PVRSRV_KERNEL_MEM_INFO *psKernelSGXHostCtlMemInfo;
 140         struct SGXMKIF_HOST_CTL __iomem *psSGXHostCtl;
 141
 142         struct PVRSRV_KERNEL_MEM_INFO *psKernelSGXTA3DCtlMemInfo;
 143
 144         u32 ui32Flags;
 145
 146 #if defined(PDUMP)
 147         struct PVRSRV_SGX_PDUMP_CONTEXT sPDContext;
 148 #endif
 149
 150
 151         u32 asSGXDevData[SGX_MAX_DEV_DATA];
 152
 153         u32 state_buf_ofs;
 154 };
 155
 156 struct SGX_TIMING_INFORMATION {
 157         u32 ui32CoreClockSpeed;
 158         u32 ui32HWRecoveryFreq;
 159         u32 ui32ActivePowManLatencyms;
 160         u32 ui32uKernelFreq;
 161 };
 162
 163 struct SGX_DEVICE_MAP {
 164         u32 ui32Flags;
 165
 166         struct IMG_SYS_PHYADDR sRegsSysPBase;
 167         struct IMG_CPU_PHYADDR sRegsCpuPBase;
 168         void __iomem *pvRegsCpuVBase;
 169         u32 ui32RegsSize;
 170
 171         struct IMG_SYS_PHYADDR sLocalMemSysPBase;
 172         struct IMG_DEV_PHYADDR sLocalMemDevPBase;
 173         struct IMG_CPU_PHYADDR sLocalMemCpuPBase;
 174         u32 ui32LocalMemSize;
 175
 176         u32 ui32IRQ;
 177 };
 178
 179 struct PVRSRV_STUB_PBDESC;
 180 struct PVRSRV_STUB_PBDESC {
 181         u32 ui32RefCount;
 182         u32 ui32TotalPBSize;
 183         struct PVRSRV_KERNEL_MEM_INFO *psSharedPBDescKernelMemInfo;
 184         struct PVRSRV_KERNEL_MEM_INFO *psHWPBDescKernelMemInfo;
 185         struct PVRSRV_KERNEL_MEM_INFO **ppsSubKernelMemInfos;
 186         u32 ui32SubKernelMemInfosCount;
 187         void *hDevCookie;
 188         struct PVRSRV_KERNEL_MEM_INFO *psBlockKernelMemInfo;
 189         struct PVRSRV_STUB_PBDESC *psNext;
 190 };
 191
 192 struct PVRSRV_SGX_CCB_INFO {
 193         struct PVRSRV_KERNEL_MEM_INFO *psCCBMemInfo;
 194         struct PVRSRV_KERNEL_MEM_INFO *psCCBCtlMemInfo;
 195         struct SGXMKIF_COMMAND *psCommands;
 196         u32 *pui32WriteOffset;
 197         volatile u32 *pui32ReadOffset;
 198 #if defined(PDUMP)
 199         u32 ui32CCBDumpWOff;
 200 #endif
 201 };
 202
 203 struct timer_work_data {
 204         struct PVRSRV_DEVICE_NODE *psDeviceNode;
 205         struct delayed_work work;
 206         struct workqueue_struct *work_queue;
 207         unsigned int interval;
 208         bool armed;
 209 };
 210
 211 enum PVRSRV_ERROR SGXRegisterDevice(struct PVRSRV_DEVICE_NODE *psDeviceNode);
 212 enum PVRSRV_ERROR SGXOSTimerEnable(struct timer_work_data *data);
 213 enum PVRSRV_ERROR SGXOSTimerCancel(struct timer_work_data *data);
 214 struct timer_work_data *
 215 SGXOSTimerInit(struct PVRSRV_DEVICE_NODE *psDeviceNode);
 216 void SGXOSTimerDeInit(struct timer_work_data *data);
 217
 218 void HWRecoveryResetSGX(struct PVRSRV_DEVICE_NODE *psDeviceNode,
 219                         const char *caller);
 220 void SGXReset(struct PVRSRV_SGXDEV_INFO *psDevInfo, u32 ui32PDUMPFlags);
 221
 222 enum PVRSRV_ERROR SGXInitialise(struct PVRSRV_SGXDEV_INFO *psDevInfo,
 223                                 IMG_BOOL bHardwareRecovery);
 224 enum PVRSRV_ERROR SGXDeinitialise(void *hDevCookie);
 225
 226 void sgx_mark_new_command(struct PVRSRV_DEVICE_NODE *node);
 227 void sgx_mark_power_down(struct PVRSRV_DEVICE_NODE *node);
 228
 229 void SGXStartTimer(struct PVRSRV_SGXDEV_INFO *psDevInfo,
 230                    IMG_BOOL bStartOSTimer);
 231
 232 enum PVRSRV_ERROR SGXPrePowerStateExt(void *hDevHandle,
 233                                       enum PVR_POWER_STATE eNewPowerState,
 234                                       enum PVR_POWER_STATE eCurrentPowerState);
 235
 236 enum PVRSRV_ERROR SGXPostPowerStateExt(void *hDevHandle,
 237                                        enum PVR_POWER_STATE eNewPowerState,
 238                                        enum PVR_POWER_STATE eCurrentPowerState);
 239
 240 enum PVRSRV_ERROR SGXPreClockSpeedChange(void *hDevHandle,
 241                                          IMG_BOOL bIdleDevice,
 242                                          enum PVR_POWER_STATE
 243                                          eCurrentPowerState);
 244
 245 enum PVRSRV_ERROR SGXPostClockSpeedChange(void *hDevHandle,
 246                                           IMG_BOOL bIdleDevice,
 247                                           enum PVR_POWER_STATE
 248                                           eCurrentPowerState);
 249
 250 enum PVRSRV_ERROR SGXDevInitCompatCheck(struct PVRSRV_DEVICE_NODE
 251                                         *psDeviceNode);
 252
 253 void SysGetSGXTimingInformation(struct SGX_TIMING_INFORMATION *psSGXTimingInfo);
 254
 255 #if defined(NO_HARDWARE)
 256 static inline void NoHardwareGenerateEvent(struct PVRSRV_SGXDEV_INFO *psDevInfo,
 257                                            u32 ui32StatusRegister,
 258                                            u32 ui32StatusValue,
 259                                            u32 ui32StatusMask)
 260 {
 261         u32 ui32RegVal;
 262
 263         ui32RegVal = OSReadHWReg(psDevInfo->pvRegsBaseKM, ui32StatusRegister);
 264
 265         ui32RegVal &= ~ui32StatusMask;
 266         ui32RegVal |= (ui32StatusValue & ui32StatusMask);
 267
 268         OSWriteHWReg(psDevInfo->pvRegsBaseKM, ui32StatusRegister, ui32RegVal);
 269 }
 270 #endif
 271
 272 #endif