pvr/sgxinfo.h

   1 /**********************************************************************
   2  *
   3  * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful but, except
  10  * as otherwise stated in writing, without any warranty; without even the
  11  * implied warranty of merchantability or fitness for a particular purpose.
  12  * See the GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  * The full GNU General Public License is included in this distribution in
  19  * the file called "COPYING".
  20  *
  21  * Contact Information:
  22  * Imagination Technologies Ltd. <gpl-support@imgtec.com>
  23  * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
  24  *
  25  ******************************************************************************/
  26
  27 #if !defined(__SGXINFO_H__)
  28 #define __SGXINFO_H__
  29
  30 #include "sgxscript.h"
  31
  32 #include "servicesint.h"
  33
  34 #include "services.h"
  35 #include "sgxapi_km.h"
  36
  37 #define SGX_MP_CORE_SELECT(x, i)        (x)
  38
  39 #define SGX_MAX_DEV_DATA                24
  40 #define SGX_MAX_INIT_MEM_HANDLES        16
  41
  42 #define SGX_BIF_DIR_LIST_INDEX_EDM      0
  43
  44 struct SGX_BRIDGE_INFO_FOR_SRVINIT {
  45         struct IMG_DEV_PHYADDR sPDDevPAddr;
  46         struct PVRSRV_HEAP_INFO asHeapInfo[PVRSRV_MAX_CLIENT_HEAPS];
  47 };
  48
  49 struct SGX_BRIDGE_INIT_INFO {
  50         void *hKernelCCBMemInfo;
  51         void *hKernelCCBCtlMemInfo;
  52         void *hKernelCCBEventKickerMemInfo;
  53         void *hKernelSGXHostCtlMemInfo;
  54         void *hKernelSGXTA3DCtlMemInfo;
  55         void *hKernelSGXMiscMemInfo;
  56         u32 ui32HostKickAddress;
  57         u32 ui32GetMiscInfoAddress;
  58         void *hKernelHWPerfCBMemInfo;
  59         void *hKernelEDMStatusBufferMemInfo;
  60
  61         u32 ui32EDMTaskReg0;
  62         u32 ui32EDMTaskReg1;
  63
  64         u32 ui32ClkGateStatusReg;
  65         u32 ui32ClkGateStatusMask;
  66
  67         u32 ui32CacheControl;
  68
  69         u32 asInitDevData[SGX_MAX_DEV_DATA];
  70         void *asInitMemHandles[SGX_MAX_INIT_MEM_HANDLES];
  71
  72         struct SGX_INIT_SCRIPTS sScripts;
  73
  74         u32 state_buf_ofs;
  75 };
  76
  77 struct SGXMKIF_COMMAND {
  78         u32 ui32ServiceAddress;
  79         u32 ui32Data[3];
  80 };
  81
  82 struct PVRSRV_SGX_KERNEL_CCB {
  83         struct SGXMKIF_COMMAND asCommands[256];
  84 };
  85
  86 struct PVRSRV_SGX_CCB_CTL {
  87         u32 ui32WriteOffset;
  88         u32 ui32ReadOffset;
  89 };
  90
  91 #define SGX_AUXCCBFLAGS_SHARED                                  0x00000001
  92
  93 enum SGXMKIF_COMMAND_TYPE {
  94         SGXMKIF_COMMAND_EDM_KICK = 0,
  95         SGXMKIF_COMMAND_VIDEO_KICK = 1,
  96         SGXMKIF_COMMAND_REQUEST_SGXMISCINFO = 2,
  97
  98         SGXMKIF_COMMAND_FORCE_I32 = -1,
  99
 100 };
 101
 102 #define PVRSRV_CCBFLAGS_RASTERCMD                       0x1
 103 #define PVRSRV_CCBFLAGS_TRANSFERCMD                     0x2
 104 #define PVRSRV_CCBFLAGS_PROCESS_QUEUESCMD               0x3
 105 #define PVRSRV_CCBFLAGS_POWERCMD                        0x5
 106
 107 #define PVRSRV_POWERCMD_POWEROFF                        0x1
 108 #define PVRSRV_POWERCMD_IDLE                            0x2
 109
 110 #define SGX_BIF_INVALIDATE_PTCACHE                      0x1
 111 #define SGX_BIF_INVALIDATE_PDCACHE                      0x2
 112
 113 struct SGXMKIF_HWDEVICE_SYNC_LIST {
 114         struct IMG_DEV_VIRTADDR sAccessDevAddr;
 115         u32 ui32NumSyncObjects;
 116
 117         struct PVRSRV_DEVICE_SYNC_OBJECT asSyncData[1];
 118 };
 119
 120 struct SGX_DEVICE_SYNC_LIST {
 121         struct SGXMKIF_HWDEVICE_SYNC_LIST *psHWDeviceSyncList;
 122
 123         void *hKernelHWSyncListMemInfo;
 124         struct PVRSRV_CLIENT_MEM_INFO *psHWDeviceSyncListClientMemInfo;
 125         struct PVRSRV_CLIENT_MEM_INFO *psAccessResourceClientMemInfo;
 126
 127         volatile u32 *pui32Lock;
 128
 129         struct SGX_DEVICE_SYNC_LIST *psNext;
 130
 131         u32 ui32NumSyncObjects;
 132         void *ahSyncHandles[1];
 133 };
 134
 135 struct SGX_INTERNEL_STATUS_UPDATE {
 136         struct CTL_STATUS sCtlStatus;
 137         void *hKernelMemInfo;
 138         /* pdump specific - required? */
 139         u32 ui32LastStatusUpdateDumpVal;
 140 };
 141
 142 struct SGX_CCB_KICK {
 143         enum SGXMKIF_COMMAND_TYPE eCommand;
 144         struct SGXMKIF_COMMAND sCommand;
 145         void *hCCBKernelMemInfo;
 146
 147         u32 ui32NumDstSyncObjects;
 148         void *hKernelHWSyncListMemInfo;
 149         void *sDstSyncHandle;
 150
 151         u32 ui32NumTAStatusVals;
 152         u32 ui32Num3DStatusVals;
 153
 154         void *ahTAStatusSyncInfo[SGX_MAX_TA_STATUS_VALS];
 155         void *ah3DStatusSyncInfo[SGX_MAX_3D_STATUS_VALS];
 156
 157         IMG_BOOL bFirstKickOrResume;
 158 #if (defined(NO_HARDWARE) || defined(PDUMP))
 159         IMG_BOOL bTerminateOrAbort;
 160 #endif
 161         IMG_BOOL bKickRender;
 162
 163         u32 ui32CCBOffset;
 164
 165         u32 ui32NumSrcSyncs;
 166         void *ahSrcKernelSyncInfo[SGX_MAX_SRC_SYNCS];
 167
 168         IMG_BOOL bTADependency;
 169         void *hTA3DSyncInfo;
 170
 171         void *hTASyncInfo;
 172         void *h3DSyncInfo;
 173 #if defined(PDUMP)
 174         u32 ui32CCBDumpWOff;
 175 #endif
 176 #if defined(NO_HARDWARE)
 177         u32 ui32WriteOpsPendingVal;
 178 #endif
 179 };
 180
 181 #define SGX_KERNEL_USE_CODE_BASE_INDEX          15
 182
 183 struct SGXMKIF_HOST_CTL {
 184
 185         u32 ui32PowerStatus;
 186         u32 ui32uKernelDetectedLockups;
 187         u32 ui32HostDetectedLockups;
 188         u32 ui32HWRecoverySampleRate;
 189         u32 ui32ActivePowManSampleRate;
 190         u32 ui32InterruptFlags;
 191         u32 ui32InterruptClearFlags;
 192
 193         u32 ui32ResManFlags;
 194         struct IMG_DEV_VIRTADDR sResManCleanupData;
 195
 196         u32 ui32NumActivePowerEvents;
 197
 198         u32 ui32HWPerfFlags;
 199
 200         /* !< See SGXMK_STATUS_BUFFER */
 201         struct IMG_DEV_VIRTADDR sEDMStatusBuffer;
 202
 203         /*< to count time wraps in the Timer task */
 204         u32 ui32TimeWraps;
 205
 206         u32 render_state_buf_ta_handle;
 207         u32 render_state_buf_3d_handle;
 208 };
 209
 210 struct SGX_CLIENT_INFO {
 211         u32 ui32ProcessID;
 212         void *pvProcess;
 213         struct PVRSRV_MISC_INFO sMiscInfo;
 214
 215         u32 asDevData[SGX_MAX_DEV_DATA];
 216
 217 };
 218
 219 struct SGX_INTERNAL_DEVINFO {
 220         u32 ui32Flags;
 221         void *hHostCtlKernelMemInfoHandle;
 222         IMG_BOOL bForcePTOff;
 223 };
 224
 225 #define SGXTQ_MAX_STATUS                (SGX_MAX_TRANSFER_STATUS_VALS + 2)
 226
 227 #define SGXMKIF_TQFLAGS_NOSYNCUPDATE                            0x00000001
 228 #define SGXMKIF_TQFLAGS_KEEPPENDING                             0x00000002
 229 #define SGXMKIF_TQFLAGS_TATQ_SYNC                               0x00000004
 230 #define SGXMKIF_TQFLAGS_3DTQ_SYNC                               0x00000008
 231 struct SGXMKIF_CMDTA_SHARED {
 232         u32 ui32NumTAStatusVals;
 233         u32 ui32Num3DStatusVals;
 234
 235         u32 ui32TATQSyncWriteOpsPendingVal;
 236         struct IMG_DEV_VIRTADDR sTATQSyncWriteOpsCompleteDevVAddr;
 237         u32 ui32TATQSyncReadOpsPendingVal;
 238         struct IMG_DEV_VIRTADDR sTATQSyncReadOpsCompleteDevVAddr;
 239
 240         u32 ui323DTQSyncWriteOpsPendingVal;
 241         struct IMG_DEV_VIRTADDR s3DTQSyncWriteOpsCompleteDevVAddr;
 242         u32 ui323DTQSyncReadOpsPendingVal;
 243         struct IMG_DEV_VIRTADDR s3DTQSyncReadOpsCompleteDevVAddr;
 244
 245         u32 ui32NumSrcSyncs;
 246         struct PVRSRV_DEVICE_SYNC_OBJECT asSrcSyncs[SGX_MAX_SRC_SYNCS];
 247
 248         struct CTL_STATUS sCtlTAStatusInfo[SGX_MAX_TA_STATUS_VALS];
 249         struct CTL_STATUS sCtl3DStatusInfo[SGX_MAX_3D_STATUS_VALS];
 250
 251         struct PVRSRV_DEVICE_SYNC_OBJECT sTA3DDependency;
 252
 253 };
 254
 255 struct SGXMKIF_TRANSFERCMD_SHARED {
 256
 257         u32 ui32SrcReadOpPendingVal;
 258         struct IMG_DEV_VIRTADDR sSrcReadOpsCompleteDevAddr;
 259
 260         u32 ui32SrcWriteOpPendingVal;
 261         struct IMG_DEV_VIRTADDR sSrcWriteOpsCompleteDevAddr;
 262
 263         u32 ui32DstReadOpPendingVal;
 264         struct IMG_DEV_VIRTADDR sDstReadOpsCompleteDevAddr;
 265
 266         u32 ui32DstWriteOpPendingVal;
 267         struct IMG_DEV_VIRTADDR sDstWriteOpsCompleteDevAddr;
 268
 269         u32 ui32TASyncWriteOpsPendingVal;
 270         struct IMG_DEV_VIRTADDR sTASyncWriteOpsCompleteDevVAddr;
 271         u32 ui32TASyncReadOpsPendingVal;
 272         struct IMG_DEV_VIRTADDR sTASyncReadOpsCompleteDevVAddr;
 273
 274         u32 ui323DSyncWriteOpsPendingVal;
 275         struct IMG_DEV_VIRTADDR s3DSyncWriteOpsCompleteDevVAddr;
 276         u32 ui323DSyncReadOpsPendingVal;
 277         struct IMG_DEV_VIRTADDR s3DSyncReadOpsCompleteDevVAddr;
 278
 279         u32 ui32NumStatusVals;
 280         struct CTL_STATUS sCtlStatusInfo[SGXTQ_MAX_STATUS];
 281 };
 282
 283 struct PVRSRV_TRANSFER_SGX_KICK {
 284         void *hCCBMemInfo;
 285         u32 ui32SharedCmdCCBOffset;
 286
 287         struct IMG_DEV_VIRTADDR sHWTransferContextDevVAddr;
 288
 289         void *hTASyncInfo;
 290         void *h3DSyncInfo;
 291
 292         u32 ui32NumSrcSync;
 293         void *ahSrcSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS];
 294
 295         u32 ui32NumDstSync;
 296         void *ahDstSyncInfo[SGX_MAX_TRANSFER_SYNC_OPS];
 297
 298         u32 ui32Flags;
 299
 300         u32 ui32PDumpFlags;
 301 #if defined(PDUMP)
 302         u32 ui32CCBDumpWOff;
 303 #endif
 304 };
 305
 306 #define PVRSRV_SGX_DIFF_NUM_COUNTERS    9
 307
 308 struct PVRSRV_SGXDEV_DIFF_INFO {
 309         u32 aui32Counters[PVRSRV_SGX_DIFF_NUM_COUNTERS];
 310         u32 ui32Time[2];
 311         u32 ui32Marker[2];
 312 };
 313
 314 #define SGXMKIF_HWPERF_CB_SIZE                                  0x100
 315
 316 struct SGXMKIF_HWPERF_CB_ENTRY {
 317         u32 ui32FrameNo;
 318         u32 ui32Type;
 319         u32 ui32Ordinal;
 320         u32 ui32TimeWraps;
 321         u32 ui32Time;
 322         u32 ui32Counters[PVRSRV_SGX_HWPERF_NUM_COUNTERS];
 323 };
 324
 325 struct SGXMKIF_HWPERF_CB {
 326         u32 ui32Woff;
 327         u32 ui32Roff;
 328         u32 ui32OrdinalGRAPHICS;
 329         u32 ui32OrdinalMK_EXECUTION;
 330         struct SGXMKIF_HWPERF_CB_ENTRY psHWPerfCBData[SGXMKIF_HWPERF_CB_SIZE];
 331 };
 332
 333 struct PVRSRV_SGX_MISCINFO_INFO {
 334         u32 ui32MiscInfoFlags;
 335         struct PVRSRV_SGX_MISCINFO_FEATURES sSGXFeatures;
 336 };
 337
 338 #endif