gpu: pvr: V2: Find and fix all incorrect sync counter completion checks
[sgx.git] / pvr / sgx_bridge.h
1 /**********************************************************************
2  *
3  * Copyright(c) 2008 Imagination Technologies Ltd. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful but, except
10  * as otherwise stated in writing, without any warranty; without even the
11  * implied warranty of merchantability or fitness for a particular purpose.
12  * See the GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License along with
15  * this program; if not, write to the Free Software Foundation, Inc.,
16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17  *
18  * The full GNU General Public License is included in this distribution in
19  * the file called "COPYING".
20  *
21  * Contact Information:
22  * Imagination Technologies Ltd. <gpl-support@imgtec.com>
23  * Home Park Estate, Kings Langley, Herts, WD4 8LZ, UK
24  *
25  ******************************************************************************/
26
27 #if !defined(__SGX_BRIDGE_H__)
28 #define __SGX_BRIDGE_H__
29
30 #include "sgxapi_km.h"
31 #include "sgxinfo.h"
32 #include "pvr_bridge.h"
33
34 #define PVRSRV_BRIDGE_SGX_CMD_BASE (PVRSRV_BRIDGE_LAST_NON_DEVICE_CMD+1)
35 #define PVRSRV_BRIDGE_SGX_GETCLIENTINFO                                 \
36                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+0)
37 #define PVRSRV_BRIDGE_SGX_RELEASECLIENTINFO                             \
38                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+1)
39 #define PVRSRV_BRIDGE_SGX_GETINTERNALDEVINFO                            \
40                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+2)
41 #define PVRSRV_BRIDGE_SGX_DOKICK                                        \
42                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+3)
43 #define PVRSRV_BRIDGE_SGX_GETPHYSPAGEADDR                               \
44                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+4)
45 #define PVRSRV_BRIDGE_SGX_READREGISTRYDWORD                             \
46                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+5)
47 #define PVRSRV_BRIDGE_SGX_SCHEDULECOMMAND                               \
48                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+6)
49
50 #define PVRSRV_BRIDGE_SGX_2DQUERYBLTSCOMPLETE                           \
51                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+9)
52
53 #define PVRSRV_BRIDGE_SGX_GETMMUPDADDR                                  \
54                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+10)
55
56 #define PVRSRV_BRIDGE_SGX_SUBMITTRANSFER                                \
57                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+13)
58 #define PVRSRV_BRIDGE_SGX_GETMISCINFO                                   \
59                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+14)
60 #define PVRSRV_BRIDGE_SGXINFO_FOR_SRVINIT                               \
61                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+15)
62 #define PVRSRV_BRIDGE_SGX_DEVINITPART2                                  \
63                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+16)
64
65 #define PVRSRV_BRIDGE_SGX_FINDSHAREDPBDESC                              \
66                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+17)
67 #define PVRSRV_BRIDGE_SGX_UNREFSHAREDPBDESC                             \
68                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+18)
69 #define PVRSRV_BRIDGE_SGX_ADDSHAREDPBDESC                               \
70                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+19)
71 #define PVRSRV_BRIDGE_SGX_REGISTER_HW_RENDER_CONTEXT                    \
72                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+20)
73 #define PVRSRV_BRIDGE_SGX_FLUSH_HW_RENDER_TARGET                        \
74                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+21)
75 #define PVRSRV_BRIDGE_SGX_UNREGISTER_HW_RENDER_CONTEXT                  \
76                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+22)
77 #define PVRSRV_BRIDGE_SGX_REGISTER_HW_TRANSFER_CONTEXT                  \
78                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+26)
79 #define PVRSRV_BRIDGE_SGX_UNREGISTER_HW_TRANSFER_CONTEXT                \
80                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+27)
81
82 #define PVRSRV_BRIDGE_SGX_SCHEDULE_PROCESS_QUEUES                       \
83                                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+28)
84
85 #define PVRSRV_BRIDGE_SGX_READ_DIFF_COUNTERS                            \
86                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+29)
87 #define PVRSRV_BRIDGE_SGX_READ_HWPERF_CB                                \
88                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_CMD_BASE+30)
89
90 #define PVRSRV_BRIDGE_LAST_SGX_CMD (PVRSRV_BRIDGE_SGX_CMD_BASE+30)
91
92
93 #if defined(PDUMP)
94 #define PVRSRV_BRIDGE_SGX_PDUMP_CMD_BASE                                \
95         (PVRSRV_BRIDGE_PDUMP_CMD_LAST+1)
96
97 #define PVRSRV_BRIDGE_SGX_PDUMP_BUFFER_ARRAY                            \
98                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_PDUMP_CMD_BASE+0)
99 #define PVRSRV_BRIDGE_SGX_PDUMP_3D_SIGNATURE_REGISTERS                  \
100                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_PDUMP_CMD_BASE+1)
101 #define PVRSRV_BRIDGE_SGX_PDUMP_COUNTER_REGISTERS                       \
102                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_PDUMP_CMD_BASE+2)
103 #define PVRSRV_BRIDGE_SGX_PDUMP_TA_SIGNATURE_REGISTERS                  \
104                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_PDUMP_CMD_BASE+3)
105 #define PVRSRV_BRIDGE_SGX_PDUMP_HWPERFCB                                \
106                 PVRSRV_IOWR(PVRSRV_BRIDGE_SGX_PDUMP_CMD_BASE+4)
107 #endif
108
109 /* sanity check */
110 #if defined(PDUMP)
111 #if PVRSRV_BRIDGE_PDUMP_CMD_FIRST <= PVRSRV_BRIDGE_LAST_SGX_CMD
112 # error Standard and PDUMP IOCTLs overlap!!!
113 #endif
114 #endif
115
116 struct PVRSRV_BRIDGE_IN_GETPHYSPAGEADDR {
117         u32 ui32BridgeFlags;
118         void *hDevMemHeap;
119         struct IMG_DEV_VIRTADDR sDevVAddr;
120 };
121
122 struct PVRSRV_BRIDGE_OUT_GETPHYSPAGEADDR {
123         enum PVRSRV_ERROR eError;
124         struct IMG_DEV_PHYADDR DevPAddr;
125         struct IMG_CPU_PHYADDR CpuPAddr;
126 };
127
128 struct PVRSRV_BRIDGE_IN_SGX_GETMMU_PDADDR {
129         u32 ui32BridgeFlags;
130         void *hDevCookie;
131         void *hDevMemContext;
132 };
133
134 struct PVRSRV_BRIDGE_OUT_SGX_GETMMU_PDADDR {
135         struct IMG_DEV_PHYADDR sPDDevPAddr;
136         enum PVRSRV_ERROR eError;
137 };
138
139 struct PVRSRV_BRIDGE_IN_GETCLIENTINFO {
140         u32 ui32BridgeFlags;
141         void *hDevCookie;
142 };
143
144 struct PVRSRV_BRIDGE_OUT_GETINTERNALDEVINFO {
145         struct SGX_INTERNAL_DEVINFO sSGXInternalDevInfo;
146         enum PVRSRV_ERROR eError;
147 };
148
149 struct PVRSRV_BRIDGE_IN_GETINTERNALDEVINFO {
150         u32 ui32BridgeFlags;
151         void *hDevCookie;
152 };
153
154 struct PVRSRV_BRIDGE_OUT_GETCLIENTINFO {
155         struct SGX_CLIENT_INFO sClientInfo;
156         enum PVRSRV_ERROR eError;
157 };
158
159 struct PVRSRV_BRIDGE_IN_RELEASECLIENTINFO {
160         u32 ui32BridgeFlags;
161         void *hDevCookie;
162         struct SGX_CLIENT_INFO sClientInfo;
163 };
164
165 struct PVRSRV_BRIDGE_IN_ISPBREAKPOLL {
166         u32 ui32BridgeFlags;
167         void *hDevCookie;
168 };
169
170 struct PVRSRV_BRIDGE_IN_DOKICK {
171         u32 ui32BridgeFlags;
172         void *hDevCookie;
173         struct SGX_CCB_KICK sCCBKick;
174 };
175
176 struct PVRSRV_BRIDGE_IN_SGX_SCHEDULE_PROCESS_QUEUES {
177         u32 ui32BridgeFlags;
178         void *hDevCookie;
179 };
180
181 struct PVRSRV_BRIDGE_IN_SUBMITTRANSFER {
182         u32 ui32BridgeFlags;
183         void *hDevCookie;
184         struct PVRSRV_TRANSFER_SGX_KICK sKick;
185 };
186
187
188 struct PVRSRV_BRIDGE_IN_READREGDWORD {
189         u32 ui32BridgeFlags;
190         void *hDevCookie;
191         char *pszKey;
192         char *pszValue;
193 };
194
195 struct PVRSRV_BRIDGE_OUT_READREGDWORD {
196         enum PVRSRV_ERROR eError;
197         u32 ui32Data;
198 };
199
200 struct PVRSRV_BRIDGE_IN_SCHEDULECOMMAND {
201         u32 ui32BridgeFlags;
202         void *hDevCookie;
203         enum SGXMKIF_COMMAND_TYPE eCommandType;
204         struct SGXMKIF_COMMAND *psCommandData;
205
206 };
207
208 struct PVRSRV_BRIDGE_IN_SGXGETMISCINFO {
209         u32 ui32BridgeFlags;
210         void *hDevCookie;
211         struct SGX_MISC_INFO __user *psMiscInfo;
212 };
213
214 struct PVRSRV_BRIDGE_IN_SGXINFO_FOR_SRVINIT {
215         u32 ui32BridgeFlags;
216         void *hDevCookie;
217 };
218
219 struct PVRSRV_BRIDGE_OUT_SGXINFO_FOR_SRVINIT {
220         enum PVRSRV_ERROR eError;
221         struct SGX_BRIDGE_INFO_FOR_SRVINIT sInitInfo;
222 };
223
224 struct PVRSRV_BRIDGE_IN_SGXDEVINITPART2 {
225         u32 ui32BridgeFlags;
226         void *hDevCookie;
227         struct SGX_BRIDGE_INIT_INFO sInitInfo;
228 };
229
230 enum pvr_sync_wait_seq_type {
231         _PVR_SYNC_WAIT_BLOCK,
232         _PVR_SYNC_WAIT_NONBLOCK,
233         _PVR_SYNC_WAIT_EVENT,
234         _PVR_SYNC_WAIT_FLIP,
235         _PVR_SYNC_WAIT_UPDATE,
236 };
237
238 struct PVRSRV_BRIDGE_IN_2DQUERYBLTSCOMPLETE {
239         u32 ui32BridgeFlags;
240         void *hDevCookie;
241         void *hKernSyncInfo;
242         u64 user_data;
243         enum pvr_sync_wait_seq_type type;
244 };
245
246 #define PVRSRV_BRIDGE_SGX_SHAREDPBDESC_MAX_SUBMEMINFOS 10
247
248 struct PVRSRV_BRIDGE_IN_SGXFINDSHAREDPBDESC {
249         u32 ui32BridgeFlags;
250         void *hDevCookie;
251         IMG_BOOL bLockOnFailure;
252         u32 ui32TotalPBSize;
253 };
254
255 struct PVRSRV_BRIDGE_OUT_SGXFINDSHAREDPBDESC {
256         void *hKernelMemInfo;
257         void *hSharedPBDesc;
258         void *hSharedPBDescKernelMemInfoHandle;
259         void *hHWPBDescKernelMemInfoHandle;
260         void *hBlockKernelMemInfoHandle;
261         void *ahSharedPBDescSubKernelMemInfoHandles
262             [PVRSRV_BRIDGE_SGX_SHAREDPBDESC_MAX_SUBMEMINFOS];
263         u32 ui32SharedPBDescSubKernelMemInfoHandlesCount;
264         enum PVRSRV_ERROR eError;
265 };
266
267 struct PVRSRV_BRIDGE_IN_SGXUNREFSHAREDPBDESC {
268         u32 ui32BridgeFlags;
269         void *hSharedPBDesc;
270 };
271
272 struct PVRSRV_BRIDGE_OUT_SGXUNREFSHAREDPBDESC {
273         enum PVRSRV_ERROR eError;
274 };
275
276 struct PVRSRV_BRIDGE_IN_SGXADDSHAREDPBDESC {
277         u32 ui32BridgeFlags;
278         void *hDevCookie;
279         void *hSharedPBDescKernelMemInfo;
280         void *hHWPBDescKernelMemInfo;
281         void *hBlockKernelMemInfo;
282         u32 ui32TotalPBSize;
283         void * __user *phKernelMemInfoHandles;
284         u32 ui32KernelMemInfoHandlesCount;
285 };
286
287 struct PVRSRV_BRIDGE_OUT_SGXADDSHAREDPBDESC {
288         enum PVRSRV_ERROR eError;
289         void *hSharedPBDesc;
290 };
291
292 #ifdef  PDUMP
293 struct PVRSRV_BRIDGE_IN_PDUMP_BUFFER_ARRAY {
294         u32 ui32BridgeFlags;
295         struct SGX_KICKTA_DUMP_BUFFER __user *psBufferArray;
296         u32 ui32BufferArrayLength;
297         IMG_BOOL bDumpPolls;
298 };
299
300 struct PVRSRV_BRIDGE_IN_PDUMP_3D_SIGNATURE_REGISTERS {
301         u32 ui32BridgeFlags;
302         u32 ui32DumpFrameNum;
303         IMG_BOOL bLastFrame;
304         u32 __user *pui32Registers;
305         u32 ui32NumRegisters;
306 };
307
308 struct PVRSRV_BRIDGE_IN_PDUMP_COUNTER_REGISTERS {
309         u32 ui32BridgeFlags;
310         u32 ui32DumpFrameNum;
311         IMG_BOOL bLastFrame;
312         u32 __user *pui32Registers;
313         u32 ui32NumRegisters;
314 };
315
316 struct PVRSRV_BRIDGE_IN_PDUMP_TA_SIGNATURE_REGISTERS {
317         u32 ui32BridgeFlags;
318         u32 ui32DumpFrameNum;
319         u32 ui32TAKickCount;
320         IMG_BOOL bLastFrame;
321         u32 __user *pui32Registers;
322         u32 ui32NumRegisters;
323 };
324
325 struct PVRSRV_BRIDGE_IN_PDUMP_HWPERFCB {
326         u32 ui32BridgeFlags;
327         void *hDevCookie;
328         char szFileName[PVRSRV_PDUMP_MAX_FILENAME_SIZE];
329         u32 ui32FileOffset;
330         u32 ui32PDumpFlags;
331
332 };
333
334 #endif
335
336 struct PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_RENDER_CONTEXT {
337         u32 ui32BridgeFlags;
338         void *hDevCookie;
339         struct IMG_DEV_VIRTADDR sHWRenderContextDevVAddr;
340 };
341
342 struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_RENDER_CONTEXT {
343         enum PVRSRV_ERROR eError;
344         void *hHWRenderContext;
345 };
346
347 struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_RENDER_CONTEXT {
348         u32 ui32BridgeFlags;
349         void *hDevCookie;
350         void *hHWRenderContext;
351 };
352
353 struct PVRSRV_BRIDGE_IN_SGX_REGISTER_HW_TRANSFER_CONTEXT {
354         u32 ui32BridgeFlags;
355         void *hDevCookie;
356         struct IMG_DEV_VIRTADDR sHWTransferContextDevVAddr;
357 };
358
359 struct PVRSRV_BRIDGE_OUT_SGX_REGISTER_HW_TRANSFER_CONTEXT {
360         enum PVRSRV_ERROR eError;
361         void *hHWTransferContext;
362 };
363
364 struct PVRSRV_BRIDGE_IN_SGX_UNREGISTER_HW_TRANSFER_CONTEXT {
365         u32 ui32BridgeFlags;
366         void *hDevCookie;
367         void *hHWTransferContext;
368 };
369
370 struct PVRSRV_BRIDGE_IN_SGX_FLUSH_HW_RENDER_TARGET {
371         u32 ui32BridgeFlags;
372         void *hDevCookie;
373         struct IMG_DEV_VIRTADDR sHWRTDataSetDevVAddr;
374 };
375
376 struct PVRSRV_BRIDGE_IN_SGX_READ_DIFF_COUNTERS {
377         u32 ui32BridgeFlags;
378         void *hDevCookie;
379         u32 ui32Reg;
380         IMG_BOOL bNew;
381         u32 ui32New;
382         u32 ui32NewReset;
383         u32 ui32CountersReg;
384 };
385
386 struct PVRSRV_BRIDGE_OUT_SGX_READ_DIFF_COUNTERS {
387         enum PVRSRV_ERROR eError;
388         u32 ui32Old;
389         u32 ui32Time;
390         IMG_BOOL bActive;
391         struct PVRSRV_SGXDEV_DIFF_INFO sDiffs;
392 };
393
394 struct PVRSRV_BRIDGE_IN_SGX_READ_HWPERF_CB {
395         u32 ui32BridgeFlags;
396         void *hDevCookie;
397         u32 ui32ArraySize;
398         struct PVRSRV_SGX_HWPERF_CB_ENTRY __user *psHWPerfCBData;
399 };
400
401 struct PVRSRV_BRIDGE_OUT_SGX_READ_HWPERF_CB {
402         enum PVRSRV_ERROR eError;
403         u32 ui32DataCount;
404         u32 ui32ClockSpeed;
405         u32 ui32HostTimeStamp;
406 };
407
408 #endif