1 /****************************************************************************
4 Copyright : 2009 by Imagination Technologies Limited.
5 All rights reserved. No part of this software, either
6 material or conceptual may be copied or distributed,
7 transmitted, transcribed, stored in a retrieval system or
8 translated into any human or computer language in any form
9 by any means, electronic, mechanical, manual or otherwise,
10 or disclosed to third parties without the express written
11 permission of Imagination Technologies Limited,
12 Home Park Estate, Kings Langley, Hertfordshire,
20 ****************************************************************************/
25 #include "sysconfig.h"
27 #define SYS_OMAP3430_OCP_REGS_SYS_PHYS_BASE \
28 (SYS_OMAP3430_SGX_REGS_SYS_PHYS_BASE + EUR_CR_OCP_REVISION)
29 #define SYS_OMAP3430_OCP_REGS_SIZE 0x110
31 /* Register EUR_CR_OCP_REVISION */
32 #define EUR_CR_OCP_REVISION 0xFE00
33 #define EUR_CR_OCP_REVISION_REV_MASK 0xFFFFFFFFUL
34 #define EUR_CR_OCP_REVISION_REV_SHIFT 0
35 #define EUR_CR_OCP_REVISION_REV_SIGNED 0
37 /* Register EUR_CR_OCP_HWINFO */
38 #define EUR_CR_OCP_HWINFO 0xFE04
39 #define EUR_CR_OCP_HWINFO_SYS_BUS_WIDTH_MASK 0x00000003UL
40 #define EUR_CR_OCP_HWINFO_SYS_BUS_WIDTH_SHIFT 0
41 #define EUR_CR_OCP_HWINFO_SYS_BUS_WIDTH_SIGNED 0
43 #define EUR_CR_OCP_HWINFO_MEM_BUS_WIDTH_MASK 0x00000004UL
44 #define EUR_CR_OCP_HWINFO_MEM_BUS_WIDTH_SHIFT 2
45 #define EUR_CR_OCP_HWINFO_MEM_BUS_WIDTH_SIGNED 0
47 /* Register EUR_CR_OCP_SYSCONFIG */
48 #define EUR_CR_OCP_SYSCONFIG 0xFE10
49 #define EUR_CR_OCP_SYSCONFIG_IDLE_MODE_MASK 0x0000000CUL
50 #define EUR_CR_OCP_SYSCONFIG_IDLE_MODE_SHIFT 2
51 #define EUR_CR_OCP_SYSCONFIG_IDLE_MODE_SIGNED 0
53 #define EUR_CR_OCP_SYSCONFIG_STANDBY_MODE_MASK 0x00000030UL
54 #define EUR_CR_OCP_SYSCONFIG_STANDBY_MODE_SHIFT 4
55 #define EUR_CR_OCP_SYSCONFIG_STANDBY_MODE_SIGNED 0
57 /* Register EUR_CR_OCP_IRQSTATUS_RAW_0 */
58 #define EUR_CR_OCP_IRQSTATUS_RAW_0 0xFE24
59 #define EUR_CR_OCP_IRQSTATUS_RAW_0_INIT_MASK 0x00000001UL
60 #define EUR_CR_OCP_IRQSTATUS_RAW_0_INIT_SHIFT 0
61 #define EUR_CR_OCP_IRQSTATUS_RAW_0_INIT_SIGNED 0
63 /* Register EUR_CR_OCP_IRQSTATUS_RAW_1 */
64 #define EUR_CR_OCP_IRQSTATUS_RAW_1 0xFE28
65 #define EUR_CR_OCP_IRQSTATUS_RAW_1_TARGET_MASK 0x00000001UL
66 #define EUR_CR_OCP_IRQSTATUS_RAW_1_TARGET_SHIFT 0
67 #define EUR_CR_OCP_IRQSTATUS_RAW_1_TARGET_SIGNED 0
69 /* Register EUR_CR_OCP_IRQSTATUS_RAW_2 */
70 #define EUR_CR_OCP_IRQSTATUS_RAW_2 0xFE2C
71 #define EUR_CR_OCP_IRQSTATUS_RAW_2_SGXCORE_MASK 0x00000001UL
72 #define EUR_CR_OCP_IRQSTATUS_RAW_2_SGXCORE_SHIFT 0
73 #define EUR_CR_OCP_IRQSTATUS_RAW_2_SGXCORE_SIGNED 0
75 /* Register EUR_CR_OCP_IRQSTATUS_0 */
76 #define EUR_CR_OCP_IRQSTATUS_0 0xFE30
77 #define EUR_CR_OCP_IRQSTATUS_0_INIT_MASK 0x00000001UL
78 #define EUR_CR_OCP_IRQSTATUS_0_INIT_SHIFT 0
79 #define EUR_CR_OCP_IRQSTATUS_0_INIT_SIGNED 0
81 /* Register EUR_CR_OCP_IRQSTATUS_1 */
82 #define EUR_CR_OCP_IRQSTATUS_1 0xFE34
83 #define EUR_CR_OCP_IRQSTATUS_1_TARGET_MASK 0x00000001UL
84 #define EUR_CR_OCP_IRQSTATUS_1_TARGET_SHIFT 0
85 #define EUR_CR_OCP_IRQSTATUS_1_TARGET_SIGNED 0
87 /* Register EUR_CR_OCP_IRQSTATUS_2 */
88 #define EUR_CR_OCP_IRQSTATUS_2 0xFE38
89 #define EUR_CR_OCP_IRQSTATUS_2_SGXCORE_MASK 0x00000001UL
90 #define EUR_CR_OCP_IRQSTATUS_2_SGXCORE_SHIFT 0
91 #define EUR_CR_OCP_IRQSTATUS_2_SGXCORE_SIGNED 0
93 /* Register EUR_CR_OCP_IRQENABLE_SET_0 */
94 #define EUR_CR_OCP_IRQENABLE_SET_0 0xFE3C
95 #define EUR_CR_OCP_IRQENABLE_SET_0_INIT_MASK 0x00000001UL
96 #define EUR_CR_OCP_IRQENABLE_SET_0_INIT_SHIFT 0
97 #define EUR_CR_OCP_IRQENABLE_SET_0_INIT_SIGNED 0
99 /* Register EUR_CR_OCP_IRQENABLE_SET_1 */
100 #define EUR_CR_OCP_IRQENABLE_SET_1 0xFE40
101 #define EUR_CR_OCP_IRQENABLE_SET_1_TARGET_MASK 0x00000001UL
102 #define EUR_CR_OCP_IRQENABLE_SET_1_TARGET_SHIFT 0
103 #define EUR_CR_OCP_IRQENABLE_SET_1_TARGET_SIGNED 0
105 /* Register EUR_CR_OCP_IRQENABLE_SET_2 */
106 #define EUR_CR_OCP_IRQENABLE_SET_2 0xFE44
107 #define EUR_CR_OCP_IRQENABLE_SET_2_SGXCORE_MASK 0x00000001UL
108 #define EUR_CR_OCP_IRQENABLE_SET_2_SGXCORE_SHIFT 0
109 #define EUR_CR_OCP_IRQENABLE_SET_2_SGXCORE_SIGNED 0
111 /* Register EUR_CR_OCP_IRQENABLE_CLR_0 */
112 #define EUR_CR_OCP_IRQENABLE_CLR_0 0xFE48
113 #define EUR_CR_OCP_IRQENABLE_CLR_0_INIT_MASK 0x00000001UL
114 #define EUR_CR_OCP_IRQENABLE_CLR_0_INIT_SHIFT 0
115 #define EUR_CR_OCP_IRQENABLE_CLR_0_INIT_SIGNED 0
117 /* Register EUR_CR_OCP_IRQENABLE_CLR_1 */
118 #define EUR_CR_OCP_IRQENABLE_CLR_1 0xFE4C
119 #define EUR_CR_OCP_IRQENABLE_CLR_1_TARGET_MASK 0x00000001UL
120 #define EUR_CR_OCP_IRQENABLE_CLR_1_TARGET_SHIFT 0
121 #define EUR_CR_OCP_IRQENABLE_CLR_1_TARGET_SIGNED 0
123 /* Register EUR_CR_OCP_IRQENABLE_CLR_2 */
124 #define EUR_CR_OCP_IRQENABLE_CLR_2 0xFE50
125 #define EUR_CR_OCP_IRQENABLE_CLR_2_SGXCORE_MASK 0x00000001UL
126 #define EUR_CR_OCP_IRQENABLE_CLR_2_SGXCORE_SHIFT 0
127 #define EUR_CR_OCP_IRQENABLE_CLR_2_SGXCORE_SIGNED 0
129 /* Register EUR_CR_OCP_PAGE_CONFIG */
130 #define EUR_CR_OCP_PAGE_CONFIG 0xFF00
131 #define EUR_CR_OCP_PAGE_CONFIG_MEM_PAGE_SIZE_MASK 0x00000001UL
132 #define EUR_CR_OCP_PAGE_CONFIG_MEM_PAGE_SIZE_SHIFT 0
133 #define EUR_CR_OCP_PAGE_CONFIG_MEM_PAGE_SIZE_SIGNED 0
135 #define EUR_CR_OCP_PAGE_CONFIG_MEM_PAGE_CHECK_ENABLE_MASK 0x00000004UL
136 #define EUR_CR_OCP_PAGE_CONFIG_MEM_PAGE_CHECK_ENABLE_SHIFT 2
137 #define EUR_CR_OCP_PAGE_CONFIG_MEM_PAGE_CHECK_ENABLE_SIGNED 0
139 #define EUR_CR_OCP_PAGE_CONFIG_SIZE_MASK 0x00000018UL
140 #define EUR_CR_OCP_PAGE_CONFIG_SIZE_SHIFT 3
141 #define EUR_CR_OCP_PAGE_CONFIG_SIZE_SIGNED 0
143 /* Register EUR_CR_OCP_INTERRUPT_EVENT */
144 #define EUR_CR_OCP_INTERRUPT_EVENT 0xFF04
145 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_MASK 0x00000001UL
146 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_SHIFT 0
147 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_UNEXPECTED_SIGNED 0
149 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_UNUSED_TAG_MASK 0x00000002UL
150 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_UNUSED_TAG_SHIFT 1
151 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_UNUSED_TAG_SIGNED 0
153 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_ERROR_MASK 0x00000004UL
154 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_ERROR_SHIFT 2
155 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_RESP_ERROR_SIGNED 0
157 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_PAGE_CROSS_ERROR_MASK 0x00000008UL
158 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_PAGE_CROSS_ERROR_SHIFT 3
159 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_PAGE_CROSS_ERROR_SIGNED 0
161 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_READ_TAG_FIFO_OVR_MASK 0x00000010UL
162 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_READ_TAG_FIFO_OVR_SHIFT 4
163 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_READ_TAG_FIFO_OVR_SIGNED 0
165 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_MEM_REQ_FIFO_OVR_MASK 0x00000020UL
166 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_MEM_REQ_FIFO_OVR_SHIFT 5
167 #define EUR_CR_OCP_INTERRUPT_EVENT_INIT_MEM_REQ_FIFO_OVR_SIGNED 0
169 #define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_RESP_FIFO_FULL_MASK 0x00000100UL
170 #define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_RESP_FIFO_FULL_SHIFT 8
171 #define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_RESP_FIFO_FULL_SIGNED 0
173 #define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_CMD_FIFO_FULL_MASK 0x00000200UL
174 #define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_CMD_FIFO_FULL_SHIFT 9
175 #define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_CMD_FIFO_FULL_SIGNED 0
177 #define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_INVALID_OCP_CMD_MASK 0x00000400UL
178 #define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_INVALID_OCP_CMD_SHIFT 10
179 #define EUR_CR_OCP_INTERRUPT_EVENT_TARGET_INVALID_OCP_CMD_SIGNED 0
181 /* Register EUR_CR_OCP_DEBUG_CONFIG */
182 #define EUR_CR_OCP_DEBUG_CONFIG 0xFF08
183 #define EUR_CR_OCP_DEBUG_CONFIG_FORCE_TARGET_IDLE_MASK 0x00000003UL
184 #define EUR_CR_OCP_DEBUG_CONFIG_FORCE_TARGET_IDLE_SHIFT 0
185 #define EUR_CR_OCP_DEBUG_CONFIG_FORCE_TARGET_IDLE_SIGNED 0
187 #define EUR_CR_OCP_DEBUG_CONFIG_FORCE_INIT_IDLE_MASK 0x0000000CUL
188 #define EUR_CR_OCP_DEBUG_CONFIG_FORCE_INIT_IDLE_SHIFT 2
189 #define EUR_CR_OCP_DEBUG_CONFIG_FORCE_INIT_IDLE_SIGNED 0
191 #define EUR_CR_OCP_DEBUG_CONFIG_FORCE_PASS_DATA_MASK 0x00000010UL
192 #define EUR_CR_OCP_DEBUG_CONFIG_FORCE_PASS_DATA_SHIFT 4
193 #define EUR_CR_OCP_DEBUG_CONFIG_FORCE_PASS_DATA_SIGNED 0
195 #define EUR_CR_OCP_DEBUG_CONFIG_SELECT_INIT_IDLE_MASK 0x00000020UL
196 #define EUR_CR_OCP_DEBUG_CONFIG_SELECT_INIT_IDLE_SHIFT 5
197 #define EUR_CR_OCP_DEBUG_CONFIG_SELECT_INIT_IDLE_SIGNED 0
199 #define EUR_CR_OCP_DEBUG_CONFIG_THALIA_INT_BYPASS_MASK 0x80000000UL
200 #define EUR_CR_OCP_DEBUG_CONFIG_THALIA_INT_BYPASS_SHIFT 31
201 #define EUR_CR_OCP_DEBUG_CONFIG_THALIA_INT_BYPASS_SIGNED 0
203 /* Register EUR_CR_OCP_DEBUG_STATUS */
204 #define EUR_CR_OCP_DEBUG_STATUS 0xFF0C
205 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_MCONNECT_MASK 0x00000003UL
206 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_MCONNECT_SHIFT 0
207 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_MCONNECT_SIGNED 0
209 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_SCONNECT_MASK 0x00000004UL
210 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_SCONNECT_SHIFT 2
211 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_SCONNECT_SIGNED 0
213 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_SIDLEREQ_MASK 0x00000008UL
214 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_SIDLEREQ_SHIFT 3
215 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_SIDLEREQ_SIGNED 0
217 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_SDISCACK_MASK 0x00000030UL
218 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_SDISCACK_SHIFT 4
219 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_SDISCACK_SIGNED 0
221 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_SIDLEACK_MASK 0x000000C0UL
222 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_SIDLEACK_SHIFT 6
223 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_SIDLEACK_SIGNED 0
225 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MCONNECT0_MASK 0x00000300UL
226 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MCONNECT0_SHIFT 8
227 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MCONNECT0_SIGNED 0
229 #define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT0_MASK 0x00000400UL
230 #define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT0_SHIFT 10
231 #define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT0_SIGNED 0
233 #define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT1_MASK 0x00000800UL
234 #define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT1_SHIFT 11
235 #define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT1_SIGNED 0
237 #define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT2_MASK 0x00001000UL
238 #define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT2_SHIFT 12
239 #define EUR_CR_OCP_DEBUG_STATUS_INIT_SCONNECT2_SIGNED 0
241 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MDISCACK_MASK 0x00006000UL
242 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MDISCACK_SHIFT 13
243 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MDISCACK_SIGNED 0
245 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MDISCREQ_MASK 0x00008000UL
246 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MDISCREQ_SHIFT 15
247 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MDISCREQ_SIGNED 0
249 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MWAIT_MASK 0x00010000UL
250 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MWAIT_SHIFT 16
251 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MWAIT_SIGNED 0
253 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MSTANDBY_MASK 0x00020000UL
254 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MSTANDBY_SHIFT 17
255 #define EUR_CR_OCP_DEBUG_STATUS_INIT_MSTANDBY_SIGNED 0
257 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_CMD_OUT_MASK 0x001C0000UL
258 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_CMD_OUT_SHIFT 18
259 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_CMD_OUT_SIGNED 0
261 #define EUR_CR_OCP_DEBUG_STATUS_WHICH_TARGET_REGISTER_MASK 0x03E00000UL
262 #define EUR_CR_OCP_DEBUG_STATUS_WHICH_TARGET_REGISTER_SHIFT 21
263 #define EUR_CR_OCP_DEBUG_STATUS_WHICH_TARGET_REGISTER_SIGNED 0
265 #define EUR_CR_OCP_DEBUG_STATUS_RESP_ERROR_MASK 0x04000000UL
266 #define EUR_CR_OCP_DEBUG_STATUS_RESP_ERROR_SHIFT 26
267 #define EUR_CR_OCP_DEBUG_STATUS_RESP_ERROR_SIGNED 0
269 #define EUR_CR_OCP_DEBUG_STATUS_CMD_FIFO_FULL_MASK 0x08000000UL
270 #define EUR_CR_OCP_DEBUG_STATUS_CMD_FIFO_FULL_SHIFT 27
271 #define EUR_CR_OCP_DEBUG_STATUS_CMD_FIFO_FULL_SIGNED 0
273 #define EUR_CR_OCP_DEBUG_STATUS_RESP_FIFO_FULL_MASK 0x10000000UL
274 #define EUR_CR_OCP_DEBUG_STATUS_RESP_FIFO_FULL_SHIFT 28
275 #define EUR_CR_OCP_DEBUG_STATUS_RESP_FIFO_FULL_SIGNED 0
277 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_IDLE_MASK 0x20000000UL
278 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_IDLE_SHIFT 29
279 #define EUR_CR_OCP_DEBUG_STATUS_TARGET_IDLE_SIGNED 0
281 #define EUR_CR_OCP_DEBUG_STATUS_CMD_RESP_DEBUG_STATE_MASK 0x40000000UL
282 #define EUR_CR_OCP_DEBUG_STATUS_CMD_RESP_DEBUG_STATE_SHIFT 30
283 #define EUR_CR_OCP_DEBUG_STATUS_CMD_RESP_DEBUG_STATE_SIGNED 0
285 #define EUR_CR_OCP_DEBUG_STATUS_CMD_DEBUG_STATE_MASK 0x80000000UL
286 #define EUR_CR_OCP_DEBUG_STATUS_CMD_DEBUG_STATE_SHIFT 31
287 #define EUR_CR_OCP_DEBUG_STATUS_CMD_DEBUG_STATE_SIGNED 0
290 #endif /* _OCPDEFS_H_ */
292 /*****************************************************************************
293 End of file (ocpdefs.h)
294 *****************************************************************************/