3 * Texas Instruments <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * X-Loader Configuation settings for the overo board.
8 * Derived from /include/configs/omap3evm.h
9 * Steve Sakoman <steve@sakoman.com>
11 * See file CREDITS for list of people who contributed to this
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 /* serial printf facility takes about 3.5K */
38 * High Level Configuration Options
40 #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
41 #define CONFIG_OMAP 1 /* in a TI OMAP core */
42 #define CONFIG_OMAP34XX 1 /* which is a 34XX */
43 #define CONFIG_OMAP3430 1 /* which is in a 3430 */
44 #define CONFIG_OVERO 1 /* working with overo */
46 /* Enable the below macro if MMC boot support is required */
48 #if defined(CONFIG_MMC)
53 #include <asm/arch/cpu.h> /* get chip and board defs */
55 /* uncomment it if you need timer based udelay(). it takes about 250 bytes */
59 #define V_OSCK 26000000 /* Clock output from T2 */
61 #if (V_OSCK > 19200000)
62 #define V_SCLK (V_OSCK >> 1)
67 //#define PRCM_CLK_CFG2_266MHZ 1 /* VDD2=1.15v - 133MHz DDR */
68 #define PRCM_CLK_CFG2_332MHZ 1 /* VDD2=1.15v - 166MHz DDR */
69 #define PRCM_PCLK_OPP2 1 /* ARM=381MHz - VDD1=1.20v */
72 #define CFG_3430SDRAM_DDR 1
74 /* The actual register values are defined in u-boot- mem.h */
75 /* SDRAM Bank Allocation method */
76 //#define SDRC_B_R_C 1
77 //#define SDRC_B1_R_B0_C 1
80 #define NAND_BASE_ADR NAND_BASE
81 #define ONENAND_BASE ONENAND_MAP
82 #define ONENAND_ADDR ONENAND_BASE
84 #define OMAP34XX_GPMC_CS0_SIZE GPMC_SIZE_128M
89 #define CFG_NS16550_SERIAL
90 #define CFG_NS16550_REG_SIZE -4
91 #define CFG_NS16550_CLK 48000000
92 #define CFG_NS16550_COM3 OMAP34XX_UART3
95 * select serial console configuration
97 #define CONFIG_SERIAL1 3 /* use UART3 */
98 #define CONFIG_CONS_INDEX 3
100 #define CONFIG_BAUDRATE 115200
101 #define CFG_PBSIZE 256
103 #endif /* CFG_PRINTF */
106 * Miscellaneous configurable options
108 #define CFG_LOADADDR 0x80008000
110 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
112 /*-----------------------------------------------------------------------
115 * The stack sizes are set up in start.S using the settings below
117 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
119 /*-----------------------------------------------------------------------
123 #define CFG_NAND_K9F1G08R0A
126 /* NAND is partitioned:
127 * 0x00000000 - 0x0007FFFF Booting Image
128 * 0x00080000 - 0x0023FFFF U-Boot Image
129 * 0x00240000 - 0x0027FFFF U-Boot Env Data (X-loader doesn't care)
130 * 0x00280000 - 0x0077FFFF Kernel Image
131 * 0x00780000 - 0x08000000 depends on application
133 #define NAND_UBOOT_START 0x0080000 /* Leaving first 4 blocks for x-load */
134 #define NAND_UBOOT_END 0x0240000 /* Giving a space of 2 blocks = 256KB */
135 #define NAND_BLOCK_SIZE 0x20000
137 #define GPMC_CONFIG (OMAP34XX_GPMC_BASE+0x50)
138 #define GPMC_NAND_COMMAND_0 (OMAP34XX_GPMC_BASE+0x7C)
139 #define GPMC_NAND_ADDRESS_0 (OMAP34XX_GPMC_BASE+0x80)
140 #define GPMC_NAND_DATA_0 (OMAP34XX_GPMC_BASE+0x84)
143 #define WRITE_NAND_COMMAND(d, adr) \
144 do {*(volatile u16 *)GPMC_NAND_COMMAND_0 = d; } while (0)
145 #define WRITE_NAND_ADDRESS(d, adr) \
146 do {*(volatile u16 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
147 #define WRITE_NAND(d, adr) \
148 do {*(volatile u16 *)GPMC_NAND_DATA_0 = d; } while (0)
149 #define READ_NAND(adr) \
150 (*(volatile u16 *)GPMC_NAND_DATA_0)
151 #define NAND_WAIT_READY()
152 #define NAND_WP_OFF() \
153 do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
154 #define NAND_WP_ON() \
155 do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
157 #else /* to support 8-bit NAND devices */
158 #define WRITE_NAND_COMMAND(d, adr) \
159 do {*(volatile u8 *)GPMC_NAND_COMMAND_0 = d; } while (0)
160 #define WRITE_NAND_ADDRESS(d, adr) \
161 do {*(volatile u8 *)GPMC_NAND_ADDRESS_0 = d; } while (0)
162 #define WRITE_NAND(d, adr) \
163 do {*(volatile u8 *)GPMC_NAND_DATA_0 = d; } while (0)
164 #define READ_NAND(adr) \
165 (*(volatile u8 *)GPMC_NAND_DATA_0);
166 #define NAND_WAIT_READY()
167 #define NAND_WP_OFF() \
168 do {*(volatile u32 *)(GPMC_CONFIG) |= 0x00000010; } while (0)
169 #define NAND_WP_ON() \
170 do {*(volatile u32 *)(GPMC_CONFIG) &= ~0x00000010; } while (0)
174 #define NAND_CTL_CLRALE(adr)
175 #define NAND_CTL_SETALE(adr)
176 #define NAND_CTL_CLRCLE(adr)
177 #define NAND_CTL_SETCLE(adr)
178 #define NAND_DISABLE_CE()
179 #define NAND_ENABLE_CE()
181 /*-----------------------------------------------------------------------
182 * Board oneNAND Info.
184 #define CFG_SYNC_BURST_READ 1
186 /* OneNAND is partitioned:
187 * 0x0000000 - 0x0080000 X-Loader
188 * 0x0080000 - 0x0240000 U-boot Image
189 * 0x0240000 - 0x0280000 U-Boot Env Data (X-loader doesn't care)
190 * 0x0280000 - 0x0780000 Kernel Image
191 * 0x0780000 - 0x8000000 depends on application
194 #define ONENAND_START_BLOCK 4
195 #define ONENAND_END_BLOCK 18
196 #define ONENAND_PAGE_SIZE 2048 /* 2KB */
197 #define ONENAND_BLOCK_SIZE 0x20000 /* 128KB */
199 #endif /* __CONFIG_H */