2 * (C) Copyright 2004 Texas Instruments
3 * Jian Zhang <jzhang@ti.com>
5 * Samsung K9F1G08R0AQ0C NAND chip driver for an OMAP2420 board
7 * This file is based on the following u-boot file:
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/arch/sys_proto.h>
32 #include <asm/arch/sys_info.h>
34 #ifdef CFG_NAND_K9F1G08R0A
36 #define K9F1G08R0A_MFR 0xec /* Samsung */
37 #define K9F1G08R0A_ID 0xa1 /* part # */
39 /* Since Micron and Samsung parts are similar in geometry and bus width
40 * we can use the same driver. Need to revisit to make this file independent
41 * of part/manufacturer
43 #define MT29F1G_MFR 0x2c /* Micron */
44 #define MT29F1G_ID 0xa1 /* x8, 1GiB */
45 #define MT29F2G_ID 0xba /* x16, 2GiB */
49 #define ADDR_COLUMN_PAGE (ADDR_COLUMN | ADDR_PAGE)
51 #define ADDR_OOB (0x4 | ADDR_COLUMN_PAGE)
53 #define PAGE_SIZE 2048
55 #define MAX_NUM_PAGES 64
57 #define ECC_CHECK_ENABLE
61 /*******************************************************
63 * Description: spinning delay to use before udelay works
64 ******************************************************/
65 static inline void delay (unsigned long loops)
67 __asm__ volatile ("1:\n"
69 "bne 1b":"=r" (loops):"0" (loops));
72 static int nand_read_page(u_char *buf, ulong page_addr);
73 static int nand_read_oob(u_char * buf, ulong page_addr);
75 /* JFFS2 large page layout for 3-byte ECC per 256 bytes ECC layout */
76 /* This is the only SW ECC supported by u-boot. So to load u-boot
77 * this should be supported */
78 static u_char ecc_pos[] =
79 {40, 41, 42, 43, 44, 45, 46, 47,
80 48, 49, 50, 51, 52, 53, 54, 55,
81 56, 57, 58, 59, 60, 61, 62, 63};
82 static u_char eccvalid_pos = 4;
84 static unsigned long chipsize = (256 << 20);
87 static int bus_width = 16;
89 static int bus_width = 8;
92 /* NanD_Command: Send a flash command to the flash chip */
93 static int NanD_Command(unsigned char command)
95 NAND_CTL_SETCLE(NAND_ADDR);
97 WRITE_NAND_COMMAND(command, NAND_ADDR);
98 NAND_CTL_CLRCLE(NAND_ADDR);
100 if(command == NAND_CMD_RESET){
101 unsigned char ret_val;
102 NanD_Command(NAND_CMD_STATUS);
104 ret_val = READ_NAND(NAND_ADDR);/* wait till ready */
105 } while((ret_val & 0x40) != 0x40);
113 /* NanD_Address: Set the current address for the flash chip */
114 static int NanD_Address(unsigned int numbytes, unsigned long ofs)
118 NAND_CTL_SETALE(NAND_ADDR);
120 if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE
121 || numbytes == ADDR_OOB)
126 WRITE_NAND_ADDRESS(u, NAND_ADDR);
128 u = (col >> 8) & 0x07;
129 if (numbytes == ADDR_OOB)
130 u = u | ((bus_width == 16) ? (1 << 2) : (1 << 3));
131 WRITE_NAND_ADDRESS(u, NAND_ADDR);
134 if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE
135 || numbytes == ADDR_OOB)
137 u = (ofs >> 11) & 0xff;
138 WRITE_NAND_ADDRESS(u, NAND_ADDR);
139 u = (ofs >> 19) & 0xff;
140 WRITE_NAND_ADDRESS(u, NAND_ADDR);
142 /* One more address cycle for devices > 128MiB */
143 if (chipsize > (128 << 20)) {
144 u = (ofs >> 27) & 0xff;
145 WRITE_NAND_ADDRESS(u, NAND_ADDR);
149 NAND_CTL_CLRALE(NAND_ADDR);
155 /* read chip mfr and id
156 * return 0 if they match board config
165 if (NanD_Command(NAND_CMD_RESET)) {
166 printf("Err: RESET\n");
171 if (NanD_Command(NAND_CMD_READID)) {
172 printf("Err: READID\n");
177 NanD_Address(ADDR_COLUMN, 0);
179 mfr = READ_NAND(NAND_ADDR);
180 id = READ_NAND(NAND_ADDR);
184 if (get_cpu_rev() == CPU_3430_ES2)
185 return (mfr != MT29F1G_MFR || !(id == MT29F1G_ID || id == MT29F2G_ID));
187 return (mfr != K9F1G08R0A_MFR || id != K9F1G08R0A_ID);
190 /* read a block data to buf
191 * return 1 if the block is bad or ECC error can't be corrected for any page
194 int nand_read_block(unsigned char *buf, ulong block_addr)
198 #ifdef ECC_CHECK_ENABLE
199 u16 oob_buf[OOB_SIZE >> 1];
201 /* check bad block */
202 /* 0th word in spare area needs be 0xff */
203 if (nand_read_oob(oob_buf, block_addr) || (oob_buf[0] & 0xff) != 0xff){
204 printf("Skipped bad block at 0x%x\n", block_addr);
205 return 1; /* skip bad block */
208 /* read the block page by page*/
209 for (i=0; i<MAX_NUM_PAGES; i++){
210 if (nand_read_page(buf+offset, block_addr + offset))
218 /* read a page with ECC */
219 static int nand_read_page(u_char *buf, ulong page_addr)
221 #ifdef ECC_CHECK_ENABLE
222 u_char ecc_code[ECC_SIZE];
223 u_char ecc_calc[ECC_STEPS];
224 u_char oob_buf[OOB_SIZE];
237 NanD_Command(NAND_CMD_READ0);
238 NanD_Address(ADDR_COLUMN_PAGE, page_addr);
239 NanD_Command(NAND_CMD_READSTART);
242 /* A delay seems to be helping here. needs more investigation */
244 len = (bus_width == 16) ? PAGE_SIZE >> 1 : PAGE_SIZE;
246 for (cntr = 0; cntr < len; cntr++){
247 *p++ = READ_NAND(NAND_ADDR);
251 #ifdef ECC_CHECK_ENABLE
253 len = (bus_width == 16) ? OOB_SIZE >> 1 : OOB_SIZE;
254 for (cntr = 0; cntr < len; cntr++){
255 *p++ = READ_NAND(NAND_ADDR);
259 NAND_DISABLE_CE(); /* set pin high */
261 /* Pick the ECC bytes out of the oob data */
262 for (cntr = 0; cntr < ECC_SIZE; cntr++)
263 ecc_code[cntr] = oob_buf[ecc_pos[cntr]];
265 for(count = 0; count < ECC_SIZE; count += ECC_STEPS) {
266 nand_calculate_ecc (buf, &ecc_calc[0]);
267 if (nand_correct_data (buf, &ecc_code[count], &ecc_calc[0]) == -1) {
268 printf ("ECC Failed, page 0x%08x\n", page_addr);
269 for (val=0; val <256; val++)
270 printf("%x ", buf[val]);
282 /* read from the 16 bytes of oob data that correspond to a 512 / 2048 byte page.
284 static int nand_read_oob(u_char *buf, ulong page_addr)
296 len = (bus_width == 16) ? OOB_SIZE >> 1 : OOB_SIZE;
298 NAND_ENABLE_CE(); /* set pin low */
299 NanD_Command(NAND_CMD_READ0);
300 NanD_Address(ADDR_OOB, page_addr);
301 NanD_Command(NAND_CMD_READSTART);
304 /* A delay seems to be helping here. needs more investigation */
306 for (cntr = 0; cntr < len; cntr++)
307 *p++ = READ_NAND(NAND_ADDR);
310 NAND_DISABLE_CE(); /* set pin high */