2 * armboot - Startup Code for OMP2420/ARM1136 CPU-core
4 * Copyright (c) 2004-2006 Texas Instruments
6 * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
7 * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
8 * Copyright (c) 2002 Gary Jennejohn <gj@denx.de>
9 * Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
10 * Copyright (c) 2003 Kshitij <kshitij@ti.com>
11 * Copyright (c) 2004 Jian Zhang <jzhang@ti.com>
13 * See file CREDITS for list of people who contributed to this
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm/arch/cpu.h>
34 #incldue <asm/arch-omap3/omap3430.h>
56 .word 0x12345678 /* now 16*4=64 */
61 .balignl 16,0xdeadbeef
63 *************************************************************************
65 * Startup Code (reset vector)
67 * do important init only if we don't start from memory!
68 * setup Memory and board specific bits prior to relocation.
69 * relocate armboot to ram
72 *************************************************************************
83 * These are defined in the board-specific linker script.
94 * the actual reset code
99 * set the cpu to SVC32 mode
106 /* Copy vectors to mask ROM indirect addr */
107 adr r0, _start /* r0 <- current position of code */
108 add r0, r0, #4 /* skip reset vector */
109 mov r2, #64 /* r2 <- size to copy */
110 add r2, r0, r2 /* r2 <- source end address */
111 mov r1, #SRAM_OFFSET0 /* build vect addr */
112 mov r3, #SRAM_OFFSET1
114 mov r3, #SRAM_OFFSET2
117 ldmia r0!, {r3-r10} /* copy from source address [r0] */
118 stmia r1!, {r3-r10} /* copy to target address [r1] */
119 cmp r0, r2 /* until source end address [r2] */
120 bne next /* loop until equal */
122 bl cpy_clk_code /* put dpll adjust code behind vectors */
124 /* the mask ROM code should have PLL and others stable */
127 relocate: /* relocate U-Boot to RAM */
128 adr r0, _start /* r0 <- current position of code */
129 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
130 cmp r0, r1 /* no need to relocate if XIP */
131 beq stack_setup /* skip txt cpy if XIP(SRAM, SDRAM) */
133 ldr r2, _armboot_start
135 sub r2, r3, r2 /* r2 <- size of armboot */
136 add r2, r0, r2 /* r2 <- source end address */
139 ldmia r0!, {r3-r10} /* copy from source address [r0] */
140 stmia r1!, {r3-r10} /* copy to target address [r1] */
141 cmp r0, r2 /* until source end addreee [r2] */
144 /* Set up the stack */
146 ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
147 sub sp, r0, #128 /* leave 32 words for abort-stack */
148 and sp, sp, #~7 /* 8 byte alinged for (ldr/str)d */
150 /* Clear BSS (if any). Is below tx (watch load addr - need space) */
152 ldr r0, _bss_start /* find start of bss segment */
153 ldr r1, _bss_end /* stop here */
154 mov r2, #0x00000000 /* clear value */
156 str r2, [r0] /* clear BSS location */
157 cmp r0, r1 /* are we at the end yet */
158 add r0, r0, #4 /* increment clear index pointer */
159 bne clbss_l /* keep clearing till at end */
161 ldr pc, _start_armboot /* jump to C code */
163 _start_armboot: .word start_armboot
167 *************************************************************************
169 * CPU_init_critical registers
171 * setup important registers
172 * setup memory timing
174 *************************************************************************
180 mov r0, #0 /* set up for MCR */
181 mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
182 mcr p15, 0, r0, c7, c5, 1 /* invalidate icache */
184 /* Invalide L2 cache (gp device call point)
185 * - warning, this may have issues on EMU/HS devices
186 * this call can corrupt r0-r5
188 mov r12, #0x1 @ set up to invalide L2
189 smi: .word 0xE1600070 @ Call SMI monitor
192 * disable MMU stuff and caches
194 mrc p15, 0, r0, c1, c0, 0
195 bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
196 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
197 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
198 #ifndef CONFIG_ICACHE_OFF
199 orr r0, r0, #0x00001800 @ set bit 11,12 (---I Z---) BTB,I-Cache
201 mcr p15, 0, r0, c1, c0, 0
204 * Jump to board specific initialization... The Mask ROM will have already initialized
205 * basic memory. Go here to bump up clock rate and handle wake up conditions.
207 adr r0, _start /* r0 <- current position of code */
208 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
209 cmp r0, r1 /* pass on info about skipping some init portions */
210 moveq r0,#0x1 /* flag to skip prcm and sdrc setup */
213 mov ip, lr /* persevere link reg across call */
214 bl lowlevel_init /* go setup pll,mux,memory */
215 mov lr, ip /* restore link */
216 mov pc, lr /* back to my caller */
223 ldr sp, _TEXT_BASE /* use 32 words abort stack */
224 bl hang /* hang and never return */