2 * (C) Copyright 2004-2009
3 * Texas Instruments, <www.ti.com>
4 * Richard Woodruff <r-woodruff2@ti.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/arch/cpu.h>
26 #include <asm/arch/bits.h>
27 #include <asm/arch/mux.h>
28 #include <asm/arch/sys_proto.h>
29 #include <asm/arch/sys_info.h>
30 #include <asm/arch/clocks.h>
31 #include <asm/arch/mem.h>
33 #if (CONFIG_COMMANDS & CFG_CMD_NAND) && defined(CFG_NAND_LEGACY)
34 #include <linux/mtd/nand_legacy.h>
37 /* EMIF and DMM registers */
38 #define EMIF1_BASE 0x4c000000
39 #define EMIF2_BASE 0x4d000000
40 #define DMM_BASE 0x4e000000
42 #define EMIF_MOD_ID_REV 0x0000
43 #define EMIF_STATUS 0x0004
44 #define EMIF_SDRAM_CONFIG 0x0008
45 #define EMIF_LPDDR2_NVM_CONFIG 0x000C
46 #define EMIF_SDRAM_REF_CTRL 0x0010
47 #define EMIF_SDRAM_REF_CTRL_SHDW 0x0014
48 #define EMIF_SDRAM_TIM_1 0x0018
49 #define EMIF_SDRAM_TIM_1_SHDW 0x001C
50 #define EMIF_SDRAM_TIM_2 0x0020
51 #define EMIF_SDRAM_TIM_2_SHDW 0x0024
52 #define EMIF_SDRAM_TIM_3 0x0028
53 #define EMIF_SDRAM_TIM_3_SHDW 0x002C
54 #define EMIF_LPDDR2_NVM_TIM 0x0030
55 #define EMIF_LPDDR2_NVM_TIM_SHDW 0x0034
56 #define EMIF_PWR_MGMT_CTRL 0x0038
57 #define EMIF_PWR_MGMT_CTRL_SHDW 0x003C
58 #define EMIF_LPDDR2_MODE_REG_DATA 0x0040
59 #define EMIF_LPDDR2_MODE_REG_CFG 0x0050
60 #define EMIF_L3_CONFIG 0x0054
61 #define EMIF_L3_CFG_VAL_1 0x0058
62 #define EMIF_L3_CFG_VAL_2 0x005C
63 #define IODFT_TLGC 0x0060
64 #define EMIF_PERF_CNT_1 0x0080
65 #define EMIF_PERF_CNT_2 0x0084
66 #define EMIF_PERF_CNT_CFG 0x0088
67 #define EMIF_PERF_CNT_SEL 0x008C
68 #define EMIF_PERF_CNT_TIM 0x0090
69 #define EMIF_READ_IDLE_CTRL 0x0098
70 #define EMIF_READ_IDLE_CTRL_SHDW 0x009c
71 #define EMIF_ZQ_CONFIG 0x00C8
72 #define EMIF_DDR_PHY_CTRL_1 0x00E4
73 #define EMIF_DDR_PHY_CTRL_1_SHDW 0x00E8
74 #define EMIF_DDR_PHY_CTRL_2 0x00EC
76 #define DMM_LISA_MAP_0 0x0040
77 #define DMM_LISA_MAP_1 0x0044
78 #define DMM_LISA_MAP_2 0x0048
79 #define DMM_LISA_MAP_3 0x004C
87 #define REF_EN 0x40000000
106 #define MR1_VALUE ((MR1_NWR3 << 5) | (MR1_WC << 4) | (MR1_BT_SEQ << 3) \
109 /* defines for MR2 */
110 #define MR2_RL3_WL1 1
111 #define MR2_RL4_WL2 2
112 #define MR2_RL5_WL2 3
113 #define MR2_RL6_WL3 4
115 /* defines for MR10 */
116 #define MR10_ZQINIT 0xFF
117 #define MR10_ZQRESET 0xC3
118 #define MR10_ZQCL 0xAB
119 #define MR10_ZQCS 0x56
122 /* TODO: FREQ update method is not working so shadow registers programming
123 * is just for same of completeness. This would be safer if auto
124 * trasnitions are working
126 #define FREQ_UPDATE_EMIF
127 /* EMIF Needs to be configured@19.2 MHz and shadow registers
128 * should be programmed for new OPP.
131 #define SDRAM_CONFIG_INIT 0x80800EB1
132 #define DDR_PHY_CTRL_1_INIT 0x849FFFF5
133 #define READ_IDLE_CTRL 0x000501FF
134 #define PWR_MGMT_CTRL 0x4000000f
135 #define PWR_MGMT_CTRL_OPP100 0x4000000f
136 #define ZQ_CONFIG 0x500b3215
138 #define CS1_MR(mr) ((mr) | 0x80000000)
151 const struct ddr_regs ddr_regs_380_mhz = {
155 .phy_ctrl_1 = 0x849FF408,
156 .ref_ctrl = 0x000005ca,
157 .config_init = 0x80000eb1,
158 .config_final = 0x80001ab1,
159 .zq_config = 0x500b3215,
165 * Unused timings - but we may need them later
166 * Keep them commented
169 const struct ddr_regs ddr_regs_400_mhz = {
173 .phy_ctrl_1 = 0x849FF408,
174 .ref_ctrl = 0x00000618,
175 .config_init = 0x80000eb1,
176 .config_final = 0x80001ab1,
177 .zq_config = 0x500b3215,
182 const struct ddr_regs ddr_regs_200_mhz = {
186 .phy_ctrl_1 = 0x849FF405,
187 .ref_ctrl = 0x0000030c,
188 .config_init = 0x80000eb1,
189 .config_final = 0x80000eb1,
190 .zq_config = 0x500b3215,
196 const struct ddr_regs ddr_regs_200_mhz_2cs = {
200 .phy_ctrl_1 = 0x849FF405,
201 .ref_ctrl = 0x0000030c,
202 .config_init = 0x80000eb9,
203 .config_final = 0x80000eb9,
204 .zq_config = 0xD00b3215,
209 const struct ddr_regs ddr_regs_400_mhz_2cs = {
210 /* tRRD changed from 10ns to 12.5ns because of the tFAW requirement*/
214 .phy_ctrl_1 = 0x849FF408,
215 .ref_ctrl = 0x00000618,
216 .config_init = 0x80000eb9,
217 .config_final = 0x80001ab9,
218 .zq_config = 0xD00b3215,
223 /*******************************************************
225 * Description: spinning delay to use before udelay works
226 ******************************************************/
227 static inline void delay(unsigned long loops)
229 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
230 "bne 1b" : "=r" (loops) : "0"(loops));
234 void big_delay(unsigned int count)
237 for (i = 0; i < count; i++)
241 void reset_phy(unsigned int base)
243 __raw_writel(__raw_readl(base + IODFT_TLGC) | (1 << 10),
247 /* this flashes the Panda LEDs forever, if called after muxconf */
251 unsigned int v = __raw_readl(OMAP44XX_GPIO_BASE1 + __GPIO_OE);
253 /* set both LED gpio to output */
254 __raw_writel((v & ~(0x03 << 7)), OMAP44XX_GPIO_BASE1 + __GPIO_OE);
256 v = __raw_readl(OMAP44XX_GPIO_BASE1 + __GPIO_DATAOUT);
258 __raw_writel((v & ~(0x03 << 7)),
259 OMAP44XX_GPIO_BASE1 + __GPIO_DATAOUT);
261 __raw_writel((v | (0x03 << 7)),
262 OMAP44XX_GPIO_BASE1 + __GPIO_DATAOUT);
267 /* TODO: FREQ update method is not working so shadow registers programming
268 * is just for same of completeness. This would be safer if auto
269 * trasnitions are working
271 static int emif_config(unsigned int base)
273 const struct ddr_regs *ddr_regs = &ddr_regs_400_mhz_2cs;
275 switch (omap_revision()) {
277 ddr_regs = &ddr_regs_380_mhz;
280 ddr_regs = &ddr_regs_200_mhz_2cs;
285 * set SDRAM CONFIG register
286 * EMIF_SDRAM_CONFIG[31:29] REG_SDRAM_TYPE = 4 for LPDDR2-S4
287 * EMIF_SDRAM_CONFIG[28:27] REG_IBANK_POS = 0
288 * EMIF_SDRAM_CONFIG[13:10] REG_CL = 3
289 * EMIF_SDRAM_CONFIG[6:4] REG_IBANK = 3 - 8 banks
290 * EMIF_SDRAM_CONFIG[3] REG_EBANK = 0 - CS0
291 * EMIF_SDRAM_CONFIG[2:0] REG_PAGESIZE = 2 - 512- 9 column
292 * JDEC specs - S4-2Gb --8 banks -- R0-R13, C0-c8
294 __raw_writel(__raw_readl(base + EMIF_LPDDR2_NVM_CONFIG) & 0xbfffffff,
295 base + EMIF_LPDDR2_NVM_CONFIG);
296 __raw_writel(ddr_regs->config_init, base + EMIF_SDRAM_CONFIG);
298 /* PHY control values */
299 __raw_writel(DDR_PHY_CTRL_1_INIT, base + EMIF_DDR_PHY_CTRL_1);
300 __raw_writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1_SHDW);
303 * EMIF_READ_IDLE_CTRL
305 __raw_writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL);
306 __raw_writel(READ_IDLE_CTRL, base + EMIF_READ_IDLE_CTRL);
311 __raw_writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1);
312 __raw_writel(ddr_regs->tim1, base + EMIF_SDRAM_TIM_1_SHDW);
317 __raw_writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2);
318 __raw_writel(ddr_regs->tim2, base + EMIF_SDRAM_TIM_2_SHDW);
323 __raw_writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3);
324 __raw_writel(ddr_regs->tim3, base + EMIF_SDRAM_TIM_3_SHDW);
326 __raw_writel(ddr_regs->zq_config, base + EMIF_ZQ_CONFIG);
329 * poll MR0 register (DAI bit)
330 * REG_CS[31] = 0 -- Mode register command to CS0
331 * REG_REFRESH_EN[30] = 1 -- Refresh enable after MRW
332 * REG_ADDRESS[7:0] = 00 -- Refresh enable after MRW
335 __raw_writel(MR0_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
337 while (__raw_readl(base + EMIF_LPDDR2_MODE_REG_DATA) & 1)
340 __raw_writel(CS1_MR(MR0_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
342 while (__raw_readl(base + EMIF_LPDDR2_MODE_REG_DATA) & 1)
346 /* set MR10 register */
347 __raw_writel(MR10_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
348 __raw_writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA);
349 __raw_writel(CS1_MR(MR10_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
350 __raw_writel(MR10_ZQINIT, base + EMIF_LPDDR2_MODE_REG_DATA);
352 /* wait for tZQINIT=1us */
355 /* set MR1 register */
356 __raw_writel(MR1_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
357 __raw_writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA);
358 __raw_writel(CS1_MR(MR1_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
359 __raw_writel(ddr_regs->mr1, base + EMIF_LPDDR2_MODE_REG_DATA);
361 /* set MR2 register RL=6 for OPP100 */
362 __raw_writel(MR2_ADDR, base + EMIF_LPDDR2_MODE_REG_CFG);
363 __raw_writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA);
364 __raw_writel(CS1_MR(MR2_ADDR), base + EMIF_LPDDR2_MODE_REG_CFG);
365 __raw_writel(ddr_regs->mr2, base + EMIF_LPDDR2_MODE_REG_DATA);
367 /* Set SDRAM CONFIG register again here with final RL-WL value */
368 __raw_writel(ddr_regs->config_final, base + EMIF_SDRAM_CONFIG);
369 __raw_writel(ddr_regs->phy_ctrl_1, base + EMIF_DDR_PHY_CTRL_1);
372 * EMIF_SDRAM_REF_CTRL
373 * refresh rate = DDR_CLK / reg_refresh_rate
374 * 3.9 uS = (400MHz) / reg_refresh_rate
376 __raw_writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL);
377 __raw_writel(ddr_regs->ref_ctrl, base + EMIF_SDRAM_REF_CTRL_SHDW);
379 /* set MR16 register */
380 __raw_writel(MR16_ADDR | REF_EN, base + EMIF_LPDDR2_MODE_REG_CFG);
381 __raw_writel(0, base + EMIF_LPDDR2_MODE_REG_DATA);
382 __raw_writel(CS1_MR(MR16_ADDR | REF_EN),
383 base + EMIF_LPDDR2_MODE_REG_CFG);
384 __raw_writel(0, base + EMIF_LPDDR2_MODE_REG_DATA);
386 /* LPDDR2 init complete */
390 /*****************************************
392 * Description: Configure DDR
393 * EMIF1 -- CS0 -- DDR1 (256 MB)
394 * EMIF2 -- CS0 -- DDR2 (256 MB)
395 *****************************************/
396 static void ddr_init(void)
398 unsigned int base_addr;
400 switch (omap_revision()) {
403 /* Configurte the Control Module DDRIO device */
404 __raw_writel(0x1c1c1c1c, OMAP44XX_CONTROL_LPDDR2IO1_0);
405 __raw_writel(0x1c1c1c1c, OMAP44XX_CONTROL_LPDDR2IO1_1);
406 __raw_writel(0x1c1c1c1c, OMAP44XX_CONTROL_LPDDR2IO1_2);
407 __raw_writel(0x1c1c1c1c, OMAP44XX_CONTROL_LPDDR2IO2_0);
408 __raw_writel(0x1c1c1c1c, OMAP44XX_CONTROL_LPDDR2IO2_1);
409 __raw_writel(0x1c1c1c1c, OMAP44XX_CONTROL_LPDDR2IO2_2);
410 /* LPDDR2IO set to NMOS PTV !!! really EFUSE2? */
411 __raw_writel(0x00ffc000, OMAP44XX_CONTROL_EFUSE_2);
413 /* Both EMIFs 128 byte interleaved */
414 __raw_writel(0x80540300, DMM_BASE + DMM_LISA_MAP_0);
417 __raw_writel(0x9e9e9e9e, OMAP44XX_CONTROL_LPDDR2IO1_0);
418 __raw_writel(0x9e9e9e9e, OMAP44XX_CONTROL_LPDDR2IO1_1);
419 __raw_writel(0x9e9e9e9e, OMAP44XX_CONTROL_LPDDR2IO1_2);
420 __raw_writel(0x9e9e9e9e, OMAP44XX_CONTROL_LPDDR2IO2_0);
421 __raw_writel(0x9e9e9e9e, OMAP44XX_CONTROL_LPDDR2IO2_1);
422 __raw_writel(0x9e9e9e9e, OMAP44XX_CONTROL_LPDDR2IO2_2);
423 /* LPDDR2IO set to NMOS PTV !!! really EFUSE2? */
424 __raw_writel(0x00ffc000, OMAP44XX_CONTROL_EFUSE_2);
427 /* Both EMIFs 128 byte interleaved */
428 __raw_writel(0x80640300, DMM_BASE + DMM_LISA_MAP_0);
436 __raw_writel(0x00000000, DMM_BASE + DMM_LISA_MAP_2);
437 __raw_writel(0xFF020100, DMM_BASE + DMM_LISA_MAP_3);
439 /* DDR needs to be initialised @ 19.2 MHz
440 * So put core DPLL in bypass mode
441 * Configure the Core DPLL but don't lock it
443 configure_core_dpll_no_lock();
446 * the following is re-enabled because without the EMIF going idle,
447 * the shadow DPLL update scheme can delay for minutes until it is
448 * able to apply the new settings... it waits until EMIF idle.
450 * This is seen in the case the ROM enabled USB boot being tried before
451 * normal boot over MMC.
454 /* No IDLE: BUG in SDC */
455 sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x2);
456 while ((__raw_readl(CM_MEMIF_CLKSTCTRL) & 0x700) != 0x700)
459 __raw_writel(0, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
460 __raw_writel(0, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
462 base_addr = EMIF1_BASE;
463 emif_config(base_addr);
465 /* Configure EMIF24D */
466 base_addr = EMIF2_BASE;
467 emif_config(base_addr);
468 /* Lock Core using shadow CM_SHADOW_FREQ_CONFIG1 */
469 lock_core_dpll_shadow();
470 /* TODO: SDC needs few hacks to get DDR freq update working */
472 /* Set DLL_OVERRIDE = 0 */
473 __raw_writel(0, CM_DLL_CTRL);
477 /* Check for DDR PHY ready for EMIF1 & EMIF2 */
478 while (!(__raw_readl(EMIF1_BASE + EMIF_STATUS) & 4) ||
479 !(__raw_readl(EMIF2_BASE + EMIF_STATUS) & 4))
482 /* Reprogram the DDR PYHY Control register */
483 /* PHY control values */
485 sr32(CM_MEMIF_EMIF_1_CLKCTRL, 0, 32, 0x1);
486 sr32(CM_MEMIF_EMIF_2_CLKCTRL, 0, 32, 0x1);
488 /* Put the Core Subsystem PD to ON State */
490 __raw_writel(1 << 31, EMIF1_BASE + EMIF_PWR_MGMT_CTRL);
491 __raw_writel(1 << 31, EMIF2_BASE + EMIF_PWR_MGMT_CTRL);
494 * In n a specific situation, the OCP interface between the DMM and
496 * 1. A TILER port is used to perform 2D burst writes of
497 * width 1 and height 8
498 * 2. ELLAn port is used to perform reads
499 * 3. All accesses are routed to the same EMIF controller
501 * Work around to avoid this issue REG_SYS_THRESH_MAX value should
502 * be kept higher than default 0x7. As per recommondation 0x0A will
503 * be used for better performance with REG_LL_THRESH_MAX = 0x00
505 if (omap_revision() == OMAP4430_ES1_0) {
506 __raw_writel(0x0A0000FF, EMIF1_BASE + EMIF_L3_CONFIG);
507 __raw_writel(0x0A0000FF, EMIF2_BASE + EMIF_L3_CONFIG);
511 * DMM : DMM_LISA_MAP_0(Section_0)
512 * [31:24] SYS_ADDR 0x80
513 * [22:20] SYS_SIZE 0x7 - 2Gb
514 * [19:18] SDRC_INTLDMM 0x1 - 128 byte
515 * [17:16] SDRC_ADDRSPC 0x0
517 * [7:0] SDRC_ADDR 0X0
519 reset_phy(EMIF1_BASE);
520 reset_phy(EMIF2_BASE);
522 __raw_writel(0, OMAP44XX_SDRC_CS0);
523 __raw_writel(0, OMAP44XX_SDRC_CS0);
525 /* MEMIF Clock Domain -> HW_AUTO */
526 sr32(CM_MEMIF_CLKSTCTRL, 0, 32, 0x3);
528 /*****************************************
529 * Routine: board_init
530 * Description: Early hardware init.
531 *****************************************/
534 unsigned int rev = omap_revision();
538 * If the ROM has started the OTG stuff, stop it and
539 * make it look as if uninitialized for Linux or U-Boot
542 /* hold OTG phy in reset (GPIO_62 -> active low reset) */
544 v = __raw_readl(OMAP44XX_GPIO_BASE2 + __GPIO_OE);
545 __raw_writel((v & ~(1 << 30)), OMAP44XX_GPIO_BASE2 + __GPIO_OE);
547 v = __raw_readl(OMAP44XX_GPIO_BASE2 + __GPIO_DATAOUT);
548 __raw_writel((v & ~(1 << 30)), OMAP44XX_GPIO_BASE2 + __GPIO_DATAOUT);
550 if (rev == OMAP4430_ES1_0)
553 if (__raw_readl(OMAP44XX_GPIO_BASE6 + __GPIO_DATAIN) & (1 << 22)) {
554 /* enable software ioreq */
555 sr32(OMAP44XX_SCRM_AUXCLK3, 8, 1, 0x1);
556 /* set for sys_clk (38.4MHz) */
557 sr32(OMAP44XX_SCRM_AUXCLK3, 1, 2, 0x0);
558 /* set divisor to 2 */
559 sr32(OMAP44XX_SCRM_AUXCLK3, 16, 4, 0x1);
560 /* set the clock source to active */
561 sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
563 sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
565 /* enable software ioreq */
566 sr32(OMAP44XX_SCRM_AUXCLK1, 8, 1, 0x1);
567 /* set for PER_DPLL */
568 sr32(OMAP44XX_SCRM_AUXCLK1, 1, 2, 0x2);
569 /* set divisor to 16 */
570 sr32(OMAP44XX_SCRM_AUXCLK1, 16, 4, 0xf);
571 /* set the clock source to active */
572 sr32(OMAP44XX_SCRM_ALTCLKSRC, 0, 1, 0x1);
574 sr32(OMAP44XX_SCRM_ALTCLKSRC, 2, 2, 0x3);
580 /*************************************************************
581 * Routine: get_mem_type(void) - returns the kind of memory connected
582 * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
583 *************************************************************/
584 u32 get_mem_type(void)
586 /* no nand, so return GPMC_NONE */
590 /*****************************************
591 * Routine: secure_unlock
592 * Description: Setup security registers for access
594 *****************************************/
595 void secure_unlock_mem(void)
597 /* Permission values for registers -Full fledged permissions to all */
598 #define UNLOCK_1 0xFFFFFFFF
599 #define UNLOCK_2 0x00000000
600 #define UNLOCK_3 0x0000FFFF
602 /* Protection Module Register Target APE (PM_RT)*/
603 __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
604 __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
605 __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
606 __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
608 __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
609 __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
610 __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
612 __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
613 __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
614 __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
615 __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
618 __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
619 __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
620 __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
622 __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
625 /**********************************************************
626 * Routine: try_unlock_sram()
627 * Description: If chip is GP/EMU(special) type, unlock the SRAM for
629 ***********************************************************/
630 void try_unlock_memory(void)
632 /* if GP device unlock device SRAM for general use */
633 /* secure code breaks for Secure/Emulation device - HS/E/T*/
637 #if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
638 static int scale_vcores(void)
640 unsigned int rev = omap_revision();
642 /* For VC bypass only VCOREx_CGF_FORCE is necessary and
643 * VCOREx_CFG_VOLTAGE changes can be discarded
645 __raw_writel(0, OMAP44XX_PRM_VC_CFG_I2C_MODE);
646 __raw_writel(0x6026, OMAP44XX_PRM_VC_CFG_I2C_CLK);
648 /* set VCORE1 force VSEL */
649 if (rev == OMAP4430_ES1_0)
650 __raw_writel(0x3B5512, OMAP44XX_PRM_VC_VAL_BYPASS);
652 __raw_writel(0x3A5512, OMAP44XX_PRM_VC_VAL_BYPASS);
654 __raw_writel(__raw_readl(OMAP44XX_PRM_VC_VAL_BYPASS) | 0x1000000,
655 OMAP44XX_PRM_VC_VAL_BYPASS);
656 while (__raw_readl(OMAP44XX_PRM_VC_VAL_BYPASS) & 0x1000000)
659 __raw_writel(__raw_readl(OMAP44XX_PRM_IRQSTATUS_MPU_A9),
660 OMAP44XX_PRM_IRQSTATUS_MPU_A9);
662 /* FIXME: set VCORE2 force VSEL, Check the reset value */
663 if (rev == OMAP4430_ES1_0)
664 __raw_writel(0x315B12, OMAP44XX_PRM_VC_VAL_BYPASS);
666 __raw_writel(0x295B12, OMAP44XX_PRM_VC_VAL_BYPASS);
668 __raw_writel(__raw_readl(OMAP44XX_PRM_VC_VAL_BYPASS) | 0x1000000,
669 OMAP44XX_PRM_VC_VAL_BYPASS);
670 while (__raw_readl(OMAP44XX_PRM_VC_VAL_BYPASS) & 0x1000000)
673 __raw_writel(__raw_readl(OMAP44XX_PRM_IRQSTATUS_MPU_A9),
674 OMAP44XX_PRM_IRQSTATUS_MPU_A9);
676 /*/set VCORE3 force VSEL */
679 __raw_writel(0x316112, OMAP44XX_PRM_VC_VAL_BYPASS);
682 __raw_writel(0x296112, OMAP44XX_PRM_VC_VAL_BYPASS);
686 __raw_writel(0x2A6112, OMAP44XX_PRM_VC_VAL_BYPASS);
689 __raw_writel(__raw_readl(OMAP44XX_PRM_VC_VAL_BYPASS) | 0x1000000,
690 OMAP44XX_PRM_VC_VAL_BYPASS);
691 while (__raw_readl(OMAP44XX_PRM_VC_VAL_BYPASS) & 0x1000000)
694 __raw_writel(__raw_readl(OMAP44XX_PRM_IRQSTATUS_MPU_A9),
695 OMAP44XX_PRM_IRQSTATUS_MPU_A9);
701 /**********************************************************
703 * Description: Does early system init of muxing and clocks.
704 * - Called path is with SRAM stack.
705 **********************************************************/
710 * this is required to survive the muxconf in the case the ROM
713 /* Set VCORE1 = 1.3 V, VCORE2 = VCORE3 = 1.21V */
714 #if defined(CONFIG_MPU_600) || defined(CONFIG_MPU_1000)
724 /* Writing to AuxCR in U-boot using SMI for GP/EMU DEV */
725 /* Currently SMI in Kernel on ES2 devices seems to have an issue
726 * Once that is resolved, we can postpone this config to kernel
728 /* setup_auxcr(get_device_type(), external_boot); */
733 /*******************************************************
734 * Routine: misc_init_r
735 * Description: Init ethernet (done here so udelay works)
736 ********************************************************/
737 int misc_init_r(void)
742 /******************************************************
743 * Routine: wait_for_command_complete
744 * Description: Wait for posting to finish on watchdog
745 ******************************************************/
746 void wait_for_command_complete(unsigned int wd_base)
748 while (__raw_readl(wd_base + WWPS))
752 /*******************************************************************
754 * Description: take the Ethernet controller out of reset and wait
755 * for the EEPROM load to complete.
756 ******************************************************************/
758 /**********************************************
760 * Description: sets uboots idea of sdram size
761 **********************************************/
767 #define CP(x) (CONTROL_PADCONF_##x)
768 #define WK(x) (CONTROL_WKUP_##x)
771 * IDIS - Input Disable
772 * PTD - Pull type Down
774 * DIS - Pull type selection is inactive
775 * EN - Pull type selection is active
777 * The commented string gives the final mux configuration for that pin
780 struct omap4panda_mux {
785 static const struct omap4panda_mux omap4panda_mux[] = {
786 { OMAP44XX_CTRL_BASE + CP(GPMC_AD0),
787 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat0 */ },
788 { OMAP44XX_CTRL_BASE + CP(GPMC_AD1),
789 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat1 */ },
790 { OMAP44XX_CTRL_BASE + CP(GPMC_AD2),
791 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat2 */ },
792 { OMAP44XX_CTRL_BASE + CP(GPMC_AD3),
793 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat3 */ },
794 { OMAP44XX_CTRL_BASE + CP(GPMC_AD4),
795 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat4 */ },
796 { OMAP44XX_CTRL_BASE + CP(GPMC_AD5),
797 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat5 */ },
798 { OMAP44XX_CTRL_BASE + CP(GPMC_AD6),
799 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat6 */ },
800 { OMAP44XX_CTRL_BASE + CP(GPMC_AD7),
801 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_dat7 */ },
802 { OMAP44XX_CTRL_BASE + CP(GPMC_AD8),
803 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M3 /* gpio_32 */ },
804 { OMAP44XX_CTRL_BASE + CP(GPMC_AD9),
805 PTU | IEN | M3 /* gpio_33 */ },
806 { OMAP44XX_CTRL_BASE + CP(GPMC_AD10),
807 PTU | IEN | M3 /* gpio_34 */ },
808 { OMAP44XX_CTRL_BASE + CP(GPMC_AD11),
809 PTU | IEN | M3 /* gpio_35 */ },
810 { OMAP44XX_CTRL_BASE + CP(GPMC_AD12),
811 PTU | IEN | M3 /* gpio_36 */ },
812 { OMAP44XX_CTRL_BASE + CP(GPMC_AD13),
813 PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_37 */ },
814 { OMAP44XX_CTRL_BASE + CP(GPMC_AD14),
815 PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_38 */ },
816 { OMAP44XX_CTRL_BASE + CP(GPMC_AD15),
817 PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_39 */ },
818 { OMAP44XX_CTRL_BASE + CP(GPMC_A16), M3 /* gpio_40 */ },
819 { OMAP44XX_CTRL_BASE + CP(GPMC_A17), PTD | M3 /* gpio_41 */ },
820 { OMAP44XX_CTRL_BASE + CP(GPMC_A18),
821 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row6 */ },
822 { OMAP44XX_CTRL_BASE + CP(GPMC_A19),
823 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row7 */ },
824 { OMAP44XX_CTRL_BASE + CP(GPMC_A20),
825 IEN | M3 /* gpio_44 */ },
826 { OMAP44XX_CTRL_BASE + CP(GPMC_A21), M3 /* gpio_45 */ },
827 { OMAP44XX_CTRL_BASE + CP(GPMC_A22), M3 /* gpio_46 */ },
828 { OMAP44XX_CTRL_BASE + CP(GPMC_A23),
829 OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_col7 */ },
830 { OMAP44XX_CTRL_BASE + CP(GPMC_A24), PTD | M3 /* gpio_48 */ },
831 { OMAP44XX_CTRL_BASE + CP(GPMC_A25), PTD | M3 /* gpio_49 */ },
832 { OMAP44XX_CTRL_BASE + CP(GPMC_NCS0), M3 /* gpio_50 */ },
833 { OMAP44XX_CTRL_BASE + CP(GPMC_NCS1), IEN | M3 /* gpio_51 */ },
834 { OMAP44XX_CTRL_BASE + CP(GPMC_NCS2), IEN | M3 /* gpio_52 */ },
835 { OMAP44XX_CTRL_BASE + CP(GPMC_NCS3), IEN | M3 /* gpio_53 */ },
836 { OMAP44XX_CTRL_BASE + CP(GPMC_NWP), M3 /* gpio_54 */ },
837 { OMAP44XX_CTRL_BASE + CP(GPMC_CLK), PTD | M3 /* gpio_55 */ },
838 { OMAP44XX_CTRL_BASE + CP(GPMC_NADV_ALE), M3 /* gpio_56 */ },
839 { OMAP44XX_CTRL_BASE + CP(GPMC_NOE),
840 PTU | IEN | OFF_EN | OFF_OUT_PTD | M1 /* sdmmc2_clk */ },
841 { OMAP44XX_CTRL_BASE + CP(GPMC_NWE),
842 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* sdmmc2_cmd */ },
843 { OMAP44XX_CTRL_BASE + CP(GPMC_NBE0_CLE), M3 /* gpio_59 */ },
844 { OMAP44XX_CTRL_BASE + CP(GPMC_NBE1), PTD | M3 /* gpio_60 */ },
845 { OMAP44XX_CTRL_BASE + CP(GPMC_WAIT0), PTU | IEN | M3 /* gpio_61 */ },
846 { OMAP44XX_CTRL_BASE + CP(GPMC_WAIT1),
847 PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_62 */ },
848 { OMAP44XX_CTRL_BASE + CP(C2C_DATA11), PTD | M3 /* gpio_100 */ },
849 { OMAP44XX_CTRL_BASE + CP(C2C_DATA12), PTD | IEN | M3 /* gpio_101 */ },
850 { OMAP44XX_CTRL_BASE + CP(C2C_DATA13), PTD | M3 /* gpio_102 */ },
851 { OMAP44XX_CTRL_BASE + CP(C2C_DATA14), M1 /* dsi2_te0 */ },
852 { OMAP44XX_CTRL_BASE + CP(C2C_DATA15), PTD | M3 /* gpio_104 */ },
853 { OMAP44XX_CTRL_BASE + CP(HDMI_HPD), M0 /* hdmi_hpd */ },
854 { OMAP44XX_CTRL_BASE + CP(HDMI_CEC), M0 /* hdmi_cec */ },
855 { OMAP44XX_CTRL_BASE + CP(HDMI_DDC_SCL), PTU | M0 /* hdmi_ddc_scl */ },
856 { OMAP44XX_CTRL_BASE + CP(HDMI_DDC_SDA),
857 PTU | IEN | M0 /* hdmi_ddc_sda */ },
858 { OMAP44XX_CTRL_BASE + CP(CSI21_DX0), IEN | M0 /* csi21_dx0 */ },
859 { OMAP44XX_CTRL_BASE + CP(CSI21_DY0), IEN | M0 /* csi21_dy0 */ },
860 { OMAP44XX_CTRL_BASE + CP(CSI21_DX1), IEN | M0 /* csi21_dx1 */ },
861 { OMAP44XX_CTRL_BASE + CP(CSI21_DY1), IEN | M0 /* csi21_dy1 */ },
862 { OMAP44XX_CTRL_BASE + CP(CSI21_DX2), IEN | M0 /* csi21_dx2 */ },
863 { OMAP44XX_CTRL_BASE + CP(CSI21_DY2), IEN | M0 /* csi21_dy2 */ },
864 { OMAP44XX_CTRL_BASE + CP(CSI21_DX3), PTD | M7 /* csi21_dx3 */ },
865 { OMAP44XX_CTRL_BASE + CP(CSI21_DY3), PTD | M7 /* csi21_dy3 */ },
866 { OMAP44XX_CTRL_BASE + CP(CSI21_DX4),
867 PTD | OFF_EN | OFF_PD | OFF_IN | M7 /* csi21_dx4 */ },
868 { OMAP44XX_CTRL_BASE + CP(CSI21_DY4),
869 PTD | OFF_EN | OFF_PD | OFF_IN | M7 /* csi21_dy4 */ },
870 { OMAP44XX_CTRL_BASE + CP(CSI22_DX0), IEN | M0 /* csi22_dx0 */ },
871 { OMAP44XX_CTRL_BASE + CP(CSI22_DY0), IEN | M0 /* csi22_dy0 */ },
872 { OMAP44XX_CTRL_BASE + CP(CSI22_DX1), IEN | M0 /* csi22_dx1 */ },
873 { OMAP44XX_CTRL_BASE + CP(CSI22_DY1), IEN | M0 /* csi22_dy1 */ },
874 { OMAP44XX_CTRL_BASE + CP(CAM_SHUTTER),
875 OFF_EN | OFF_PD | OFF_OUT_PTD | M0 /* cam_shutter */ },
876 { OMAP44XX_CTRL_BASE + CP(CAM_STROBE),
877 OFF_EN | OFF_PD | OFF_OUT_PTD | M0 /* cam_strobe */ },
878 { OMAP44XX_CTRL_BASE + CP(CAM_GLOBALRESET),
879 PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3 /* gpio_83 */ },
880 { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_CLK),
881 PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_clk */ },
882 { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_STP),
883 OFF_EN | OFF_OUT_PTD | M4 /* usbb1_ulpiphy_stp */ },
884 { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DIR),
885 IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dir */ },
886 { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_NXT),
887 IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_nxt */ },
888 { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT0),
889 IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat0 */ },
890 { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT1),
891 IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat1 */ },
892 { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT2),
893 IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat2 */ },
894 { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT3),
895 IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat3 */ },
896 { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT4),
897 IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat4 */ },
898 { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT5),
899 IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat5 */ },
900 { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT6),
901 IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat6 */ },
902 { OMAP44XX_CTRL_BASE + CP(USBB1_ULPITLL_DAT7),
903 IEN | OFF_EN | OFF_PD | OFF_IN | M4 /* usbb1_ulpiphy_dat7 */ },
904 { OMAP44XX_CTRL_BASE + CP(USBB1_HSIC_DATA),
905 IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* usbb1_hsic_data */ },
906 { OMAP44XX_CTRL_BASE + CP(USBB1_HSIC_STROBE),
907 IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* usbb1_hsic_strobe */ },
908 { OMAP44XX_CTRL_BASE + CP(USBC1_ICUSB_DP),
909 IEN | M0 /* usbc1_icusb_dp */ },
910 { OMAP44XX_CTRL_BASE + CP(USBC1_ICUSB_DM),
911 IEN | M0 /* usbc1_icusb_dm */ },
912 { OMAP44XX_CTRL_BASE + CP(SDMMC1_CLK),
913 PTU | OFF_EN | OFF_OUT_PTD | M0 /* sdmmc1_clk */ },
914 { OMAP44XX_CTRL_BASE + CP(SDMMC1_CMD),
915 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_cmd */ },
916 { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT0),
917 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat0 */ },
918 { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT1),
919 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat1 */ },
920 { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT2),
921 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat2 */ },
922 { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT3),
923 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat3 */ },
924 { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT4),
925 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat4 */ },
926 { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT5),
927 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat5 */ },
928 { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT6),
929 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat6 */ },
930 { OMAP44XX_CTRL_BASE + CP(SDMMC1_DAT7),
931 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc1_dat7 */ },
932 { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP2_CLKX),
933 IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_mcbsp2_clkx */ },
934 { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP2_DR),
935 IEN | OFF_EN | OFF_OUT_PTD | M0 /* abe_mcbsp2_dr */ },
936 { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP2_DX),
937 OFF_EN | OFF_OUT_PTD | M0 /* abe_mcbsp2_dx */ },
938 { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP2_FSX),
939 IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_mcbsp2_fsx */ },
940 { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP1_CLKX),
941 IEN | M1 /* abe_slimbus1_clock */ },
942 { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP1_DR),
943 IEN | M1 /* abe_slimbus1_data */ },
944 { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP1_DX),
945 OFF_EN | OFF_OUT_PTD | M0 /* abe_mcbsp1_dx */ },
946 { OMAP44XX_CTRL_BASE + CP(ABE_MCBSP1_FSX),
947 IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_mcbsp1_fsx */ },
948 { OMAP44XX_CTRL_BASE + CP(ABE_PDM_UL_DATA),
949 PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_pdm_ul_data */ },
950 { OMAP44XX_CTRL_BASE + CP(ABE_PDM_DL_DATA),
951 PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_pdm_dl_data */ },
952 { OMAP44XX_CTRL_BASE + CP(ABE_PDM_FRAME),
953 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_pdm_frame */ },
954 { OMAP44XX_CTRL_BASE + CP(ABE_PDM_LB_CLK),
955 PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_pdm_lb_clk */ },
956 { OMAP44XX_CTRL_BASE + CP(ABE_CLKS),
957 PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* abe_clks */ },
958 { OMAP44XX_CTRL_BASE + CP(ABE_DMIC_CLK1), M0 /* abe_dmic_clk1 */ },
959 { OMAP44XX_CTRL_BASE + CP(ABE_DMIC_DIN1),
960 IEN | M0 /* abe_dmic_din1 */ },
961 { OMAP44XX_CTRL_BASE + CP(ABE_DMIC_DIN2),
962 IEN | M0 /* abe_dmic_din2 */ },
963 { OMAP44XX_CTRL_BASE + CP(ABE_DMIC_DIN3),
964 IEN | M0 /* abe_dmic_din3 */ },
965 { OMAP44XX_CTRL_BASE + CP(UART2_CTS), PTU | IEN | M0 /* uart2_cts */ },
966 { OMAP44XX_CTRL_BASE + CP(UART2_RTS), M0 /* uart2_rts */ },
967 { OMAP44XX_CTRL_BASE + CP(UART2_RX), PTU | IEN | M0 /* uart2_rx */ },
968 { OMAP44XX_CTRL_BASE + CP(UART2_TX), M0 /* uart2_tx */ },
969 { OMAP44XX_CTRL_BASE + CP(HDQ_SIO), M3 /* gpio_127 */ },
970 { OMAP44XX_CTRL_BASE + CP(I2C1_SCL), PTU | IEN | M0 /* i2c1_scl */ },
971 { OMAP44XX_CTRL_BASE + CP(I2C1_SDA), PTU | IEN | M0 /* i2c1_sda */ },
972 { OMAP44XX_CTRL_BASE + CP(I2C2_SCL), PTU | IEN | M0 /* i2c2_scl */ },
973 { OMAP44XX_CTRL_BASE + CP(I2C2_SDA), PTU | IEN | M0 /* i2c2_sda */ },
974 { OMAP44XX_CTRL_BASE + CP(I2C3_SCL), PTU | IEN | M0 /* i2c3_scl */ },
975 { OMAP44XX_CTRL_BASE + CP(I2C3_SDA), PTU | IEN | M0 /* i2c3_sda */ },
976 { OMAP44XX_CTRL_BASE + CP(I2C4_SCL), PTU | IEN | M0 /* i2c4_scl */ },
977 { OMAP44XX_CTRL_BASE + CP(I2C4_SDA), PTU | IEN | M0 /* i2c4_sda */ },
978 { OMAP44XX_CTRL_BASE + CP(MCSPI1_CLK),
979 IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi1_clk */ },
980 { OMAP44XX_CTRL_BASE + CP(MCSPI1_SOMI),
981 IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi1_somi */ },
982 { OMAP44XX_CTRL_BASE + CP(MCSPI1_SIMO),
983 IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi1_simo */ },
984 { OMAP44XX_CTRL_BASE + CP(MCSPI1_CS0),
985 PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi1_cs0 */ },
986 { OMAP44XX_CTRL_BASE + CP(MCSPI1_CS1),
987 PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M3 /* mcspi1_cs1 */ },
988 { OMAP44XX_CTRL_BASE + CP(MCSPI1_CS2),
989 PTU | OFF_EN | OFF_OUT_PTU | M3 /* gpio_139 */ },
990 { OMAP44XX_CTRL_BASE + CP(MCSPI1_CS3), PTU | IEN | M3 /* gpio_140 */ },
991 { OMAP44XX_CTRL_BASE + CP(UART3_CTS_RCTX),
992 PTU | IEN | M0 /* uart3_tx */ },
993 { OMAP44XX_CTRL_BASE + CP(UART3_RTS_SD), M0 /* uart3_rts_sd */ },
994 { OMAP44XX_CTRL_BASE + CP(UART3_RX_IRRX), IEN | M0 /* uart3_rx */ },
995 { OMAP44XX_CTRL_BASE + CP(UART3_TX_IRTX), M0 /* uart3_tx */ },
996 { OMAP44XX_CTRL_BASE + CP(SDMMC5_CLK),
997 PTU | IEN | OFF_EN | OFF_OUT_PTD | M0 /* sdmmc5_clk */ },
998 { OMAP44XX_CTRL_BASE + CP(SDMMC5_CMD),
999 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_cmd */ },
1000 { OMAP44XX_CTRL_BASE + CP(SDMMC5_DAT0),
1001 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_dat0 */ },
1002 { OMAP44XX_CTRL_BASE + CP(SDMMC5_DAT1),
1003 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_dat1 */ },
1004 { OMAP44XX_CTRL_BASE + CP(SDMMC5_DAT2),
1005 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_dat2 */ },
1006 { OMAP44XX_CTRL_BASE + CP(SDMMC5_DAT3),
1007 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* sdmmc5_dat3 */ },
1008 { OMAP44XX_CTRL_BASE + CP(MCSPI4_CLK),
1009 IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi4_clk */ },
1010 { OMAP44XX_CTRL_BASE + CP(MCSPI4_SIMO),
1011 IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi4_simo */ },
1012 { OMAP44XX_CTRL_BASE + CP(MCSPI4_SOMI),
1013 IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi4_somi */ },
1014 { OMAP44XX_CTRL_BASE + CP(MCSPI4_CS0),
1015 PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* mcspi4_cs0 */ },
1016 { OMAP44XX_CTRL_BASE + CP(UART4_RX), IEN | M0 /* uart4_rx */ },
1017 { OMAP44XX_CTRL_BASE + CP(UART4_TX), M0 /* uart4_tx */ },
1018 { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_CLK),
1019 IEN | M3 /* gpio_157 */ },
1020 { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_STP),
1021 IEN | M5 /* dispc2_data23 */ },
1022 { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DIR),
1023 IEN | M5 /* dispc2_data22 */ },
1024 { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_NXT),
1025 IEN | M5 /* dispc2_data21 */ },
1026 { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT0),
1027 IEN | M5 /* dispc2_data20 */ },
1028 { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT1),
1029 IEN | M5 /* dispc2_data19 */ },
1030 { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT2),
1031 IEN | M5 /* dispc2_data18 */ },
1032 { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT3),
1033 IEN | M5 /* dispc2_data15 */ },
1034 { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT4),
1035 IEN | M5 /* dispc2_data14 */ },
1036 { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT5),
1037 IEN | M5 /* dispc2_data13 */ },
1038 { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT6),
1039 IEN | M5 /* dispc2_data12 */ },
1040 { OMAP44XX_CTRL_BASE + CP(USBB2_ULPITLL_DAT7),
1041 IEN | M5 /* dispc2_data11 */ },
1042 { OMAP44XX_CTRL_BASE + CP(USBB2_HSIC_DATA),
1043 PTD | OFF_EN | OFF_OUT_PTU | M3 /* gpio_169 */ },
1044 { OMAP44XX_CTRL_BASE + CP(USBB2_HSIC_STROBE),
1045 PTD | OFF_EN | OFF_OUT_PTU | M3 /* gpio_170 */ },
1046 { OMAP44XX_CTRL_BASE + CP(UNIPRO_TX0), PTD | IEN | M3 /* gpio_171 */ },
1047 { OMAP44XX_CTRL_BASE + CP(UNIPRO_TY0),
1048 OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_col1 */ },
1049 { OMAP44XX_CTRL_BASE + CP(UNIPRO_TX1),
1050 OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_col2 */ },
1051 { OMAP44XX_CTRL_BASE + CP(UNIPRO_TY1),
1052 OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_col3 */ },
1053 { OMAP44XX_CTRL_BASE + CP(UNIPRO_TX2), PTU | IEN | M3 /* gpio_0 */ },
1054 { OMAP44XX_CTRL_BASE + CP(UNIPRO_TY2), PTU | IEN | M3 /* gpio_1 */ },
1055 { OMAP44XX_CTRL_BASE + CP(UNIPRO_RX0),
1056 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row0 */ },
1057 { OMAP44XX_CTRL_BASE + CP(UNIPRO_RY0),
1058 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row1 */ },
1059 { OMAP44XX_CTRL_BASE + CP(UNIPRO_RX1),
1060 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row2 */ },
1061 { OMAP44XX_CTRL_BASE + CP(UNIPRO_RY1),
1062 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row3 */ },
1063 { OMAP44XX_CTRL_BASE + CP(UNIPRO_RX2),
1064 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row4 */ },
1065 { OMAP44XX_CTRL_BASE + CP(UNIPRO_RY2),
1066 PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1 /* kpd_row5 */ },
1067 { OMAP44XX_CTRL_BASE + CP(USBA0_OTG_CE),
1068 PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M0 /* usba0_otg_ce */ },
1069 { OMAP44XX_CTRL_BASE + CP(USBA0_OTG_DP),
1070 IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* usba0_otg_dp */ },
1071 { OMAP44XX_CTRL_BASE + CP(USBA0_OTG_DM),
1072 IEN | OFF_EN | OFF_PD | OFF_IN | M0 /* usba0_otg_dm */ },
1073 { OMAP44XX_CTRL_BASE + CP(FREF_CLK1_OUT), M0 /* fref_clk1_out */ },
1074 { OMAP44XX_CTRL_BASE + CP(FREF_CLK2_OUT),
1075 PTD | IEN | M3 /* gpio_182 */ },
1076 { OMAP44XX_CTRL_BASE + CP(SYS_NIRQ1), PTU | IEN | M0 /* sys_nirq1 */ },
1077 { OMAP44XX_CTRL_BASE + CP(SYS_NIRQ2), M7 /* sys_nirq2 */ },
1078 { OMAP44XX_CTRL_BASE + CP(SYS_BOOT0), PTU | IEN | M3 /* gpio_184 */ },
1079 { OMAP44XX_CTRL_BASE + CP(SYS_BOOT1), M3 /* gpio_185 */ },
1080 { OMAP44XX_CTRL_BASE + CP(SYS_BOOT2), PTD | IEN | M3 /* gpio_186 */ },
1081 { OMAP44XX_CTRL_BASE + CP(SYS_BOOT3), M3 /* gpio_187 */ },
1082 { OMAP44XX_CTRL_BASE + CP(SYS_BOOT4), M3 /* gpio_188 */ },
1083 { OMAP44XX_CTRL_BASE + CP(SYS_BOOT5), PTD | IEN | M3 /* gpio_189 */ },
1084 { OMAP44XX_CTRL_BASE + CP(DPM_EMU0), IEN | M0 /* dpm_emu0 */ },
1085 { OMAP44XX_CTRL_BASE + CP(DPM_EMU1), IEN | M0 /* dpm_emu1 */ },
1086 { OMAP44XX_CTRL_BASE + CP(DPM_EMU2), IEN | M0 /* dpm_emu2 */ },
1087 { OMAP44XX_CTRL_BASE + CP(DPM_EMU3), IEN | M5 /* dispc2_data10 */ },
1088 { OMAP44XX_CTRL_BASE + CP(DPM_EMU4), IEN | M5 /* dispc2_data9 */ },
1089 { OMAP44XX_CTRL_BASE + CP(DPM_EMU5), IEN | M5 /* dispc2_data16 */ },
1090 { OMAP44XX_CTRL_BASE + CP(DPM_EMU6), IEN | M5 /* dispc2_data17 */ },
1091 { OMAP44XX_CTRL_BASE + CP(DPM_EMU7), IEN | M5 /* dispc2_hsync */ },
1092 { OMAP44XX_CTRL_BASE + CP(DPM_EMU8), IEN | M5 /* dispc2_pclk */ },
1093 { OMAP44XX_CTRL_BASE + CP(DPM_EMU9), IEN | M5 /* dispc2_vsync */ },
1094 { OMAP44XX_CTRL_BASE + CP(DPM_EMU10), IEN | M5 /* dispc2_de */ },
1095 { OMAP44XX_CTRL_BASE + CP(DPM_EMU11), IEN | M5 /* dispc2_data8 */ },
1096 { OMAP44XX_CTRL_BASE + CP(DPM_EMU12), IEN | M5 /* dispc2_data7 */ },
1097 { OMAP44XX_CTRL_BASE + CP(DPM_EMU13), IEN | M5 /* dispc2_data6 */ },
1098 { OMAP44XX_CTRL_BASE + CP(DPM_EMU14), IEN | M5 /* dispc2_data5 */ },
1099 { OMAP44XX_CTRL_BASE + CP(DPM_EMU15), IEN | M5 /* dispc2_data4 */ },
1100 { OMAP44XX_CTRL_BASE + CP(DPM_EMU16), M3 /* gpio_27 */ },
1101 { OMAP44XX_CTRL_BASE + CP(DPM_EMU17), IEN | M5 /* dispc2_data2 */ },
1102 { OMAP44XX_CTRL_BASE + CP(DPM_EMU18), IEN | M5 /* dispc2_data1 */ },
1103 { OMAP44XX_CTRL_BASE + CP(DPM_EMU19), IEN | M5 /* dispc2_data0 */ },
1104 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SIM_IO), IEN | M0 /* sim_io */ },
1105 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SIM_CLK), M0 /* sim_clk */ },
1106 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SIM_RESET), M0 /* sim_reset */ },
1107 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SIM_CD),
1108 PTU | IEN | M0 /* sim_cd */ },
1109 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SIM_PWRCTRL),
1110 M0 /* sim_pwrctrl */ },
1111 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SR_SCL),
1112 PTU | IEN | M0 /* sr_scl */ },
1113 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SR_SDA),
1114 PTU | IEN | M0 /* sr_sda */ },
1115 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_XTAL_IN), M0 /* # */ },
1116 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_SLICER_IN),
1117 M0 /* fref_slicer_in */ },
1118 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK_IOREQ),
1119 M0 /* fref_clk_ioreq */ },
1120 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_CLK0_OUT),
1121 M2 /* sys_drm_msecure */ },
1122 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK3_REQ),
1123 PTU | IEN | M0 /* # */ },
1124 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_CLK3_OUT),
1125 M0 /* fref_clk3_out */ },
1126 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK4_REQ),
1127 PTU | IEN | M0 /* # */ },
1128 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_CLK4_OUT), M0 /* # */ },
1129 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SYS_32K), IEN | M0 /* sys_32k */ },
1130 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SYS_NRESPWRON),
1131 M0 /* sys_nrespwron */ },
1132 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SYS_NRESWARM),
1133 M0 /* sys_nreswarm */ },
1134 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SYS_PWR_REQ),
1135 PTU | M0 /* sys_pwr_req */ },
1136 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SYS_PWRON_RESET),
1137 M3 /* gpio_wk29 */ },
1138 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_SYS_BOOT6),
1139 IEN | M3 /* gpio_wk9 */ },
1140 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_SYS_BOOT7),
1141 IEN | M3 /* gpio_wk10 */ },
1142 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK3_REQ),
1143 M3 /* gpio_wk30 */ },
1144 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD1_FREF_CLK4_REQ), M3 /* gpio_wk7 */ },
1145 { OMAP44XX_WKUP_CTRL_BASE + WK(PAD0_FREF_CLK4_OUT), M3 /* gpio_wk8 */ },
1148 /**********************************************************
1149 * Routine: set_muxconf_regs
1150 * Description: Setting up the configuration Mux registers
1151 * specific to the hardware. Many pins need
1152 * to be moved from protect to primary mode.
1153 *********************************************************/
1154 void set_muxconf_regs(void)
1158 for (n = 0; n < sizeof omap4panda_mux / sizeof omap4panda_mux[0]; n++)
1159 __raw_writew(omap4panda_mux[n].value, omap4panda_mux[n].ads);
1162 /******************************************************************************
1163 * Routine: update_mux()
1164 * Description:Update balls which are different between boards. All should be
1165 * updated to match functionality. However, I'm only updating ones
1166 * which I'll be using for now. When power comes into play they
1167 * all need updating.
1168 *****************************************************************************/
1169 void update_mux(u32 btype, u32 mtype)
1174 void board_hang(void)