spi: zynq_spi: Add fdt support in driver
authorJagan Teki <jteki@openedev.com>
Fri, 26 Jun 2015 19:21:34 +0000 (00:51 +0530)
committerJagan Teki <jteki@openedev.com>
Wed, 1 Jul 2015 15:45:03 +0000 (21:15 +0530)
Now zynq spi driver platform data is controlled by devicetree,
enable the status by saying "okay" on respective board dts to use
the devicetree generated platdata.

Ex:
&spi1 {
status = "okay";
};

Signed-off-by: Jagan Teki <jteki@openedev.com>
Acked-by: Simon Glass <sjg@chromium.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: Jagan Teki <jteki@openedev.com>
arch/arm/dts/zynq-7000.dtsi
doc/device-tree-bindings/spi/spi-zynq.txt
drivers/spi/zynq_spi.c

index f66f8dc..9207159 100644 (file)
                        interrupts = <0 26 4>;
                        clocks = <&clkc 25>, <&clkc 34>;
                        clock-names = "ref_clk", "pclk";
+                       spi-max-frequency = <166666700>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                };
                        interrupts = <0 49 4>;
                        clocks = <&clkc 26>, <&clkc 35>;
                        clock-names = "ref_clk", "pclk";
+                       spi-max-frequency = <166666700>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                };
index a7c2757..f397a36 100644 (file)
@@ -11,6 +11,7 @@ Required properties:
 - clocks               : Clock phandles (see clock bindings for details).
 - clock-names          : List of input clock names - "ref_clk", "pclk"
                          (See clock bindings for details).
+- spi-max-frequency    : Maximum SPI clocking speed of device in Hz
 
 Example:
 
@@ -22,6 +23,7 @@ Example:
                interrupts = <0 26 4>;
                clocks = <&clkc 25>, <&clkc 34>;
                clock-names = "ref_clk", "pclk";
+               spi-max-frequency = <166666700>;
                #address-cells = <1>;
                #size-cells = <0>;
        } ;
index 50fb1aa..c5c3e10 100644 (file)
 #include <errno.h>
 #include <malloc.h>
 #include <spi.h>
+#include <fdtdec.h>
 #include <asm/io.h>
 #include <asm/arch/hardware.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
 #define ZYNQ_SPI_CR_MSA_MASK           (1 << 15)       /* Manual start enb */
 #define ZYNQ_SPI_CR_MCS_MASK           (1 << 14)       /* Manual chip select */
@@ -63,22 +66,22 @@ struct zynq_spi_priv {
        u32 freq;               /* required frequency */
 };
 
-static inline struct zynq_spi_regs *get_zynq_spi_regs(struct udevice *bus)
-{
-       if (bus->seq)
-               return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR1;
-       else
-               return (struct zynq_spi_regs *)ZYNQ_SPI_BASEADDR0;
-}
-
 static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
 {
        struct zynq_spi_platdata *plat = bus->platdata;
+       const void *blob = gd->fdt_blob;
+       int node = bus->of_offset;
+
+       plat->regs = (struct zynq_spi_regs *)fdtdec_get_addr(blob, node, "reg");
 
-       plat->regs = get_zynq_spi_regs(bus);
-       plat->frequency = 166666700;
+       /* FIXME: Use 250MHz as a suitable default */
+       plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
+                                       250000000);
        plat->speed_hz = plat->frequency / 2;
 
+       debug("zynq_spi_ofdata_to_platdata: regs=%p max-frequency=%d\n",
+             plat->regs, plat->frequency);
+
        return 0;
 }