MIPS: Move cache sizes to Kconfig

Move details of the L1 cache line sizes & total sizes into Kconfig,
defaulting to 0. A new CONFIG_SYS_CACHE_SIZE_AUTO Kconfig entry is
introduced to allow platforms to select auto-detection of cache sizes,
and it defaults to being enabled if none of the cache sizes are set by
the configuration (ie. sizes are all the default 0), and code is
adjusted to #ifdef on that rather than on the definition of the sizes
(which will always be defined even if 0).

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a929452..a79224e 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -246,6 +246,34 @@ config SWAP_IO_SPACE
 config SYS_MIPS_CACHE_INIT_RAM_LOAD
        bool
 
+config SYS_DCACHE_SIZE
+       int
+       default 0
+       help
+         The total size of the L1 Dcache, if known at compile time.
+
+config SYS_ICACHE_SIZE
+       int
+       default 0
+       help
+         The total size of the L1 ICache, if known at compile time.
+
+config SYS_CACHELINE_SIZE
+       int
+       default 0
+       help
+         The size of L1 cache lines, if known at compile time.
+
+config SYS_CACHE_SIZE_AUTO
+       def_bool y if SYS_DCACHE_SIZE = 0 && SYS_ICACHE_SIZE = 0 && \
+               SYS_CACHELINE_SIZE = 0
+       help
+         Select this (or let it be auto-selected by not defining any cache
+         sizes) in order to allow U-Boot to automatically detect the sizes
+         of caches at runtime. This has a small cost in code size & runtime
+         so if you know the cache configuration for your system at compile
+         time it would be beneficial to configure it.
+
 config MIPS_L1_CACHE_SHIFT_4
        bool
 

diff --git a/arch/mips/lib/cache.c b/arch/mips/lib/cache.c
index 7482005..fbaafee 100644 (file)
--- a/arch/mips/lib/cache.c
+++ b/arch/mips/lib/cache.c
@@ -9,7 +9,7 @@
 #include <asm/cacheops.h>
 #include <asm/mipsregs.h>
 
-#ifdef CONFIG_SYS_CACHELINE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 
 static inline unsigned long icache_line_size(void)
 {

diff --git a/arch/mips/lib/cache_init.S b/arch/mips/lib/cache_init.S
index 08b7c3a..4bb9a17 100644 (file)
--- a/arch/mips/lib/cache_init.S
+++ b/arch/mips/lib/cache_init.S
@@ -99,14 +99,14 @@
  *
  */
 LEAF(mips_cache_reset)
-#ifdef CONFIG_SYS_ICACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
        li      t2, CONFIG_SYS_ICACHE_SIZE
        li      t8, CONFIG_SYS_CACHELINE_SIZE
 #else
        l1_info t2, t8, MIPS_CONF1_IA_SHF
 #endif
 
-#ifdef CONFIG_SYS_DCACHE_SIZE
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
        li      t3, CONFIG_SYS_DCACHE_SIZE
        li      t9, CONFIG_SYS_CACHELINE_SIZE
 #else
@@ -116,7 +116,7 @@ LEAF(mips_cache_reset)
 #ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
 
        /* Determine the largest L1 cache size */
-#if defined(CONFIG_SYS_ICACHE_SIZE) && defined(CONFIG_SYS_DCACHE_SIZE)
+#ifndef CONFIG_SYS_CACHE_SIZE_AUTO
 #if CONFIG_SYS_ICACHE_SIZE > CONFIG_SYS_DCACHE_SIZE
        li      v0, CONFIG_SYS_ICACHE_SIZE
 #else

diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig
index 342ec59..1715a28 100644 (file)
--- a/board/dbau1x00/Kconfig
+++ b/board/dbau1x00/Kconfig
@@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
        default 0xbfc00000
 
+config SYS_DCACHE_SIZE
+       default 16384
+
+config SYS_ICACHE_SIZE
+       default 16384
+
+config SYS_CACHELINE_SIZE
+       default 32
+
 menu "dbau1x00 board options"
 
 choice

diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
index 535a77b..5bb6f03 100644 (file)
--- a/board/micronas/vct/Kconfig
+++ b/board/micronas/vct/Kconfig
@@ -12,6 +12,15 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
        default 0x87000000
 
+config SYS_DCACHE_SIZE
+       default 16384
+
+config SYS_ICACHE_SIZE
+       default 16384
+
+config SYS_CACHELINE_SIZE
+       default 32
+
 menu "vct board options"
 
 choice

diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig
index 236a410..27b2ef0 100644 (file)
--- a/board/pb1x00/Kconfig
+++ b/board/pb1x00/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
        default 0x83800000
 
+config SYS_DCACHE_SIZE
+       default 16384
+
+config SYS_ICACHE_SIZE
+       default 16384
+
+config SYS_CACHELINE_SIZE
+       default 32
+
 endif

diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
index c3ecc8f..f28ea1c 100644 (file)
--- a/board/qca/ap121/Kconfig
+++ b/board/qca/ap121/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
        default 0x9f000000
 
+config SYS_DCACHE_SIZE
+       default 32768
+
+config SYS_ICACHE_SIZE
+       default 65536
+
+config SYS_CACHELINE_SIZE
+       default 32
+
 endif

diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
index 5ea5d6f..ff02236 100644 (file)
--- a/board/qca/ap143/Kconfig
+++ b/board/qca/ap143/Kconfig
@@ -12,4 +12,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
        default 0x9f000000
 
+config SYS_DCACHE_SIZE
+       default 32768
+
+config SYS_ICACHE_SIZE
+       default 65536
+
+config SYS_CACHELINE_SIZE
+       default 32
+
 endif

diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
index 3de1f44..66957e7 100644 (file)
--- a/board/qemu-mips/Kconfig
+++ b/board/qemu-mips/Kconfig
@@ -11,4 +11,13 @@ config SYS_TEXT_BASE
        default 0xbfc00000 if 32BIT
        default 0xffffffffbfc00000 if 64BIT
 
+config SYS_DCACHE_SIZE
+       default 16384
+
+config SYS_ICACHE_SIZE
+       default 16384
+
+config SYS_CACHELINE_SIZE
+       default 32
+
 endif

diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
index 65785bd..ded7f9b 100644 (file)
--- a/board/tplink/wdr4300/Kconfig
+++ b/board/tplink/wdr4300/Kconfig
@@ -15,4 +15,13 @@ config SYS_CONFIG_NAME
 config SYS_TEXT_BASE
        default 0xa1000000
 
+config SYS_DCACHE_SIZE
+       default 32768
+
+config SYS_ICACHE_SIZE
+       default 65536
+
+config SYS_CACHELINE_SIZE
+       default 32
+
 endif

diff --git a/include/configs/ap121.h b/include/configs/ap121.h
index 6f69f31..f069d50 100644 (file)
--- a/include/configs/ap121.h
+++ b/include/configs/ap121.h
@@ -15,11 +15,6 @@
 #define CONFIG_SYS_MHZ                  200
 #define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE          0x8000
-#define CONFIG_SYS_ICACHE_SIZE          0x10000
-#define CONFIG_SYS_CACHELINE_SIZE       32
-
 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN           0x40000

diff --git a/include/configs/ap143.h b/include/configs/ap143.h
index f907c02..e45f743 100644 (file)
--- a/include/configs/ap143.h
+++ b/include/configs/ap143.h
@@ -15,11 +15,6 @@
 #define CONFIG_SYS_MHZ                  325
 #define CONFIG_SYS_MIPS_TIMER_FREQ      (CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE          0x8000
-#define CONFIG_SYS_ICACHE_SIZE          0x10000
-#define CONFIG_SYS_CACHELINE_SIZE       32
-
 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN           0x40000

diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 68d9e36..68ff025 100644 (file)
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -202,11 +202,4 @@
 #define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
 #endif /* CONFIG_DBAU1550 */
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE         16384
-#define CONFIG_SYS_ICACHE_SIZE         16384
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 #endif /* __CONFIG_H */

diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index 869768a..b907419 100644 (file)
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -144,12 +144,6 @@
 #define CONFIG_SYS_ATA_ALT_OFFSET      0x0100
 
 #endif
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE         16384
-#define CONFIG_SYS_ICACHE_SIZE         16384
-#define CONFIG_SYS_CACHELINE_SIZE      32
 
 /*
  * BOOTP options

diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h
index 246ee01..f58fc4c 100644 (file)
--- a/include/configs/qemu-mips.h
+++ b/include/configs/qemu-mips.h
@@ -132,11 +132,4 @@
 
 #define CONFIG_LZMA
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE         16384
-#define CONFIG_SYS_ICACHE_SIZE         16384
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 #endif /* __CONFIG_H */

diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
index 60a3a71..2190d16 100644 (file)
--- a/include/configs/qemu-mips64.h
+++ b/include/configs/qemu-mips64.h
@@ -132,11 +132,4 @@
 
 #define CONFIG_LZMA
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE         16384
-#define CONFIG_SYS_ICACHE_SIZE         16384
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 #endif /* __CONFIG_H */

diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h
index 09a69fe..6273711 100644 (file)
--- a/include/configs/tplink_wdr4300.h
+++ b/include/configs/tplink_wdr4300.h
@@ -15,11 +15,6 @@
 #define CONFIG_SYS_MHZ                 280
 #define CONFIG_SYS_MIPS_TIMER_FREQ     (CONFIG_SYS_MHZ * 1000000)
 
-/* Cache Configuration */
-#define CONFIG_SYS_DCACHE_SIZE         0x8000
-#define CONFIG_SYS_ICACHE_SIZE         0x10000
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 #define CONFIG_SYS_MONITOR_BASE                CONFIG_SYS_TEXT_BASE
 
 #define CONFIG_SYS_MALLOC_LEN          0x40000

diff --git a/include/configs/vct.h b/include/configs/vct.h
index 68eb089..cc5e354 100644 (file)
--- a/include/configs/vct.h
+++ b/include/configs/vct.h
@@ -203,13 +203,6 @@
 #define        CONFIG_ENV_SIZE                 (128 << 10)     /* erase size */
 #endif /* CONFIG_VCT_ONENAND */
 
-/*
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE         16384
-#define CONFIG_SYS_ICACHE_SIZE         16384
-#define CONFIG_SYS_CACHELINE_SIZE      32
-
 /*
  * I2C/EEPROM
  */