Merge git://git.denx.de/u-boot-fsl-qoriq
authorTom Rini <trini@konsulko.com>
Tue, 25 Apr 2017 20:11:35 +0000 (16:11 -0400)
committerTom Rini <trini@konsulko.com>
Tue, 25 Apr 2017 20:11:35 +0000 (16:11 -0400)
24 files changed:
arch/arm/cpu/armv8/cpu-dt.c
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
arch/arm/cpu/armv8/fsl-layerscape/ppa.c
arch/arm/cpu/armv8/sec_firmware.c
arch/arm/include/asm/arch-fsl-layerscape/mp.h
arch/arm/include/asm/armv8/sec_firmware.h
board/freescale/ls1021atwr/ls1021atwr.c
board/freescale/ls1043aqds/ddr.c
board/freescale/ls1043aqds/ls1043aqds.c
board/freescale/ls1046aqds/ddr.c
board/freescale/ls1046aqds/ls1046aqds.c
board/freescale/ls1046ardb/ddr.c
board/freescale/ls2080ardb/eth_ls2080rdb.c
configs/ls1043aqds_defconfig
configs/ls1043aqds_lpuart_defconfig
configs/ls1043aqds_nand_defconfig
configs/ls1043aqds_nor_ddr3_defconfig
configs/ls1043aqds_qspi_defconfig
configs/ls1043aqds_sdcard_ifc_defconfig
configs/ls1043aqds_sdcard_qspi_defconfig
configs/ls1043ardb_nand_SECURE_BOOT_defconfig
configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig
configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig

index 5156a15..e3c8aa2 100644 (file)
@@ -7,25 +7,19 @@
 #include <common.h>
 #include <asm/psci.h>
 #include <asm/system.h>
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include <asm/armv8/sec_firmware.h>
-#endif
 
+#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 int psci_update_dt(void *fdt)
 {
-#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_PSCI) || defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
-
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
        /*
         * If the PSCI in SEC Firmware didn't work, avoid to update the
         * device node of PSCI. But still return 0 instead of an error
         * number to support detecting PSCI dynamically and then switching
         * the SMP boot method between PSCI and spin-table.
         */
-       if (sec_firmware_support_psci_version() == 0xffffffff)
+       if (sec_firmware_support_psci_version() == PSCI_INVALID_VER)
                return 0;
-#endif
        fdt_psci(fdt);
 
 #if defined(CONFIG_ARMV8_PSCI) && !defined(CONFIG_ARMV8_SECURE_BASE)
@@ -34,7 +28,6 @@ int psci_update_dt(void *fdt)
                        __secure_end - __secure_start);
 #endif
 
-#endif
-#endif
        return 0;
 }
+#endif
index 12fd80e..4c16c4c 100644 (file)
@@ -182,12 +182,22 @@ config SYS_LS_PPA_ESBC_ADDR
        default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
        default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
        default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
+       default 0x700000 if SYS_LS_PPA_FW_IN_MMC
+       default 0x700000 if SYS_LS_PPA_FW_IN_NAND
        help
          If the PPA header firmware locate at XIP flash, such as NOR or
          QSPI flash, this address is a directly memory-mapped.
          If it is in a serial accessed flash, such as NAND and SD
          card, it is a byte offset.
 
+config LS_PPA_ESBC_HDR_SIZE
+       hex "Length of PPA ESBC header"
+       depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
+       default 0x2000
+       help
+         Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
+         NAND to memory to validate PPA image.
+
 endmenu
 
 config SYS_FSL_ERRATUM_A010315
index c24f3f1..bb02960 100644 (file)
 #include <asm/arch/soc.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/speed.h>
-#ifdef CONFIG_MP
 #include <asm/arch/mp.h>
-#endif
 #include <efi_loader.h>
 #include <fm_eth.h>
 #include <fsl-mc/fsl_mc.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include <asm/armv8/sec_firmware.h>
-#endif
 #ifdef CONFIG_SYS_FSL_DDR
 #include <fsl_ddr.h>
 #endif
@@ -475,13 +471,19 @@ int cpu_eth_init(bd_t *bis)
        return error;
 }
 
-int arch_early_init_r(void)
+static inline int check_psci(void)
 {
-#ifdef CONFIG_MP
-       int rv = 1;
-       u32 psci_ver = 0xffffffff;
-#endif
+       unsigned int psci_ver;
 
+       psci_ver = sec_firmware_support_psci_version();
+       if (psci_ver == PSCI_INVALID_VER)
+               return 1;
+
+       return 0;
+}
+
+int arch_early_init_r(void)
+{
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
        u32 svr_dev_id;
        /*
@@ -495,18 +497,13 @@ int arch_early_init_r(void)
 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
        erratum_a009942_check_cpo();
 #endif
-#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
-       defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
-       /* Check the psci version to determine if the psci is supported */
-       psci_ver = sec_firmware_support_psci_version();
-#endif
-       if (psci_ver == 0xffffffff) {
-               rv = fsl_layerscape_wake_seconday_cores();
-               if (rv)
+       if (check_psci()) {
+               debug("PSCI: PSCI does not exist.\n");
+
+               /* if PSCI does not exist, boot secondary cores here */
+               if (fsl_layerscape_wake_seconday_cores())
                        printf("Did not wake secondary cores\n");
        }
-#endif
 
 #ifdef CONFIG_SYS_HAS_SERDES
        fsl_serdes_init();
index 7f87bb8..26c47a1 100644 (file)
@@ -37,13 +37,20 @@ int ppa_init(void)
        int ret;
 
 #ifdef CONFIG_CHAIN_OF_TRUST
-       uintptr_t ppa_esbc_hdr = CONFIG_SYS_LS_PPA_ESBC_ADDR;
+       uintptr_t ppa_esbc_hdr = 0;
        uintptr_t ppa_img_addr = 0;
+#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
+       defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
+       void *ppa_hdr_ddr;
+#endif
 #endif
 
 #ifdef CONFIG_SYS_LS_PPA_FW_IN_XIP
        ppa_fit_addr = (void *)CONFIG_SYS_LS_PPA_FW_ADDR;
        debug("%s: PPA image load from XIP\n", __func__);
+#ifdef CONFIG_CHAIN_OF_TRUST
+       ppa_esbc_hdr = CONFIG_SYS_LS_PPA_ESBC_ADDR;
+#endif
 #else /* !CONFIG_SYS_LS_PPA_FW_IN_XIP */
        size_t fw_length, fdt_header_len = sizeof(struct fdt_header);
 
@@ -53,7 +60,7 @@ int ppa_init(void)
        int dev = CONFIG_SYS_MMC_ENV_DEV;
        struct fdt_header *fitp;
        u32 cnt;
-       u32 blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512;
+       u32 blk;
 
        debug("%s: PPA image load from eMMC/SD\n", __func__);
 
@@ -81,6 +88,7 @@ int ppa_init(void)
                return -ENOMEM;
        }
 
+       blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512;
        cnt = DIV_ROUND_UP(fdt_header_len, 512);
        debug("%s: MMC read PPA FIT header: dev # %u, block # %u, count %u\n",
              __func__, dev, blk, cnt);
@@ -102,6 +110,29 @@ int ppa_init(void)
                return ret;
        }
 
+#ifdef CONFIG_CHAIN_OF_TRUST
+       ppa_hdr_ddr = malloc(CONFIG_LS_PPA_ESBC_HDR_SIZE);
+       if (!ppa_hdr_ddr) {
+               printf("PPA: malloc failed for PPA header\n");
+               return -ENOMEM;
+       }
+
+       blk = CONFIG_SYS_LS_PPA_ESBC_ADDR >> 9;
+       cnt = DIV_ROUND_UP(CONFIG_LS_PPA_ESBC_HDR_SIZE, 512);
+       ret = mmc->block_dev.block_read(&mmc->block_dev, blk, cnt, ppa_hdr_ddr);
+       if (ret != cnt) {
+               free(ppa_hdr_ddr);
+               printf("MMC/SD read of PPA header failed\n");
+               return -EIO;
+       }
+       debug("Read PPA header to 0x%p\n", ppa_hdr_ddr);
+
+       /* flush cache after read */
+       flush_cache((ulong)ppa_hdr_ddr, cnt * 512);
+
+       ppa_esbc_hdr = (uintptr_t)ppa_hdr_ddr;
+#endif
+
        fw_length = fdt_totalsize(fitp);
        free(fitp);
 
@@ -113,6 +144,7 @@ int ppa_init(void)
                return -ENOMEM;
        }
 
+       blk = CONFIG_SYS_LS_PPA_FW_ADDR / 512;
        cnt = DIV_ROUND_UP(fw_length, 512);
        debug("%s: MMC read PPA FIT image: dev # %u, block # %u, count %u\n",
              __func__, dev, blk, cnt);
@@ -148,6 +180,31 @@ int ppa_init(void)
                return ret;
        }
 
+#ifdef CONFIG_CHAIN_OF_TRUST
+       ppa_hdr_ddr = malloc(CONFIG_LS_PPA_ESBC_HDR_SIZE);
+       if (!ppa_hdr_ddr) {
+               printf("PPA: malloc failed for PPA header\n");
+               return -ENOMEM;
+       }
+
+       fw_length = CONFIG_LS_PPA_ESBC_HDR_SIZE;
+
+       ret = nand_read(nand_info[0], (loff_t)CONFIG_SYS_LS_PPA_ESBC_ADDR,
+                      &fw_length, (u_char *)ppa_hdr_ddr);
+       if (ret == -EUCLEAN) {
+               free(ppa_hdr_ddr);
+               printf("NAND read of PPA firmware at offset 0x%x failed\n",
+                      CONFIG_SYS_LS_PPA_FW_ADDR);
+               return -EIO;
+       }
+       debug("Read PPA header to 0x%p\n", ppa_hdr_ddr);
+
+       /* flush cache after read */
+       flush_cache((ulong)ppa_hdr_ddr, fw_length);
+
+       ppa_esbc_hdr = (uintptr_t)ppa_hdr_ddr;
+#endif
+
        fw_length = fdt_totalsize(&fit);
 
        ppa_fit_addr = malloc(fw_length);
@@ -177,6 +234,13 @@ int ppa_init(void)
 #ifdef CONFIG_CHAIN_OF_TRUST
        ppa_img_addr = (uintptr_t)ppa_fit_addr;
        if (fsl_check_boot_mode_secure() != 0) {
+               /*
+                * In case of failure in validation, fsl_secboot_validate
+                * would not return back in case of Production environment
+                * with ITS=1. In Development environment (ITS=0 and
+                * SB_EN=1), the function may return back in case of
+                * non-fatal failures.
+                */
                ret = fsl_secboot_validate(ppa_esbc_hdr,
                                           PPA_KEY_HASH,
                                           &ppa_img_addr);
@@ -185,6 +249,10 @@ int ppa_init(void)
                else
                        printf("PPA validation Successful\n");
        }
+#if defined(CONFIG_SYS_LS_PPA_FW_IN_MMC) || \
+       defined(CONFIG_SYS_LS_PPA_FW_IN_NAND)
+       free(ppa_hdr_ddr);
+#endif
 #endif
 
 #ifdef CONFIG_FSL_LSCH3
index ec9cf40..4afa3ad 100644 (file)
@@ -227,7 +227,7 @@ unsigned int sec_firmware_support_psci_version(void)
        if (sec_firmware_addr & SEC_FIRMWARE_RUNNING)
                return _sec_firmware_support_psci_version();
 
-       return 0xffffffff;
+       return PSCI_INVALID_VER;
 }
 #endif
 
index d0832b5..fd3f851 100644 (file)
@@ -31,7 +31,11 @@ extern u64 __spin_table[];
 extern u64 __real_cntfrq;
 extern u64 *secondary_boot_code;
 extern size_t __secondary_boot_code_size;
+#ifdef CONFIG_MP
 int fsl_layerscape_wake_seconday_cores(void);
+#else
+static inline int fsl_layerscape_wake_seconday_cores(void) { return 0; }
+#endif
 void *get_spin_tbl_addr(void);
 phys_addr_t determine_mp_bootpg(void);
 void secondary_boot_func(void);
index bcdb1b0..bc1d97d 100644 (file)
@@ -7,12 +7,19 @@
 #ifndef __SEC_FIRMWARE_H_
 #define __SEC_FIRMWARE_H_
 
+#define PSCI_INVALID_VER               0xffffffff
+
 int sec_firmware_init(const void *, u32 *, u32 *);
 int _sec_firmware_entry(const void *, u32 *, u32 *);
 bool sec_firmware_is_valid(const void *);
 #ifdef CONFIG_SEC_FIRMWARE_ARMV8_PSCI
 unsigned int sec_firmware_support_psci_version(void);
 unsigned int _sec_firmware_support_psci_version(void);
+#else
+static inline unsigned int sec_firmware_support_psci_version(void)
+{
+       return PSCI_INVALID_VER;
+}
 #endif
 
 #endif /* __SEC_FIRMWARE_H_ */
index d96fd77..ff32d5c 100644 (file)
@@ -273,6 +273,7 @@ int board_eth_init(bd_t *bis)
 #endif
 #ifdef CONFIG_TSEC3
        SET_STD_TSEC_INFO(tsec_info[num], 3);
+       tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
        num++;
 #endif
        if (!num) {
index 2643f5b..b22d378 100644 (file)
@@ -113,7 +113,9 @@ int fsl_initdram(void)
        phys_size_t dram_size;
 
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-       return fsl_ddr_sdram_size();
+       gd->ram_size = fsl_ddr_sdram_size();
+
+       return 0;
 #else
        puts("Initializing DDR....using SPD\n");
 
index 2df63e4..8fbd3a7 100644 (file)
@@ -11,6 +11,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ppa.h>
 #include <asm/arch/fdt.h>
 #include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
@@ -325,6 +326,10 @@ int board_init(void)
        config_serdes_mux();
 #endif
 
+#ifdef CONFIG_FSL_LS_PPA
+       ppa_init();
+#endif
+
        return 0;
 }
 
index d37af34..5fcfa0f 100644 (file)
@@ -97,7 +97,9 @@ int fsl_initdram(void)
        phys_size_t dram_size;
 
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-       return fsl_ddr_sdram_size();
+       gd->ram_size = fsl_ddr_sdram_size();
+
+       return 0;
 #else
        puts("Initializing DDR....using SPD\n");
 
index 58ce75a..057a11d 100644 (file)
@@ -11,6 +11,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/fsl_serdes.h>
+#include <asm/arch/ppa.h>
 #include <asm/arch/fdt.h>
 #include <asm/arch/mmu.h>
 #include <asm/arch/soc.h>
@@ -267,6 +268,10 @@ int board_init(void)
        if (adjust_vdd(0))
                printf("Warning: Adjusting core voltage failed.\n");
 
+#ifdef CONFIG_FSL_LS_PPA
+       ppa_init();
+#endif
+
 #ifdef CONFIG_SECURE_BOOT
        /*
         * In case of Secure Boot, the IBR configures the SMMU
index a16f7bc..ae5046c 100644 (file)
@@ -101,7 +101,9 @@ int fsl_initdram(void)
        phys_size_t dram_size;
 
 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
-       return fsl_ddr_sdram_size();
+       gd->ram_size = fsl_ddr_sdram_size();
+
+       return 0;
 #else
        puts("Initializing DDR....using SPD\n");
 
index 799799c..ba584c8 100644 (file)
@@ -61,6 +61,13 @@ int board_eth_init(bd_t *bis)
                wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
                wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
 
+               break;
+       case 0x4B:
+               wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
+               wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
+               wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
+               wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
+
                break;
        default:
                printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
index 838bf1d..cb137b2 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
index c3b3c80..0acaba1 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-lpuart"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
index 75150ed..d168e78 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_SERIAL_SUPPORT=y
index 8f99256..fd8d0f6 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
index 7b01ab8..4da173d 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds-duart"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
index acb811d..ba484e4 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_MMC_SUPPORT=y
index 78153ff..35688a4 100644 (file)
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1043AQDS=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_MMC_SUPPORT=y
index 66c89fa..70f28d8 100644 (file)
@@ -10,6 +10,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
 CONFIG_NAND_BOOT=y
index 3f35d64..5f9b21d 100644 (file)
@@ -10,6 +10,7 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_SECURE_BOOT=y
index a41ec80..1e32023 100644 (file)
@@ -3,6 +3,7 @@ CONFIG_TARGET_LS1046ARDB=y
 CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
+CONFIG_FSL_LS_PPA=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL"
 CONFIG_SECURE_BOOT=y