#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
-/*NO// #include <memtest.h> */
#include <i2c.h>
#include <spi.h>
#define ADC_INITIAL_DELAY (10 * ADC_VREF_CAP) /* 10 usec per uF, in usec */
#define ADC_SDATA_DELAY 100 /* ADC SDATA release delay in usec */
#define ADC_CAL_DELAY (1000000 / INITIAL_SAMPLE_RATE * 4500)
- /* Wait at least 4100 LRCLK's */
+ /* Wait at least 4100 LRCLK's */
#define ADC_REG1_FRAME_START 0x80 /* Frame start */
#define ADC_REG1_GROUND_CAL 0x40 /* Ground calibration enable */
else if(j == 4) cols = data & 0x0F;
else if(j == 12) {
/*
- * Refresh rate: this assumes the prescaler is set to
+ * Refresh rate: this assumes the prescaler is set to
* approximately 1uSec per tick.
*/
switch(data & 0x7F) {
- default:
- case 0: psrt = 14 ; /* 15.625uS */ break;
- case 1: psrt = 2; /* 3.9uS */ break;
- case 2: psrt = 6; /* 7.8uS */ break;
- case 3: psrt = 29; /* 31.3uS */ break;
- case 4: psrt = 60; /* 62.5uS */ break;
- case 5: psrt = 120; /* 125uS */ break;
+ default:
+ case 0: psrt = 14 ; /* 15.625uS */ break;
+ case 1: psrt = 2; /* 3.9uS */ break;
+ case 2: psrt = 6; /* 7.8uS */ break;
+ case 3: psrt = 29; /* 31.3uS */ break;
+ case 4: psrt = 60; /* 62.5uS */ break;
+ case 5: psrt = 120; /* 125uS */ break;
}
}
else if(j == 17) banks = data;
#endif
else {
printf ("WARNING: Unknown CAS latency 0x%02X, using 3\n",
- data);
+ data);
}
}
else if(j == 63) {
if(data != cksum) {
printf ("WARNING: Configuration data checksum failure:"
- " is 0x%02x, calculated 0x%02x\n",
+ " is 0x%02x, calculated 0x%02x\n",
data, cksum);
}
}
PSDMR_ACTTORW_8W |\
PSDMR_WRC_4C |\
PSDMR_EAMUX |\
- PSDMR_BUFCMD) |\
+ PSDMR_BUFCMD) |\
caslatency |\
((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
(sdam << 24) |\
PSDMR_ACTTORW_2W | /* 1 for 7E parts (fast PC-133) */ \
PSDMR_WRC_1C | /* 1 clock + 7nSec */
EAMUX |\
- BUFCMD) |\
+ BUFCMD) |\
caslatency |\
((caslatency - 1) << 6) | /* LDOTOPRE is CL - 1 */ \
(sdam << 24) |\
* two chip selects (double sided).
*/
if(chipselects > 1) {
- ramaddr += sdram_size;
+ ramaddr += sdram_size;
memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
memctl->memc_or3 = or;
sample_rate = INITIAL_SAMPLE_RATE;
if ((ep = getenv("DaqSampleRate")) != NULL) {
- sample_rate = simple_strtol(ep, NULL, 10);
+ sample_rate = simple_strtol(ep, NULL, 10);
}
sample_64x = INITIAL_SAMPLE_64X;
sample_128x = INITIAL_SAMPLE_128X;
if ((ep = getenv("Daq64xSampling")) != NULL) {
- sample_64x = simple_strtol(ep, NULL, 10);
+ sample_64x = simple_strtol(ep, NULL, 10);
if (sample_64x) {
sample_128x = 0;
}
}
}
else {
- if ((ep = getenv("Daq128xSampling")) != NULL) {
+ if ((ep = getenv("Daq128xSampling")) != NULL) {
sample_128x = simple_strtol(ep, NULL, 10);
if (sample_128x) {
- sample_64x = 0;
+ sample_64x = 0;
}
else {
- sample_64x = 1;
+ sample_64x = 1;
}
}
}
+ /*
+ * Stop the clocks and wait for at least 1 LRCLK period
+ * to make sure the clocking has really stopped.
+ */
+ Daq_Stop_Clocks();
+ udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
+
+ /*
+ * Initialize the clocks with the new rates
+ */
Daq_Init_Clocks(sample_rate, sample_64x);
sample_rate = Daq_Get_SampleRate();
+
+ /*
+ * Start the clocks and wait for at least 1 LRCLK period
+ * to make sure the clocking has become stable.
+ */
Daq_Start_Clocks(sample_rate);
+ udelay((1000000 / sample_rate) * NUM_LRCLKS_TO_STABILIZE);
sprintf(str_buf, "%d", sample_rate);
setenv("DaqSampleRate", str_buf);
if (sample_64x) {
- setenv("Daq64xSampling", "1");
- setenv("Daq128xSampling", NULL);
+ setenv("Daq64xSampling", "1");
+ setenv("Daq128xSampling", NULL);
}
else {
- setenv("Daq64xSampling", NULL);
- setenv("Daq128xSampling", "1");
+ setenv("Daq64xSampling", NULL);
+ setenv("Daq128xSampling", "1");
}
/* Display the ADC/DAC clocking information */
right_just = INITIAL_RIGHT_JUST;
if ((ep = getenv("DaqDACRightJustified")) != NULL) {
- right_just = simple_strtol(ep, NULL, 10);
+ right_just = simple_strtol(ep, NULL, 10);
}
sprintf(str_buf, "%d", right_just);
mclk_divide = INITIAL_MCLK_DIVIDE;
if ((ep = getenv("DaqDACMClockDivide")) != NULL) {
- mclk_divide = simple_strtol(ep, NULL, 10);
+ mclk_divide = simple_strtol(ep, NULL, 10);
}
sprintf(str_buf, "%d", mclk_divide);
*/
i2c_reg_write(I2C_DAC_ADDR, 0x01,
(right_just ? DAC_REG1_RIGHT_JUST_24BIT :
- DAC_REG1_LEFT_JUST_24_BIT) |
+ DAC_REG1_LEFT_JUST_24_BIT) |
DAC_REG1_DEM_NO |
(sample_rate >= 50000 ? DAC_REG1_DOUBLE : DAC_REG1_SINGLE));
* Recursively do upper digits.
*/
if(digits > 1) {
- flash_code(number / modulo, modulo, digits - 1);
+ flash_code(number / modulo, modulo, digits - 1);
}
number = number % modulo;
* Zero is indicated by one long flash (dash).
*/
if(number == 0) {
- status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
- udelay(1000000);
- status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
- udelay(200000);
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+ udelay(1000000);
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+ udelay(200000);
} else {
- /*
- * Non-zero is indicated by short flashes, one per count.
- */
- for(j = 0; j < number; j++) {
- status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
- udelay(100000);
- status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
- udelay(200000);
- }
+ /*
+ * Non-zero is indicated by short flashes, one per count.
+ */
+ for(j = 0; j < number; j++) {
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+ udelay(100000);
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
+ udelay(200000);
+ }
}
/*
* Inter-digit pause: we've already waited 200 mSec, wait 1 sec total
void show_boot_progress (int status)
{
if(status != -1) {
- last_boot_progress = status;
+ last_boot_progress = status;
} else {
- /*
- * Houston, we have a problem. Blink the last OK status which
- * indicates where things failed.
- */
- status_led_set(STATUS_LED_RED, STATUS_LED_ON);
- flash_code(last_boot_progress, 5, 3);
- udelay(1000000);
- status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING);
+ /*
+ * Houston, we have a problem. Blink the last OK status which
+ * indicates where things failed.
+ */
+ status_led_set(STATUS_LED_RED, STATUS_LED_ON);
+ flash_code(last_boot_progress, 5, 3);
+ udelay(1000000);
+ status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING);
}
}
#endif /* CONFIG_SHOW_BOOT_PROGRESS */
* chip selects: it calls the appropriate function to control the SPI
* chip selects.
*/
-spi_chipsel_type spi_chipsel[2] = {
+spi_chipsel_type spi_chipsel[] = {
spi_adc_chipsel,
spi_dac_chipsel
};
+int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
+
#endif /* CFG_CMD_SPI */
#endif /* CONFIG_MISC_INIT_R */
+
+#ifdef CONFIG_POST
+/*
+ * Returns 1 if keys pressed to start the power-on long-running tests
+ * Called from board_init_f().
+ */
+int post_hotkeys_pressed(void)
+{
+ return 0; /* No hotkeys supported */
+}
+
+#endif
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