14 { "MCBSPLP_DRR_REG", 0x00 },
15 { "MCBSPLP_DXR_REG", 0x08 },
16 { "MCBSPLP_SPCR2_REG", 0x10 },
17 { "MCBSPLP_SPCR1_REG", 0x14 },
18 { "MCBSPLP_RCR2_REG", 0x18 },
19 { "MCBSPLP_RCR1_REG", 0x1C },
20 { "MCBSPLP_XCR2_REG", 0x20 },
21 { "MCBSPLP_XCR1_REG", 0x24 },
22 { "MCBSPLP_SRGR2_REG", 0x28 },
23 { "MCBSPLP_SRGR1_REG", 0x2C },
24 { "MCBSPLP_MCR2_REG", 0x30 },
25 { "MCBSPLP_MCR1_REG", 0x34 },
26 { "MCBSPLP_RCERA_REG", 0x38 },
27 { "MCBSPLP_RCERB_REG", 0x3C },
28 { "MCBSPLP_XCERA_REG", 0x40 },
29 { "MCBSPLP_XCERB_REG", 0x44 },
30 { "MCBSPLP_PCR_REG", 0x48 },
31 { "MCBSPLP_RCERC_REG", 0x4C },
32 { "MCBSPLP_RCERD_REG", 0x50 },
33 { "MCBSPLP_XCERC_REG", 0x54 },
34 { "MCBSPLP_XCERD_REG", 0x58 },
35 { "MCBSPLP_RCERE_REG", 0x5C },
36 { "MCBSPLP_RCERF_REG", 0x60 },
37 { "MCBSPLP_XCERE_REG", 0x64 },
38 { "MCBSPLP_XCERF_REG", 0x68 },
39 { "MCBSPLP_RCERG_REG", 0x6C },
40 { "MCBSPLP_RCERH_REG", 0x70 },
41 { "MCBSPLP_XCERG_REG", 0x74 },
42 { "MCBSPLP_XCERH_REG", 0x78 },
43 { "MCBSPLP_RINTCLR_REG", 0x80 },
44 { "MCBSPLP_XINTCLR_REG", 0x84 },
45 { "MCBSPLP_ROVFLCLR_REG", 0x88 },
46 { "MCBSPLP_SYSCONFIG_REG", 0x8C },
47 { "MCBSPLP_THRSH2_REG", 0x90 },
48 { "MCBSPLP_THRSH1_REG", 0x94 },
49 { "MCBSPLP_IRQSTATUS_REG", 0xA0 },
50 { "MCBSPLP_IRQENABLE_REG", 0xA4 },
51 { "MCBSPLP_WAKEUPEN_REG", 0xA8 },
52 { "MCBSPLP_XCCR_REG", 0xAC },
53 { "MCBSPLP_RCCR_REG", 0xB0 },
54 { "MCBSPLP_XBUFFSTAT_REG", 0xB4 },
55 { "MCBSPLP_RBUFFSTAT_REG", 0xB8 },
56 { "MCBSPLP_SSELCR_REG", 0xBC },
57 { "MCBSPLP_STATUS_REG", 0xC0 },
61 void *checked_mmap(int memdev, unsigned int addr, unsigned int len)
63 void *regs = mmap(0, len, PROT_WRITE|PROT_READ, MAP_SHARED, memdev, addr);
64 if (regs == MAP_FAILED)
67 sprintf(err, "mmap 0x%08x", addr);
75 int main(int argc, char *argv[])
77 volatile unsigned int *regs;
80 memdev = open("/dev/mem", O_RDWR|O_SYNC);
83 printf("no memdev\n");
87 /* ----- clocks ----- */
89 regs = checked_mmap(memdev, 0x48000000, 0x10000);
91 printf("48002274 %08x CONTROL_DEVCONF0\n", regs[0x2274>>2]);
92 printf("480022D8 %08x CONTROL_DEVCONF1\n", regs[0x22D8>>2]);
93 printf("48004d40 %08x CM_CLKSEL1_PLL\n", regs[0x4d40>>2]);
94 printf("48005000 %08x CM_FCLKEN_PER\n", regs[0x5000>>2]);
95 printf("48005010 %08x CM_ICLKEN_PER\n", regs[0x5010>>2]);
96 printf("48005020 %08x CM_IDLEST_PER - idle status\n", regs[0x5020>>2]);
97 printf("48005030 %08x CM_AUTOIDLE_PER\n", regs[0x5030>>2]);
98 printf("480022A4 %08x CONTROL_MSUSPENDMUX_5x\n", regs[0x22a4>>2]);
99 printf("4800216c %08x PADCONF_MCBSP3_DX\n", regs[0x216c>>2]);
100 printf("48002170 %08x PADCONF_MCBSP3_CLKX\n", regs[0x2170>>2]);
102 munmap((void *)regs, 0x10000);
104 /* ----- PRCM ----- */
106 regs = checked_mmap(memdev, 0x48300000, 0x10000);
108 printf("483070a4 %08x PM_MPUGRPSEL_PER\n", regs[0x70a4>>2]);
109 printf("483070a8 %08x PM_IVA2GRPSEL_PER\n", regs[0x70a8>>2]);
110 printf("483070b0 %08x PM_WKST_PER\n", regs[0x70b0>>2]);
112 munmap((void *)regs, 0x10000);
114 /* ----- SSELCR ----- */
116 regs = checked_mmap(memdev, 0x49020000, 0x10000);
118 printf("4902a02c %08x ST_SSELCR_REG\n", regs[0xa02c>>2]);
120 munmap((void *)regs, 0x10000);
122 /* ----- IRQs ----- */
124 regs = checked_mmap(memdev, 0x48200000, 0x10000);
126 // 22 ~ MCBSP3_IRQ, 89 ~ MCBSP3_IRQ_TX, 90 ~ MCBSP3_IRQ_RX
127 printf("IRQs: %i, TX %i, RX %i\n", !(regs[0x0084>>2] & (1<<22)),
128 !(regs[0x008c>>2] & (1<<(89-64))), !(regs[0x008c>>2] & (1<<(90-64))));
130 munmap((void *)regs, 0x10000);
132 /* ----- McBSP ----- */
134 regs = checked_mmap(memdev, 0x49024000, 0x2000);
137 for (i = 0; i < 0xC4; i+= 4)
139 printf("%02x %8x ", i, regs[i>>2]);
140 for (u = 0; u < sizeof(noffs) / sizeof(noffs[0]); u++)
142 if (i == noffs[u].offset) {
143 printf("%s", noffs[u].name);
150 munmap((void *)regs, 0x2000);