--- /dev/null
+* ARM architected timer
+
+ARM Cortex-A7 and Cortex-A15 have a per-core architected timer, which
+provides per-cpu timers.
+
+The timer is attached to a GIC to deliver its per-processor interrupts.
+
+** Timer node properties:
+
+- compatible : Should at least contain "arm,armv7-timer".
+
+- interrupts : Interrupt list for secure, non-secure, virtual and
+ hypervisor timers, in that order.
+
+- clock-frequency : The frequency of the main counter, in Hz. Optional.
+
+Example:
+
+ timer {
+ compatible = "arm,cortex-a15-timer",
+ "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ clock-frequency = <100000000>;
+ };
select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
select HAVE_ARCH_KGDB
+ select HAVE_ARCH_TRACEHOOK
select HAVE_KPROBES if !XIP_KERNEL
select HAVE_KRETPROBES if (HAVE_KPROBES)
select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
select HAVE_C_RECORDMCOUNT
select HAVE_GENERIC_HARDIRQS
+ select HARDIRQS_SW_RESEND
+ select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW
select CPU_PM if (SUSPEND || CPU_IDLE)
select GENERIC_PCI_IOMAP
bool
default y
-config HARDIRQS_SW_RESEND
- bool
- default y
-
-config GENERIC_IRQ_PROBE
- bool
- default y
-
config GENERIC_LOCKBREAK
bool
default y
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
select SPARSE_IRQ
+ select MULTI_IRQ_HANDLER
help
Support for ARM's Integrator platform.
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select GPIO_PXA
- select TICK_ONESHOT
select PLAT_PXA
select SPARSE_IRQ
select GENERIC_ALLOCATOR
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select GPIO_PXA
- select TICK_ONESHOT
select PLAT_PXA
select SPARSE_IRQ
select AUTO_ZRELADDR
select CPU_FREQ
select GENERIC_CLOCKEVENTS
select CLKDEV_LOOKUP
- select TICK_ONESHOT
select ARCH_REQUIRE_GPIOLIB
select HAVE_IDE
select NEED_MACH_MEMORY_H
help
This option enables support for the ARM system coherency unit
+config ARM_ARCH_TIMER
+ bool "Architected timer support"
+ depends on CPU_V7
+ help
+ This option enables support for the ARM architected timer
+
config HAVE_ARM_TWD
bool
depends on SMP
- select TICK_ONESHOT
help
This options enables support for the ARM timer and watchdog unit
arch-$(CONFIG_CPU_32v3) :=-D__LINUX_ARM_ARCH__=3 -march=armv3
# This selects how we optimise for the processor.
-tune-$(CONFIG_CPU_ARM610) :=-mtune=arm610
-tune-$(CONFIG_CPU_ARM710) :=-mtune=arm710
tune-$(CONFIG_CPU_ARM7TDMI) :=-mtune=arm7tdmi
tune-$(CONFIG_CPU_ARM720T) :=-mtune=arm7tdmi
tune-$(CONFIG_CPU_ARM740T) :=-mtune=arm7tdmi
mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
mov pc, lr
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+#define CB_BITS 0x08
+#else
+#define CB_BITS 0x0c
+#endif
+
__setup_mmu: sub r3, r4, #16384 @ Page directory size
bic r3, r3, #0xff @ Align the pointer
bic r3, r3, #0x3f00
mov r9, r0, lsr #18
mov r9, r9, lsl #18 @ start of RAM
add r10, r9, #0x10000000 @ a reasonable RAM size
- mov r1, #0x12
- orr r1, r1, #3 << 10
+ mov r1, #0x12 @ XN|U + section mapping
+ orr r1, r1, #3 << 10 @ AP=11
add r2, r3, #16384
1: cmp r1, r9 @ if virt > start of RAM
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
- orrhs r1, r1, #0x08 @ set cacheable
-#else
- orrhs r1, r1, #0x0c @ set cacheable, bufferable
-#endif
- cmp r1, r10 @ if virt > end of RAM
- bichs r1, r1, #0x0c @ clear cacheable, bufferable
+ cmphs r10, r1 @ && end of RAM > virt
+ bic r1, r1, #0x1c @ clear XN|U + C + B
+ orrlo r1, r1, #0x10 @ Set XN|U for non-RAM
+ orrhs r1, r1, r6 @ set RAM section settings
str r1, [r0], #4 @ 1:1 mapping
add r1, r1, #1048576
teq r0, r2
* so there is no map overlap problem for up to 1 MB compressed kernel.
* If the execution is in RAM then we would only be duplicating the above.
*/
- mov r1, #0x1e
+ orr r1, r6, #0x04 @ ensure B is set for this
orr r1, r1, #3 << 10
mov r2, pc
mov r2, r2, lsr #20
__armv4_mmu_cache_on:
mov r12, lr
#ifdef CONFIG_MMU
+ mov r6, #CB_BITS | 0x12 @ U
bl __setup_mmu
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
#ifdef CONFIG_MMU
mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
tst r11, #0xf @ VMSA
+ movne r6, #CB_BITS | 0x02 @ !XN
blne __setup_mmu
mov r0, #0
mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
orr r0, r0, #1 << 25 @ big-endian page tables
#endif
orrne r0, r0, #1 @ MMU enabled
- movne r1, #-1
+ movne r1, #0xfffffffd @ domain 0 = client
mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
#endif
__fa526_cache_on:
mov r12, lr
+ mov r6, #CB_BITS | 0x12 @ U
bl __setup_mmu
mov r0, #0
mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
mov pc, r12
-__arm6_mmu_cache_on:
- mov r12, lr
- bl __setup_mmu
- mov r0, #0
- mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
- mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
- mov r0, #0x30
- bl __common_mmu_cache_on
- mov r0, #0
- mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
- mov pc, r12
-
__common_mmu_cache_on:
#ifndef CONFIG_THUMB2_KERNEL
#ifndef DEBUG
.align 2
.type proc_types,#object
proc_types:
- .word 0x41560600 @ ARM6/610
- .word 0xffffffe0
- W(b) __arm6_mmu_cache_off @ works, but slow
- W(b) __arm6_mmu_cache_off
- mov pc, lr
- THUMB( nop )
-@ b __arm6_mmu_cache_on @ untested
-@ b __arm6_mmu_cache_off
-@ b __armv3_mmu_cache_flush
-
.word 0x00000000 @ old ARM ID
.word 0x0000f000
mov pc, lr
.word 0x41007000 @ ARM7/710
.word 0xfff8fe00
- W(b) __arm7_mmu_cache_off
- W(b) __arm7_mmu_cache_off
+ mov pc, lr
+ THUMB( nop )
+ mov pc, lr
+ THUMB( nop )
mov pc, lr
THUMB( nop )
mcr p15, 0, r0, c7, c5, 4 @ ISB
mov pc, r12
-__arm6_mmu_cache_off:
- mov r0, #0x00000030 @ ARM6 control reg.
- b __armv3_mmu_cache_off
-
-__arm7_mmu_cache_off:
- mov r0, #0x00000070 @ ARM7 control reg.
- b __armv3_mmu_cache_off
-
-__armv3_mmu_cache_off:
- mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
- mov r0, #0
- mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
- mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
- mov pc, lr
-
/*
* Clean and flush the cache to maintain consistency.
*
return PCIBIOS_SUCCESSFUL;
}
-static struct pci_ops it8152_ops = {
+struct pci_ops it8152_ops = {
.read = it8152_pci_read_config,
.write = it8152_pci_write_config,
};
}
-struct pci_bus * __init it8152_pci_scan_bus(int nr, struct pci_sys_data *sys)
-{
- return pci_scan_root_bus(NULL, nr, &it8152_ops, sys, &sys->resources);
-}
-
EXPORT_SYMBOL(dma_set_coherent_mask);
return PCIBIOS_SUCCESSFUL;
}
-static struct pci_ops via82c505_ops = {
+struct pci_ops via82c505_ops = {
.read = via82c505_read_config,
.write = via82c505_write_config,
};
{
return (nr == 0);
}
-
-struct pci_bus * __init via82c505_scan_bus(int nr, struct pci_sys_data *sysdata)
-{
- if (nr == 0)
- return pci_scan_root_bus(NULL, 0, &via82c505_ops, sysdata,
- &sysdata->resources);
-
- return NULL;
-}
* struct vic_device - VIC PM device
* @irq: The IRQ number for the base of the VIC.
* @base: The register base for the VIC.
+ * @valid_sources: A bitmask of valid interrupts
* @resume_sources: A bitmask of interrupts for resume.
* @resume_irqs: The IRQs enabled for resume.
* @int_select: Save for VIC_INT_SELECT.
struct vic_device {
void __iomem *base;
int irq;
+ u32 valid_sources;
u32 resume_sources;
u32 resume_irqs;
u32 int_select;
late_initcall(vic_pm_init);
#endif /* CONFIG_PM */
+static struct irq_chip vic_chip;
+
+static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ struct vic_device *v = d->host_data;
+
+ /* Skip invalid IRQs, only register handlers for the real ones */
+ if (!(v->valid_sources & (1 << hwirq)))
+ return -ENOTSUPP;
+ irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
+ irq_set_chip_data(irq, v->base);
+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+ return 0;
+}
+
+static struct irq_domain_ops vic_irqdomain_ops = {
+ .map = vic_irqdomain_map,
+ .xlate = irq_domain_xlate_onetwocell,
+};
+
/**
* vic_register() - Register a VIC.
* @base: The base address of the VIC.
* @irq: The base IRQ for the VIC.
+ * @valid_sources: bitmask of valid interrupts
* @resume_sources: bitmask of interrupts allowed for resume sources.
* @node: The device tree node associated with the VIC.
*
* This also configures the IRQ domain for the VIC.
*/
static void __init vic_register(void __iomem *base, unsigned int irq,
- u32 resume_sources, struct device_node *node)
+ u32 valid_sources, u32 resume_sources,
+ struct device_node *node)
{
struct vic_device *v;
v = &vic_devices[vic_id];
v->base = base;
+ v->valid_sources = valid_sources;
v->resume_sources = resume_sources;
v->irq = irq;
vic_id++;
- v->domain = irq_domain_add_legacy(node, 32, irq, 0,
- &irq_domain_simple_ops, v);
+ v->domain = irq_domain_add_legacy(node, fls(valid_sources), irq, 0,
+ &vic_irqdomain_ops, v);
}
static void vic_ack_irq(struct irq_data *d)
}
}
-static void __init vic_set_irq_sources(void __iomem *base,
- unsigned int irq_start, u32 vic_sources)
-{
- unsigned int i;
-
- for (i = 0; i < 32; i++) {
- if (vic_sources & (1 << i)) {
- unsigned int irq = irq_start + i;
-
- irq_set_chip_and_handler(irq, &vic_chip,
- handle_level_irq);
- irq_set_chip_data(irq, base);
- set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
- }
- }
-}
-
/*
* The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
* The original cell has 32 interrupts, while the modified one has 64,
writel(32, base + VIC_PL190_DEF_VECT_ADDR);
}
- vic_set_irq_sources(base, irq_start, vic_sources);
- vic_register(base, irq_start, 0, node);
+ vic_register(base, irq_start, vic_sources, 0, node);
}
void __init __vic_init(void __iomem *base, unsigned int irq_start,
vic_init2(base);
- vic_set_irq_sources(base, irq_start, vic_sources);
-
- vic_register(base, irq_start, resume_sources, node);
+ vic_register(base, irq_start, vic_sources, resume_sources, node);
}
/**
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_RPC=y
-CONFIG_CPU_ARM610=y
-CONFIG_CPU_ARM710=y
CONFIG_CPU_SA110=y
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
--- /dev/null
+#ifndef __ASMARM_ARCH_TIMER_H
+#define __ASMARM_ARCH_TIMER_H
+
+#ifdef CONFIG_ARM_ARCH_TIMER
+int arch_timer_of_register(void);
+int arch_timer_sched_clock_init(void);
+#else
+static inline int arch_timer_of_register(void)
+{
+ return -ENXIO;
+}
+
+static inline int arch_timer_sched_clock_init(void)
+{
+ return -ENXIO;
+}
+#endif
+
+#endif
void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
void (*coherent_kern_range)(unsigned long, unsigned long);
- void (*coherent_user_range)(unsigned long, unsigned long);
+ int (*coherent_user_range)(unsigned long, unsigned long);
void (*flush_kern_dcache_area)(void *, size_t);
void (*dma_map_area)(const void *, size_t, int);
extern void __cpuc_flush_user_all(void);
extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
-extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
+extern int __cpuc_coherent_user_range(unsigned long, unsigned long);
extern void __cpuc_flush_dcache_area(void *, size_t);
/*
* Harvard caches are synchronised for the user space address range.
* This is used for the ARM private sys_cacheflush system call.
*/
-#define flush_cache_user_range(vma,start,end) \
+#define flush_cache_user_range(start,end) \
__cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
/*
(unsigned long)(n), \
sizeof(*(ptr))))
-#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */
-
-/*
- * Note : ARMv7-M (currently unsupported by Linux) does not support
- * ldrexd/strexd. If ARMv7-M is ever supported by the Linux kernel, it should
- * not be allowed to use __cmpxchg64.
- */
-static inline unsigned long long __cmpxchg64(volatile void *ptr,
- unsigned long long old,
- unsigned long long new)
-{
- register unsigned long long oldval asm("r0");
- register unsigned long long __old asm("r2") = old;
- register unsigned long long __new asm("r4") = new;
- unsigned long res;
-
- do {
- asm volatile(
- " @ __cmpxchg8\n"
- " ldrexd %1, %H1, [%2]\n"
- " mov %0, #0\n"
- " teq %1, %3\n"
- " teqeq %H1, %H3\n"
- " strexdeq %0, %4, %H4, [%2]\n"
- : "=&r" (res), "=&r" (oldval)
- : "r" (ptr), "Ir" (__old), "r" (__new)
- : "memory", "cc");
- } while (res);
-
- return oldval;
-}
-
-static inline unsigned long long __cmpxchg64_mb(volatile void *ptr,
- unsigned long long old,
- unsigned long long new)
-{
- unsigned long long ret;
-
- smp_mb();
- ret = __cmpxchg64(ptr, old, new);
- smp_mb();
-
- return ret;
-}
-
-#define cmpxchg64(ptr,o,n) \
- ((__typeof__(*(ptr)))__cmpxchg64_mb((ptr), \
- (unsigned long long)(o), \
- (unsigned long long)(n)))
-
-#define cmpxchg64_local(ptr,o,n) \
- ((__typeof__(*(ptr)))__cmpxchg64((ptr), \
- (unsigned long long)(o), \
- (unsigned long long)(n)))
-
-#else /* min ARCH = ARMv6 */
-
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#endif
+#define cmpxchg64(ptr, o, n) \
+ ((__typeof__(*(ptr)))atomic64_cmpxchg(container_of((ptr), \
+ atomic64_t, \
+ counter), \
+ (unsigned long)(o), \
+ (unsigned long)(n)))
+
+#define cmpxchg64_local(ptr, o, n) \
+ ((__typeof__(*(ptr)))local64_cmpxchg(container_of((ptr), \
+ local64_t, \
+ a), \
+ (unsigned long)(o), \
+ (unsigned long)(n)))
#endif /* __LINUX_ARM_ARCH__ >= 6 */
#undef CPU_DABORT_HANDLER
#undef MULTI_DABORT
-#if defined(CONFIG_CPU_ARM610)
-# ifdef CPU_DABORT_HANDLER
-# define MULTI_DABORT 1
-# else
-# define CPU_DABORT_HANDLER cpu_arm6_data_abort
-# endif
-#endif
-
#if defined(CONFIG_CPU_ARM710)
# ifdef CPU_DABORT_HANDLER
# define MULTI_DABORT 1
* CPU_NAME - the prefix for CPU related functions
*/
-#ifdef CONFIG_CPU_ARM610
-# ifdef CPU_NAME
-# undef MULTI_CPU
-# define MULTI_CPU
-# else
-# define CPU_NAME cpu_arm6
-# endif
-#endif
-
#ifdef CONFIG_CPU_ARM7TDMI
# ifdef CPU_NAME
# undef MULTI_CPU
# endif
#endif
-#ifdef CONFIG_CPU_ARM710
-# ifdef CPU_NAME
-# undef MULTI_CPU
-# define MULTI_CPU
-# else
-# define CPU_NAME cpu_arm7
-# endif
-#endif
-
#ifdef CONFIG_CPU_ARM720T
# ifdef CPU_NAME
# undef MULTI_CPU
extern void it8152_init_irq(void);
extern int it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
-extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys);
+extern struct pci_ops it8152_ops;
#endif /* __ASM_HARDWARE_IT8152_H */
#define __ASM_MACH_PCI_H
struct pci_sys_data;
+struct pci_ops;
struct pci_bus;
struct hw_pci {
#ifdef CONFIG_PCI_DOMAINS
int domain;
#endif
- struct list_head buses;
+ struct pci_ops *ops;
int nr_controllers;
int (*setup)(int nr, struct pci_sys_data *);
struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
u8 (*swizzle)(struct pci_dev *, u8 *);
/* IRQ mapping */
int (*map_irq)(const struct pci_dev *, u8, u8);
- struct hw_pci *hw;
void *private_data; /* platform controller private data */
};
-/*
- * This is the standard PCI-PCI bridge swizzling algorithm.
- */
-#define pci_std_swizzle pci_common_swizzle
-
/*
* Call this with your hw_pci struct to initialise the PCI system.
*/
/*
* PCI controllers
*/
+extern struct pci_ops iop3xx_ops;
extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
extern void iop3xx_pci_preinit(void);
extern void iop3xx_pci_preinit_cond(void);
+extern struct pci_ops dc21285_ops;
extern int dc21285_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
extern void dc21285_preinit(void);
extern void dc21285_postinit(void);
+extern struct pci_ops via82c505_ops;
extern int via82c505_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *via82c505_scan_bus(int nr, struct pci_sys_data *);
extern void via82c505_init(void *sysdata);
+extern struct pci_ops pci_v3_ops;
extern int pci_v3_setup(int nr, struct pci_sys_data *);
-extern struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *);
extern void pci_v3_preinit(void);
extern void pci_v3_postinit(void);
extern void timer_tick(void);
+struct timespec;
+typedef void (*clock_access_fn)(struct timespec *);
+extern int register_persistent_clock(clock_access_fn read_boot,
+ clock_access_fn read_persistent);
+
#endif
#endif
-/*
- * switch_mm() may do a full cache flush over the context switch,
- * so enable interrupts over the context switch to avoid high
- * latency.
- */
-#define __ARCH_WANT_INTERRUPTS_ON_CTXSW
-
#endif
#define ASID_FIRST_VERSION (1 << ASID_BITS)
extern unsigned int cpu_last_asid;
-#ifdef CONFIG_SMP
-DECLARE_PER_CPU(struct mm_struct *, current_mm);
-#endif
void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
void __new_context(struct mm_struct *mm);
+void cpu_set_reserved_ttbr0(void);
-static inline void check_context(struct mm_struct *mm)
+static inline void switch_new_context(struct mm_struct *mm)
{
- /*
- * This code is executed with interrupts enabled. Therefore,
- * mm->context.id cannot be updated to the latest ASID version
- * on a different CPU (and condition below not triggered)
- * without first getting an IPI to reset the context. The
- * alternative is to take a read_lock on mm->context.id_lock
- * (after changing its type to rwlock_t).
- */
- if (unlikely((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
- __new_context(mm);
+ unsigned long flags;
+
+ __new_context(mm);
+
+ local_irq_save(flags);
+ cpu_switch_mm(mm->pgd, mm);
+ local_irq_restore(flags);
+}
+static inline void check_and_switch_context(struct mm_struct *mm,
+ struct task_struct *tsk)
+{
if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
__check_kvm_seq(mm);
+
+ /*
+ * Required during context switch to avoid speculative page table
+ * walking with the wrong TTBR.
+ */
+ cpu_set_reserved_ttbr0();
+
+ if (!((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
+ /*
+ * The ASID is from the current generation, just switch to the
+ * new pgd. This condition is only true for calls from
+ * context_switch() and interrupts are already disabled.
+ */
+ cpu_switch_mm(mm->pgd, mm);
+ else if (irqs_disabled())
+ /*
+ * Defer the new ASID allocation until after the context
+ * switch critical region since __new_context() cannot be
+ * called with interrupts disabled (it sends IPIs).
+ */
+ set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
+ else
+ /*
+ * That is a direct call to switch_mm() or activate_mm() with
+ * interrupts enabled and a new context.
+ */
+ switch_new_context(mm);
}
#define init_new_context(tsk,mm) (__init_new_context(tsk,mm),0)
-#else
-
-static inline void check_context(struct mm_struct *mm)
+#define finish_arch_post_lock_switch \
+ finish_arch_post_lock_switch
+static inline void finish_arch_post_lock_switch(void)
{
+ if (test_and_clear_thread_flag(TIF_SWITCH_MM))
+ switch_new_context(current->mm);
+}
+
+#else /* !CONFIG_CPU_HAS_ASID */
+
#ifdef CONFIG_MMU
+
+static inline void check_and_switch_context(struct mm_struct *mm,
+ struct task_struct *tsk)
+{
if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
__check_kvm_seq(mm);
-#endif
+
+ if (irqs_disabled())
+ /*
+ * cpu_switch_mm() needs to flush the VIVT caches. To avoid
+ * high interrupt latencies, defer the call and continue
+ * running with the old mm. Since we only support UP systems
+ * on non-ASID CPUs, the old mm will remain valid until the
+ * finish_arch_post_lock_switch() call.
+ */
+ set_ti_thread_flag(task_thread_info(tsk), TIF_SWITCH_MM);
+ else
+ cpu_switch_mm(mm->pgd, mm);
}
+#define finish_arch_post_lock_switch \
+ finish_arch_post_lock_switch
+static inline void finish_arch_post_lock_switch(void)
+{
+ if (test_and_clear_thread_flag(TIF_SWITCH_MM)) {
+ struct mm_struct *mm = current->mm;
+ cpu_switch_mm(mm->pgd, mm);
+ }
+}
+
+#endif /* CONFIG_MMU */
+
#define init_new_context(tsk,mm) 0
-#endif
+#endif /* CONFIG_CPU_HAS_ASID */
#define destroy_context(mm) do { } while(0)
__flush_icache_all();
#endif
if (!cpumask_test_and_set_cpu(cpu, mm_cpumask(next)) || prev != next) {
-#ifdef CONFIG_SMP
- struct mm_struct **crt_mm = &per_cpu(current_mm, cpu);
- *crt_mm = next;
-#endif
- check_context(next);
- cpu_switch_mm(next->pgd, next);
+ check_and_switch_context(next, tsk);
if (cache_is_vivt())
cpumask_clear_cpu(cpu, mm_cpumask(prev));
}
* processor(s) we're building for.
*
* We have the following to choose from:
- * v3 - ARMv3
* v4wt - ARMv4 with writethrough cache, without minicache
* v4wb - ARMv4 with writeback cache, without minicache
* v4_mc - ARMv4 with minicache
#undef _USER
#undef MULTI_USER
-#ifdef CONFIG_CPU_COPY_V3
-# ifdef _USER
-# define MULTI_USER 1
-# else
-# define _USER v3
-# endif
-#endif
-
#ifdef CONFIG_CPU_COPY_V4WT
# ifdef _USER
# define MULTI_USER 1
*/
#define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Valid */
#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */
-#define L_PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) /* AttrIndx[0] */
-#define L_PTE_CACHEABLE (_AT(pteval_t, 1) << 3) /* AttrIndx[1] */
#define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
#define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
return regs->ARM_sp;
}
+static inline unsigned long user_stack_pointer(struct pt_regs *regs)
+{
+ return regs->ARM_sp;
+}
+
#endif /* __KERNEL__ */
#endif /* __ASSEMBLY__ */
--- /dev/null
+/*
+ * Access to user system call parameters and results
+ *
+ * See asm-generic/syscall.h for descriptions of what we must do here.
+ */
+
+#ifndef _ASM_ARM_SYSCALL_H
+#define _ASM_ARM_SYSCALL_H
+
+#include <linux/err.h>
+
+extern const unsigned long sys_call_table[];
+
+static inline int syscall_get_nr(struct task_struct *task,
+ struct pt_regs *regs)
+{
+ return task_thread_info(task)->syscall;
+}
+
+static inline void syscall_rollback(struct task_struct *task,
+ struct pt_regs *regs)
+{
+ regs->ARM_r0 = regs->ARM_ORIG_r0;
+}
+
+static inline long syscall_get_error(struct task_struct *task,
+ struct pt_regs *regs)
+{
+ unsigned long error = regs->ARM_r0;
+ return IS_ERR_VALUE(error) ? error : 0;
+}
+
+static inline long syscall_get_return_value(struct task_struct *task,
+ struct pt_regs *regs)
+{
+ return regs->ARM_r0;
+}
+
+static inline void syscall_set_return_value(struct task_struct *task,
+ struct pt_regs *regs,
+ int error, long val)
+{
+ regs->ARM_r0 = (long) error ? error : val;
+}
+
+#define SYSCALL_MAX_ARGS 7
+
+static inline void syscall_get_arguments(struct task_struct *task,
+ struct pt_regs *regs,
+ unsigned int i, unsigned int n,
+ unsigned long *args)
+{
+ if (i + n > SYSCALL_MAX_ARGS) {
+ unsigned long *args_bad = args + SYSCALL_MAX_ARGS - i;
+ unsigned int n_bad = n + i - SYSCALL_MAX_ARGS;
+ pr_warning("%s called with max args %d, handling only %d\n",
+ __func__, i + n, SYSCALL_MAX_ARGS);
+ memset(args_bad, 0, n_bad * sizeof(args[0]));
+ n = SYSCALL_MAX_ARGS - i;
+ }
+
+ if (i == 0) {
+ args[0] = regs->ARM_ORIG_r0;
+ args++;
+ i++;
+ n--;
+ }
+
+ memcpy(args, ®s->ARM_r0 + i, n * sizeof(args[0]));
+}
+
+static inline void syscall_set_arguments(struct task_struct *task,
+ struct pt_regs *regs,
+ unsigned int i, unsigned int n,
+ const unsigned long *args)
+{
+ if (i + n > SYSCALL_MAX_ARGS) {
+ pr_warning("%s called with max args %d, handling only %d\n",
+ __func__, i + n, SYSCALL_MAX_ARGS);
+ n = SYSCALL_MAX_ARGS - i;
+ }
+
+ if (i == 0) {
+ regs->ARM_ORIG_r0 = args[0];
+ args++;
+ i++;
+ n--;
+ }
+
+ memcpy(®s->ARM_r0 + i, args, n * sizeof(args[0]));
+}
+
+#endif /* _ASM_ARM_SYSCALL_H */
#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
#define TIF_RESTORE_SIGMASK 20
#define TIF_SECCOMP 21
+#define TIF_SWITCH_MM 22 /* deferred switch_mm */
#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
#define MULTI_TLB 1
#endif
-#define v3_tlb_flags (TLB_V3_FULL | TLB_V3_PAGE)
-
-#ifdef CONFIG_CPU_TLB_V3
-# define v3_possible_flags v3_tlb_flags
-# define v3_always_flags v3_tlb_flags
-# ifdef _TLB
-# define MULTI_TLB 1
-# else
-# define _TLB v3
-# endif
-#else
-# define v3_possible_flags 0
-# define v3_always_flags (-1UL)
-#endif
-
#define v4_tlb_flags (TLB_V4_U_FULL | TLB_V4_U_PAGE)
#ifdef CONFIG_CPU_TLB_V4WT
* implemented the "%?" method, but this has been discontinued due to too
* many people getting it wrong.
*/
-#define possible_tlb_flags (v3_possible_flags | \
- v4_possible_flags | \
+#define possible_tlb_flags (v4_possible_flags | \
v4wbi_possible_flags | \
fr_possible_flags | \
v4wb_possible_flags | \
v6wbi_possible_flags | \
v7wbi_possible_flags)
-#define always_tlb_flags (v3_always_flags & \
- v4_always_flags & \
+#define always_tlb_flags (v4_always_flags & \
v4wbi_always_flags & \
fr_always_flags & \
v4wb_always_flags & \
obj-$(CONFIG_SMP) += smp.o smp_tlb.o
obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o
obj-$(CONFIG_HAVE_ARM_TWD) += smp_twd.o
+obj-$(CONFIG_ARM_ARCH_TIMER) += arch_timer.o
obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o insn.o
obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o insn.o
obj-$(CONFIG_JUMP_LABEL) += jump_label.o insn.o patch.o
--- /dev/null
+/*
+ * linux/arch/arm/kernel/arch_timer.c
+ *
+ * Copyright (C) 2011 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/cpu.h>
+#include <linux/jiffies.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+
+#include <asm/cputype.h>
+#include <asm/localtimer.h>
+#include <asm/arch_timer.h>
+#include <asm/system_info.h>
+#include <asm/sched_clock.h>
+
+static unsigned long arch_timer_rate;
+static int arch_timer_ppi;
+static int arch_timer_ppi2;
+
+static struct clock_event_device __percpu **arch_timer_evt;
+
+/*
+ * Architected system timer support.
+ */
+
+#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
+#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
+#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
+
+#define ARCH_TIMER_REG_CTRL 0
+#define ARCH_TIMER_REG_FREQ 1
+#define ARCH_TIMER_REG_TVAL 2
+
+static void arch_timer_reg_write(int reg, u32 val)
+{
+ switch (reg) {
+ case ARCH_TIMER_REG_CTRL:
+ asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+ break;
+ case ARCH_TIMER_REG_TVAL:
+ asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
+ break;
+ }
+
+ isb();
+}
+
+static u32 arch_timer_reg_read(int reg)
+{
+ u32 val;
+
+ switch (reg) {
+ case ARCH_TIMER_REG_CTRL:
+ asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+ break;
+ case ARCH_TIMER_REG_FREQ:
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
+ break;
+ case ARCH_TIMER_REG_TVAL:
+ asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
+ break;
+ default:
+ BUG();
+ }
+
+ return val;
+}
+
+static irqreturn_t arch_timer_handler(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+ unsigned long ctrl;
+
+ ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+ if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
+ ctrl |= ARCH_TIMER_CTRL_IT_MASK;
+ arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+ evt->event_handler(evt);
+ return IRQ_HANDLED;
+ }
+
+ return IRQ_NONE;
+}
+
+static void arch_timer_disable(void)
+{
+ unsigned long ctrl;
+
+ ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+ ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+ arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+}
+
+static void arch_timer_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *clk)
+{
+ switch (mode) {
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ arch_timer_disable();
+ break;
+ default:
+ break;
+ }
+}
+
+static int arch_timer_set_next_event(unsigned long evt,
+ struct clock_event_device *unused)
+{
+ unsigned long ctrl;
+
+ ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+ ctrl |= ARCH_TIMER_CTRL_ENABLE;
+ ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
+
+ arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
+ arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+
+ return 0;
+}
+
+static int __cpuinit arch_timer_setup(struct clock_event_device *clk)
+{
+ /* Be safe... */
+ arch_timer_disable();
+
+ clk->features = CLOCK_EVT_FEAT_ONESHOT;
+ clk->name = "arch_sys_timer";
+ clk->rating = 450;
+ clk->set_mode = arch_timer_set_mode;
+ clk->set_next_event = arch_timer_set_next_event;
+ clk->irq = arch_timer_ppi;
+
+ clockevents_config_and_register(clk, arch_timer_rate,
+ 0xf, 0x7fffffff);
+
+ *__this_cpu_ptr(arch_timer_evt) = clk;
+
+ enable_percpu_irq(clk->irq, 0);
+ if (arch_timer_ppi2)
+ enable_percpu_irq(arch_timer_ppi2, 0);
+
+ return 0;
+}
+
+/* Is the optional system timer available? */
+static int local_timer_is_architected(void)
+{
+ return (cpu_architecture() >= CPU_ARCH_ARMv7) &&
+ ((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1;
+}
+
+static int arch_timer_available(void)
+{
+ unsigned long freq;
+
+ if (!local_timer_is_architected())
+ return -ENXIO;
+
+ if (arch_timer_rate == 0) {
+ arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
+ freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
+
+ /* Check the timer frequency. */
+ if (freq == 0) {
+ pr_warn("Architected timer frequency not available\n");
+ return -EINVAL;
+ }
+
+ arch_timer_rate = freq;
+ }
+
+ pr_info_once("Architected local timer running at %lu.%02luMHz.\n",
+ arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100);
+ return 0;
+}
+
+static inline cycle_t arch_counter_get_cntpct(void)
+{
+ u32 cvall, cvalh;
+
+ asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+
+ return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static inline cycle_t arch_counter_get_cntvct(void)
+{
+ u32 cvall, cvalh;
+
+ asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+
+ return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static u32 notrace arch_counter_get_cntvct32(void)
+{
+ cycle_t cntvct = arch_counter_get_cntvct();
+
+ /*
+ * The sched_clock infrastructure only knows about counters
+ * with at most 32bits. Forget about the upper 24 bits for the
+ * time being...
+ */
+ return (u32)(cntvct & (u32)~0);
+}
+
+static cycle_t arch_counter_read(struct clocksource *cs)
+{
+ return arch_counter_get_cntpct();
+}
+
+static struct clocksource clocksource_counter = {
+ .name = "arch_sys_counter",
+ .rating = 400,
+ .read = arch_counter_read,
+ .mask = CLOCKSOURCE_MASK(56),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void __cpuinit arch_timer_stop(struct clock_event_device *clk)
+{
+ pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
+ clk->irq, smp_processor_id());
+ disable_percpu_irq(clk->irq);
+ if (arch_timer_ppi2)
+ disable_percpu_irq(arch_timer_ppi2);
+ arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
+}
+
+static struct local_timer_ops arch_timer_ops __cpuinitdata = {
+ .setup = arch_timer_setup,
+ .stop = arch_timer_stop,
+};
+
+static struct clock_event_device arch_timer_global_evt;
+
+static int __init arch_timer_register(void)
+{
+ int err;
+
+ err = arch_timer_available();
+ if (err)
+ return err;
+
+ arch_timer_evt = alloc_percpu(struct clock_event_device *);
+ if (!arch_timer_evt)
+ return -ENOMEM;
+
+ clocksource_register_hz(&clocksource_counter, arch_timer_rate);
+
+ err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
+ "arch_timer", arch_timer_evt);
+ if (err) {
+ pr_err("arch_timer: can't register interrupt %d (%d)\n",
+ arch_timer_ppi, err);
+ goto out_free;
+ }
+
+ if (arch_timer_ppi2) {
+ err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
+ "arch_timer", arch_timer_evt);
+ if (err) {
+ pr_err("arch_timer: can't register interrupt %d (%d)\n",
+ arch_timer_ppi2, err);
+ arch_timer_ppi2 = 0;
+ goto out_free_irq;
+ }
+ }
+
+ err = local_timer_register(&arch_timer_ops);
+ if (err) {
+ /*
+ * We couldn't register as a local timer (could be
+ * because we're on a UP platform, or because some
+ * other local timer is already present...). Try as a
+ * global timer instead.
+ */
+ arch_timer_global_evt.cpumask = cpumask_of(0);
+ err = arch_timer_setup(&arch_timer_global_evt);
+ }
+
+ if (err)
+ goto out_free_irq;
+
+ return 0;
+
+out_free_irq:
+ free_percpu_irq(arch_timer_ppi, arch_timer_evt);
+ if (arch_timer_ppi2)
+ free_percpu_irq(arch_timer_ppi2, arch_timer_evt);
+
+out_free:
+ free_percpu(arch_timer_evt);
+
+ return err;
+}
+
+static const struct of_device_id arch_timer_of_match[] __initconst = {
+ { .compatible = "arm,armv7-timer", },
+ {},
+};
+
+int __init arch_timer_of_register(void)
+{
+ struct device_node *np;
+ u32 freq;
+
+ np = of_find_matching_node(NULL, arch_timer_of_match);
+ if (!np) {
+ pr_err("arch_timer: can't find DT node\n");
+ return -ENODEV;
+ }
+
+ /* Try to determine the frequency from the device tree or CNTFRQ */
+ if (!of_property_read_u32(np, "clock-frequency", &freq))
+ arch_timer_rate = freq;
+
+ arch_timer_ppi = irq_of_parse_and_map(np, 0);
+ arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
+ pr_info("arch_timer: found %s irqs %d %d\n",
+ np->name, arch_timer_ppi, arch_timer_ppi2);
+
+ return arch_timer_register();
+}
+
+int __init arch_timer_sched_clock_init(void)
+{
+ int err;
+
+ err = arch_timer_available();
+ if (err)
+ return err;
+
+ setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
+ return 0;
+}
#endif
/*
- * Swizzle the device pin each time we cross a bridge.
- * This might update pin and returns the slot number.
+ * Swizzle the device pin each time we cross a bridge. If a platform does
+ * not provide a swizzle function, we perform the standard PCI swizzling.
+ *
+ * The default swizzling walks up the bus tree one level at a time, applying
+ * the standard swizzle function at each step, stopping when it finds the PCI
+ * root bus. This will return the slot number of the bridge device on the
+ * root bus and the interrupt pin on that device which should correspond
+ * with the downstream device interrupt.
+ *
+ * Platforms may override this, in which case the slot and pin returned
+ * depend entirely on the platform code. However, please note that the
+ * PCI standard swizzle is implemented on plug-in cards and Cardbus based
+ * PCI extenders, so it can not be ignored.
*/
static u8 __devinit pcibios_swizzle(struct pci_dev *dev, u8 *pin)
{
struct pci_sys_data *sys = dev->sysdata;
- int slot = 0, oldpin = *pin;
+ int slot, oldpin = *pin;
if (sys->swizzle)
slot = sys->swizzle(dev, pin);
+ else
+ slot = pci_common_swizzle(dev, pin);
if (debug_pci)
printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
return irq;
}
-static void __init pcibios_init_hw(struct hw_pci *hw)
+static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
{
struct pci_sys_data *sys = NULL;
int ret;
#ifdef CONFIG_PCI_DOMAINS
sys->domain = hw->domain;
#endif
- sys->hw = hw;
sys->busnr = busnr;
sys->swizzle = hw->swizzle;
sys->map_irq = hw->map_irq;
&iomem_resource, sys->mem_offset);
}
- sys->bus = hw->scan(nr, sys);
+ if (hw->scan)
+ sys->bus = hw->scan(nr, sys);
+ else
+ sys->bus = pci_scan_root_bus(NULL, sys->busnr,
+ hw->ops, sys, &sys->resources);
if (!sys->bus)
panic("PCI: unable to scan bus!");
busnr = sys->bus->subordinate + 1;
- list_add(&sys->node, &hw->buses);
+ list_add(&sys->node, head);
} else {
kfree(sys);
if (ret < 0)
void __init pci_common_init(struct hw_pci *hw)
{
struct pci_sys_data *sys;
-
- INIT_LIST_HEAD(&hw->buses);
+ LIST_HEAD(head);
pci_add_flags(PCI_REASSIGN_ALL_RSRC);
if (hw->preinit)
hw->preinit();
- pcibios_init_hw(hw);
+ pcibios_init_hw(hw, &head);
if (hw->postinit)
hw->postinit();
pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
- list_for_each_entry(sys, &hw->buses, node) {
+ list_for_each_entry(sys, &head, node) {
struct pci_bus *bus = sys->bus;
if (!pci_has_flag(PCI_PROBE_ONLY)) {
#endif
tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
-#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
- and r8, r0, #0x0f000000 @ mask out op-code bits
- teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
-#endif
moveq pc, lr
get_thread_info r10 @ get current thread
and r8, r0, #0x00000f00 @ mask out CP number
*-----------------------------------------------------------------------------
*/
- /* If we're optimising for StrongARM the resulting code won't
- run on an ARM7 and we can save a couple of instructions.
- --pb */
-#ifdef CONFIG_CPU_ARM710
-#define A710(code...) code
-.Larm710bug:
- ldmia sp, {r0 - lr}^ @ Get calling r0 - lr
- mov r0, r0
- add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4
-#else
-#define A710(code...)
-#endif
-
.align 5
ENTRY(vector_swi)
sub sp, sp, #S_FRAME_SIZE
ldreq r10, [lr, #-4] @ get SWI instruction
#else
ldr r10, [lr, #-4] @ get SWI instruction
- A710( and ip, r10, #0x0f000000 @ check for SWI )
- A710( teq ip, #0x0f000000 )
- A710( bne .Larm710bug )
#endif
#ifdef CONFIG_CPU_ENDIAN_BE8
rev r10, r10 @ little endian instruction
/*
* Pure EABI user space always put syscall number into scno (r7).
*/
- A710( ldr ip, [lr, #-4] @ get SWI instruction )
- A710( and ip, ip, #0x0f000000 @ check for SWI )
- A710( teq ip, #0x0f000000 )
- A710( bne .Larm710bug )
-
#elif defined(CONFIG_ARM_THUMB)
-
/* Legacy ABI only, possibly thumb mode. */
tst r8, #PSR_T_BIT @ this is SPSR from save_user_regs
addne scno, r7, #__NR_SYSCALL_BASE @ put OS number in
ldreq scno, [lr, #-4]
#else
-
/* Legacy ABI only. */
ldr scno, [lr, #-4] @ get SWI instruction
- A710( and ip, scno, #0x0f000000 @ check for SWI )
- A710( teq ip, #0x0f000000 )
- A710( bne .Larm710bug )
-
#endif
#ifdef CONFIG_ALIGNMENT_TRAP
mov r3, r3, lsl #PMD_ORDER
add r0, r4, r3
- rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
- cmp r3, #0x0800 @ limit to 512MB
- movhi r3, #0x0800
- add r6, r0, r3
mov r3, r7, lsr #SECTION_SHIFT
ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
orr r3, r7, r3, lsl #SECTION_SHIFT
#else
orr r3, r3, #PMD_SECT_XN
#endif
-1: str r3, [r0], #4
+ str r3, [r0], #4
#ifdef CONFIG_ARM_LPAE
str r7, [r0], #4
#endif
- add r3, r3, #1 << SECTION_SHIFT
- cmp r0, r6
- blo 1b
#else /* CONFIG_DEBUG_ICEDCC || CONFIG_DEBUG_SEMIHOSTING */
/* we don't need any serial debugging mappings */
#include <linux/hw_breakpoint.h>
#include <linux/regset.h>
#include <linux/audit.h>
+#include <linux/tracehook.h>
#include <asm/pgtable.h>
#include <asm/traps.h>
if (!test_thread_flag(TIF_SYSCALL_TRACE))
return scno;
- if (!(current->ptrace & PT_PTRACED))
- return scno;
current_thread_info()->syscall = scno;
ip = regs->ARM_ip;
regs->ARM_ip = why;
- /* the 0x80 provides a way for the tracing parent to distinguish
- between a syscall stop and SIGTRAP delivery */
- ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
- ? 0x80 : 0));
- /*
- * this isn't the same as continuing with a signal, but it will do
- * for normal use. strace only continues with a signal if the
- * stopping signal is not SIGTRAP. -brl
- */
- if (current->exit_code) {
- send_sig(current->exit_code, current, 1);
- current->exit_code = 0;
- }
+ if (why)
+ tracehook_report_syscall_exit(regs, 0);
+ else if (tracehook_report_syscall_entry(regs))
+ current_thread_info()->syscall = -1;
+
regs->ARM_ip = ip;
return current_thread_info()->syscall;
*/
block_sigmask(ka, sig);
+ tracehook_signal_handler(sig, info, ka, regs, 0);
+
return 0;
}
#ifdef CONFIG_LOCAL_TIMERS
int local_timer_register(struct local_timer_ops *ops)
{
+ if (!is_smp() || !setup_max_cpus)
+ return -ENXIO;
+
if (lt_ops)
return -EBUSY;
#include <linux/init.h>
#include <linux/io.h>
+#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include <asm/cacheflush.h>
#include <asm/cputype.h>
int scu_power_mode(void __iomem *scu_base, unsigned int mode)
{
unsigned int val;
- int cpu = smp_processor_id();
+ int cpu = cpu_logical_map(smp_processor_id());
if (mode > 3 || mode == 1 || cpu > 3)
return -EINVAL;
#include <linux/kernel.h>
#include <linux/init.h>
+#include <asm/cputype.h>
#include <asm/system_info.h>
#include <asm/thread_notify.h>
if (cpu_arch < CPU_ARCH_ARMv7)
return 0;
- /* processor feature register 0 */
- asm("mrc p15, 0, %0, c0, c1, 0\n" : "=r" (pfr0));
+ pfr0 = read_cpuid_ext(CPUID_EXT_PFR0);
if ((pfr0 & 0x0000f000) != 0x00001000)
return 0;
}
#endif
+static void dummy_clock_access(struct timespec *ts)
+{
+ ts->tv_sec = 0;
+ ts->tv_nsec = 0;
+}
+
+static clock_access_fn __read_persistent_clock = dummy_clock_access;
+static clock_access_fn __read_boot_clock = dummy_clock_access;;
+
+void read_persistent_clock(struct timespec *ts)
+{
+ __read_persistent_clock(ts);
+}
+
+void read_boot_clock(struct timespec *ts)
+{
+ __read_boot_clock(ts);
+}
+
+int __init register_persistent_clock(clock_access_fn read_boot,
+ clock_access_fn read_persistent)
+{
+ /* Only allow the clockaccess functions to be registered once */
+ if (__read_persistent_clock == dummy_clock_access &&
+ __read_boot_clock == dummy_clock_access) {
+ if (read_boot)
+ __read_boot_clock = read_boot;
+ if (read_persistent)
+ __read_persistent_clock = read_persistent;
+
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
#if defined(CONFIG_PM) && !defined(CONFIG_GENERIC_CLOCKEVENTS)
static int timer_suspend(void)
{
return regs->ARM_r0;
}
-static inline void
+static inline int
do_cache_op(unsigned long start, unsigned long end, int flags)
{
struct mm_struct *mm = current->active_mm;
struct vm_area_struct *vma;
if (end < start || flags)
- return;
+ return -EINVAL;
down_read(&mm->mmap_sem);
vma = find_vma(mm, start);
if (end > vma->vm_end)
end = vma->vm_end;
- flush_cache_user_range(vma, start, end);
+ up_read(&mm->mmap_sem);
+ return flush_cache_user_range(start, end);
}
up_read(&mm->mmap_sem);
+ return -EINVAL;
}
/*
* the specified region).
*/
case NR(cacheflush):
- do_cache_op(regs->ARM_r0, regs->ARM_r1, regs->ARM_r2);
- return 0;
+ return do_cache_op(regs->ARM_r0, regs->ARM_r1, regs->ARM_r2);
case NR(usr26):
if (!(elf_hwcap & HWCAP_26BIT))
call_with_stack.o
mmu-y := clear_user.o copy_page.o getuser.o putuser.o
-
-# the code in uaccess.S is not preemption safe and
-# probably faster on ARMv3 only
-ifeq ($(CONFIG_PREEMPT),y)
- mmu-y += copy_from_user.o copy_to_user.o
-else
-ifneq ($(CONFIG_CPU_32v3),y)
- mmu-y += copy_from_user.o copy_to_user.o
-else
- mmu-y += uaccess.o
-endif
-endif
+mmu-y += copy_from_user.o copy_to_user.o
# using lib_ here won't override already available weak symbols
obj-$(CONFIG_UACCESS_WITH_MEMCPY) += uaccess_with_memcpy.o
-lib-$(CONFIG_MMU) += $(mmu-y)
-
-ifeq ($(CONFIG_CPU_32v3),y)
- lib-y += io-readsw-armv3.o io-writesw-armv3.o
-else
- lib-y += io-readsw-armv4.o io-writesw-armv4.o
-endif
-
+lib-$(CONFIG_MMU) += $(mmu-y)
+lib-y += io-readsw-armv4.o io-writesw-armv4.o
lib-$(CONFIG_ARCH_RPC) += ecard.o io-acorn.o floppydma.o
lib-$(CONFIG_ARCH_SHARK) += io-shark.o
+++ /dev/null
-/*
- * linux/arch/arm/lib/io-readsw-armv3.S
- *
- * Copyright (C) 1995-2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-.Linsw_bad_alignment:
- adr r0, .Linsw_bad_align_msg
- mov r2, lr
- b panic
-.Linsw_bad_align_msg:
- .asciz "insw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
- .align
-
-.Linsw_align: tst r1, #1
- bne .Linsw_bad_alignment
-
- ldr r3, [r0]
- strb r3, [r1], #1
- mov r3, r3, lsr #8
- strb r3, [r1], #1
-
- subs r2, r2, #1
- moveq pc, lr
-
-ENTRY(__raw_readsw)
- teq r2, #0 @ do we have to check for the zero len?
- moveq pc, lr
- tst r1, #3
- bne .Linsw_align
-
-.Linsw_aligned: mov ip, #0xff
- orr ip, ip, ip, lsl #8
- stmfd sp!, {r4, r5, r6, lr}
-
- subs r2, r2, #8
- bmi .Lno_insw_8
-
-.Linsw_8_lp: ldr r3, [r0]
- and r3, r3, ip
- ldr r4, [r0]
- orr r3, r3, r4, lsl #16
-
- ldr r4, [r0]
- and r4, r4, ip
- ldr r5, [r0]
- orr r4, r4, r5, lsl #16
-
- ldr r5, [r0]
- and r5, r5, ip
- ldr r6, [r0]
- orr r5, r5, r6, lsl #16
-
- ldr r6, [r0]
- and r6, r6, ip
- ldr lr, [r0]
- orr r6, r6, lr, lsl #16
-
- stmia r1!, {r3 - r6}
-
- subs r2, r2, #8
- bpl .Linsw_8_lp
-
- tst r2, #7
- ldmeqfd sp!, {r4, r5, r6, pc}
-
-.Lno_insw_8: tst r2, #4
- beq .Lno_insw_4
-
- ldr r3, [r0]
- and r3, r3, ip
- ldr r4, [r0]
- orr r3, r3, r4, lsl #16
-
- ldr r4, [r0]
- and r4, r4, ip
- ldr r5, [r0]
- orr r4, r4, r5, lsl #16
-
- stmia r1!, {r3, r4}
-
-.Lno_insw_4: tst r2, #2
- beq .Lno_insw_2
-
- ldr r3, [r0]
- and r3, r3, ip
- ldr r4, [r0]
- orr r3, r3, r4, lsl #16
-
- str r3, [r1], #4
-
-.Lno_insw_2: tst r2, #1
- ldrne r3, [r0]
- strneb r3, [r1], #1
- movne r3, r3, lsr #8
- strneb r3, [r1]
-
- ldmfd sp!, {r4, r5, r6, pc}
-
-
+++ /dev/null
-/*
- * linux/arch/arm/lib/io-writesw-armv3.S
- *
- * Copyright (C) 1995-2000 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-.Loutsw_bad_alignment:
- adr r0, .Loutsw_bad_align_msg
- mov r2, lr
- b panic
-.Loutsw_bad_align_msg:
- .asciz "outsw: bad buffer alignment (0x%p, lr=0x%08lX)\n"
- .align
-
-.Loutsw_align: tst r1, #1
- bne .Loutsw_bad_alignment
-
- add r1, r1, #2
-
- ldr r3, [r1, #-4]
- mov r3, r3, lsr #16
- orr r3, r3, r3, lsl #16
- str r3, [r0]
- subs r2, r2, #1
- moveq pc, lr
-
-ENTRY(__raw_writesw)
- teq r2, #0 @ do we have to check for the zero len?
- moveq pc, lr
- tst r1, #3
- bne .Loutsw_align
-
- stmfd sp!, {r4, r5, r6, lr}
-
- subs r2, r2, #8
- bmi .Lno_outsw_8
-
-.Loutsw_8_lp: ldmia r1!, {r3, r4, r5, r6}
-
- mov ip, r3, lsl #16
- orr ip, ip, ip, lsr #16
- str ip, [r0]
-
- mov ip, r3, lsr #16
- orr ip, ip, ip, lsl #16
- str ip, [r0]
-
- mov ip, r4, lsl #16
- orr ip, ip, ip, lsr #16
- str ip, [r0]
-
- mov ip, r4, lsr #16
- orr ip, ip, ip, lsl #16
- str ip, [r0]
-
- mov ip, r5, lsl #16
- orr ip, ip, ip, lsr #16
- str ip, [r0]
-
- mov ip, r5, lsr #16
- orr ip, ip, ip, lsl #16
- str ip, [r0]
-
- mov ip, r6, lsl #16
- orr ip, ip, ip, lsr #16
- str ip, [r0]
-
- mov ip, r6, lsr #16
- orr ip, ip, ip, lsl #16
- str ip, [r0]
-
- subs r2, r2, #8
- bpl .Loutsw_8_lp
-
- tst r2, #7
- ldmeqfd sp!, {r4, r5, r6, pc}
-
-.Lno_outsw_8: tst r2, #4
- beq .Lno_outsw_4
-
- ldmia r1!, {r3, r4}
-
- mov ip, r3, lsl #16
- orr ip, ip, ip, lsr #16
- str ip, [r0]
-
- mov ip, r3, lsr #16
- orr ip, ip, ip, lsl #16
- str ip, [r0]
-
- mov ip, r4, lsl #16
- orr ip, ip, ip, lsr #16
- str ip, [r0]
-
- mov ip, r4, lsr #16
- orr ip, ip, ip, lsl #16
- str ip, [r0]
-
-.Lno_outsw_4: tst r2, #2
- beq .Lno_outsw_2
-
- ldr r3, [r1], #4
-
- mov ip, r3, lsl #16
- orr ip, ip, ip, lsr #16
- str ip, [r0]
-
- mov ip, r3, lsr #16
- orr ip, ip, ip, lsl #16
- str ip, [r0]
-
-.Lno_outsw_2: tst r2, #1
-
- ldrne r3, [r1]
-
- movne ip, r3, lsl #16
- orrne ip, ip, ip, lsr #16
- strne ip, [r0]
-
- ldmfd sp!, {r4, r5, r6, pc}
+++ /dev/null
-/*
- * linux/arch/arm/lib/uaccess.S
- *
- * Copyright (C) 1995, 1996,1997,1998 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Routines to block copy data to/from user memory
- * These are highly optimised both for the 4k page size
- * and for various alignments.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <asm/errno.h>
-#include <asm/domain.h>
-
- .text
-
-#define PAGE_SHIFT 12
-
-/* Prototype: int __copy_to_user(void *to, const char *from, size_t n)
- * Purpose : copy a block to user memory from kernel memory
- * Params : to - user memory
- * : from - kernel memory
- * : n - number of bytes to copy
- * Returns : Number of bytes NOT copied.
- */
-
-.Lc2u_dest_not_aligned:
- rsb ip, ip, #4
- cmp ip, #2
- ldrb r3, [r1], #1
-USER( TUSER( strb) r3, [r0], #1) @ May fault
- ldrgeb r3, [r1], #1
-USER( TUSER( strgeb) r3, [r0], #1) @ May fault
- ldrgtb r3, [r1], #1
-USER( TUSER( strgtb) r3, [r0], #1) @ May fault
- sub r2, r2, ip
- b .Lc2u_dest_aligned
-
-ENTRY(__copy_to_user)
- stmfd sp!, {r2, r4 - r7, lr}
- cmp r2, #4
- blt .Lc2u_not_enough
- ands ip, r0, #3
- bne .Lc2u_dest_not_aligned
-.Lc2u_dest_aligned:
-
- ands ip, r1, #3
- bne .Lc2u_src_not_aligned
-/*
- * Seeing as there has to be at least 8 bytes to copy, we can
- * copy one word, and force a user-mode page fault...
- */
-
-.Lc2u_0fupi: subs r2, r2, #4
- addmi ip, r2, #4
- bmi .Lc2u_0nowords
- ldr r3, [r1], #4
-USER( TUSER( str) r3, [r0], #4) @ May fault
- mov ip, r0, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction
- rsb ip, ip, #0
- movs ip, ip, lsr #32 - PAGE_SHIFT
- beq .Lc2u_0fupi
-/*
- * ip = max no. of bytes to copy before needing another "strt" insn
- */
- cmp r2, ip
- movlt ip, r2
- sub r2, r2, ip
- subs ip, ip, #32
- blt .Lc2u_0rem8lp
-
-.Lc2u_0cpy8lp: ldmia r1!, {r3 - r6}
- stmia r0!, {r3 - r6} @ Shouldnt fault
- ldmia r1!, {r3 - r6}
- subs ip, ip, #32
- stmia r0!, {r3 - r6} @ Shouldnt fault
- bpl .Lc2u_0cpy8lp
-
-.Lc2u_0rem8lp: cmn ip, #16
- ldmgeia r1!, {r3 - r6}
- stmgeia r0!, {r3 - r6} @ Shouldnt fault
- tst ip, #8
- ldmneia r1!, {r3 - r4}
- stmneia r0!, {r3 - r4} @ Shouldnt fault
- tst ip, #4
- ldrne r3, [r1], #4
- TUSER( strne) r3, [r0], #4 @ Shouldnt fault
- ands ip, ip, #3
- beq .Lc2u_0fupi
-.Lc2u_0nowords: teq ip, #0
- beq .Lc2u_finished
-.Lc2u_nowords: cmp ip, #2
- ldrb r3, [r1], #1
-USER( TUSER( strb) r3, [r0], #1) @ May fault
- ldrgeb r3, [r1], #1
-USER( TUSER( strgeb) r3, [r0], #1) @ May fault
- ldrgtb r3, [r1], #1
-USER( TUSER( strgtb) r3, [r0], #1) @ May fault
- b .Lc2u_finished
-
-.Lc2u_not_enough:
- movs ip, r2
- bne .Lc2u_nowords
-.Lc2u_finished: mov r0, #0
- ldmfd sp!, {r2, r4 - r7, pc}
-
-.Lc2u_src_not_aligned:
- bic r1, r1, #3
- ldr r7, [r1], #4
- cmp ip, #2
- bgt .Lc2u_3fupi
- beq .Lc2u_2fupi
-.Lc2u_1fupi: subs r2, r2, #4
- addmi ip, r2, #4
- bmi .Lc2u_1nowords
- mov r3, r7, pull #8
- ldr r7, [r1], #4
- orr r3, r3, r7, push #24
-USER( TUSER( str) r3, [r0], #4) @ May fault
- mov ip, r0, lsl #32 - PAGE_SHIFT
- rsb ip, ip, #0
- movs ip, ip, lsr #32 - PAGE_SHIFT
- beq .Lc2u_1fupi
- cmp r2, ip
- movlt ip, r2
- sub r2, r2, ip
- subs ip, ip, #16
- blt .Lc2u_1rem8lp
-
-.Lc2u_1cpy8lp: mov r3, r7, pull #8
- ldmia r1!, {r4 - r7}
- subs ip, ip, #16
- orr r3, r3, r4, push #24
- mov r4, r4, pull #8
- orr r4, r4, r5, push #24
- mov r5, r5, pull #8
- orr r5, r5, r6, push #24
- mov r6, r6, pull #8
- orr r6, r6, r7, push #24
- stmia r0!, {r3 - r6} @ Shouldnt fault
- bpl .Lc2u_1cpy8lp
-
-.Lc2u_1rem8lp: tst ip, #8
- movne r3, r7, pull #8
- ldmneia r1!, {r4, r7}
- orrne r3, r3, r4, push #24
- movne r4, r4, pull #8
- orrne r4, r4, r7, push #24
- stmneia r0!, {r3 - r4} @ Shouldnt fault
- tst ip, #4
- movne r3, r7, pull #8
- ldrne r7, [r1], #4
- orrne r3, r3, r7, push #24
- TUSER( strne) r3, [r0], #4 @ Shouldnt fault
- ands ip, ip, #3
- beq .Lc2u_1fupi
-.Lc2u_1nowords: mov r3, r7, get_byte_1
- teq ip, #0
- beq .Lc2u_finished
- cmp ip, #2
-USER( TUSER( strb) r3, [r0], #1) @ May fault
- movge r3, r7, get_byte_2
-USER( TUSER( strgeb) r3, [r0], #1) @ May fault
- movgt r3, r7, get_byte_3
-USER( TUSER( strgtb) r3, [r0], #1) @ May fault
- b .Lc2u_finished
-
-.Lc2u_2fupi: subs r2, r2, #4
- addmi ip, r2, #4
- bmi .Lc2u_2nowords
- mov r3, r7, pull #16
- ldr r7, [r1], #4
- orr r3, r3, r7, push #16
-USER( TUSER( str) r3, [r0], #4) @ May fault
- mov ip, r0, lsl #32 - PAGE_SHIFT
- rsb ip, ip, #0
- movs ip, ip, lsr #32 - PAGE_SHIFT
- beq .Lc2u_2fupi
- cmp r2, ip
- movlt ip, r2
- sub r2, r2, ip
- subs ip, ip, #16
- blt .Lc2u_2rem8lp
-
-.Lc2u_2cpy8lp: mov r3, r7, pull #16
- ldmia r1!, {r4 - r7}
- subs ip, ip, #16
- orr r3, r3, r4, push #16
- mov r4, r4, pull #16
- orr r4, r4, r5, push #16
- mov r5, r5, pull #16
- orr r5, r5, r6, push #16
- mov r6, r6, pull #16
- orr r6, r6, r7, push #16
- stmia r0!, {r3 - r6} @ Shouldnt fault
- bpl .Lc2u_2cpy8lp
-
-.Lc2u_2rem8lp: tst ip, #8
- movne r3, r7, pull #16
- ldmneia r1!, {r4, r7}
- orrne r3, r3, r4, push #16
- movne r4, r4, pull #16
- orrne r4, r4, r7, push #16
- stmneia r0!, {r3 - r4} @ Shouldnt fault
- tst ip, #4
- movne r3, r7, pull #16
- ldrne r7, [r1], #4
- orrne r3, r3, r7, push #16
- TUSER( strne) r3, [r0], #4 @ Shouldnt fault
- ands ip, ip, #3
- beq .Lc2u_2fupi
-.Lc2u_2nowords: mov r3, r7, get_byte_2
- teq ip, #0
- beq .Lc2u_finished
- cmp ip, #2
-USER( TUSER( strb) r3, [r0], #1) @ May fault
- movge r3, r7, get_byte_3
-USER( TUSER( strgeb) r3, [r0], #1) @ May fault
- ldrgtb r3, [r1], #0
-USER( TUSER( strgtb) r3, [r0], #1) @ May fault
- b .Lc2u_finished
-
-.Lc2u_3fupi: subs r2, r2, #4
- addmi ip, r2, #4
- bmi .Lc2u_3nowords
- mov r3, r7, pull #24
- ldr r7, [r1], #4
- orr r3, r3, r7, push #8
-USER( TUSER( str) r3, [r0], #4) @ May fault
- mov ip, r0, lsl #32 - PAGE_SHIFT
- rsb ip, ip, #0
- movs ip, ip, lsr #32 - PAGE_SHIFT
- beq .Lc2u_3fupi
- cmp r2, ip
- movlt ip, r2
- sub r2, r2, ip
- subs ip, ip, #16
- blt .Lc2u_3rem8lp
-
-.Lc2u_3cpy8lp: mov r3, r7, pull #24
- ldmia r1!, {r4 - r7}
- subs ip, ip, #16
- orr r3, r3, r4, push #8
- mov r4, r4, pull #24
- orr r4, r4, r5, push #8
- mov r5, r5, pull #24
- orr r5, r5, r6, push #8
- mov r6, r6, pull #24
- orr r6, r6, r7, push #8
- stmia r0!, {r3 - r6} @ Shouldnt fault
- bpl .Lc2u_3cpy8lp
-
-.Lc2u_3rem8lp: tst ip, #8
- movne r3, r7, pull #24
- ldmneia r1!, {r4, r7}
- orrne r3, r3, r4, push #8
- movne r4, r4, pull #24
- orrne r4, r4, r7, push #8
- stmneia r0!, {r3 - r4} @ Shouldnt fault
- tst ip, #4
- movne r3, r7, pull #24
- ldrne r7, [r1], #4
- orrne r3, r3, r7, push #8
- TUSER( strne) r3, [r0], #4 @ Shouldnt fault
- ands ip, ip, #3
- beq .Lc2u_3fupi
-.Lc2u_3nowords: mov r3, r7, get_byte_3
- teq ip, #0
- beq .Lc2u_finished
- cmp ip, #2
-USER( TUSER( strb) r3, [r0], #1) @ May fault
- ldrgeb r3, [r1], #1
-USER( TUSER( strgeb) r3, [r0], #1) @ May fault
- ldrgtb r3, [r1], #0
-USER( TUSER( strgtb) r3, [r0], #1) @ May fault
- b .Lc2u_finished
-ENDPROC(__copy_to_user)
-
- .pushsection .fixup,"ax"
- .align 0
-9001: ldmfd sp!, {r0, r4 - r7, pc}
- .popsection
-
-/* Prototype: unsigned long __copy_from_user(void *to,const void *from,unsigned long n);
- * Purpose : copy a block from user memory to kernel memory
- * Params : to - kernel memory
- * : from - user memory
- * : n - number of bytes to copy
- * Returns : Number of bytes NOT copied.
- */
-.Lcfu_dest_not_aligned:
- rsb ip, ip, #4
- cmp ip, #2
-USER( TUSER( ldrb) r3, [r1], #1) @ May fault
- strb r3, [r0], #1
-USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
- strgeb r3, [r0], #1
-USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
- strgtb r3, [r0], #1
- sub r2, r2, ip
- b .Lcfu_dest_aligned
-
-ENTRY(__copy_from_user)
- stmfd sp!, {r0, r2, r4 - r7, lr}
- cmp r2, #4
- blt .Lcfu_not_enough
- ands ip, r0, #3
- bne .Lcfu_dest_not_aligned
-.Lcfu_dest_aligned:
- ands ip, r1, #3
- bne .Lcfu_src_not_aligned
-
-/*
- * Seeing as there has to be at least 8 bytes to copy, we can
- * copy one word, and force a user-mode page fault...
- */
-
-.Lcfu_0fupi: subs r2, r2, #4
- addmi ip, r2, #4
- bmi .Lcfu_0nowords
-USER( TUSER( ldr) r3, [r1], #4)
- str r3, [r0], #4
- mov ip, r1, lsl #32 - PAGE_SHIFT @ On each page, use a ld/st??t instruction
- rsb ip, ip, #0
- movs ip, ip, lsr #32 - PAGE_SHIFT
- beq .Lcfu_0fupi
-/*
- * ip = max no. of bytes to copy before needing another "strt" insn
- */
- cmp r2, ip
- movlt ip, r2
- sub r2, r2, ip
- subs ip, ip, #32
- blt .Lcfu_0rem8lp
-
-.Lcfu_0cpy8lp: ldmia r1!, {r3 - r6} @ Shouldnt fault
- stmia r0!, {r3 - r6}
- ldmia r1!, {r3 - r6} @ Shouldnt fault
- subs ip, ip, #32
- stmia r0!, {r3 - r6}
- bpl .Lcfu_0cpy8lp
-
-.Lcfu_0rem8lp: cmn ip, #16
- ldmgeia r1!, {r3 - r6} @ Shouldnt fault
- stmgeia r0!, {r3 - r6}
- tst ip, #8
- ldmneia r1!, {r3 - r4} @ Shouldnt fault
- stmneia r0!, {r3 - r4}
- tst ip, #4
- TUSER( ldrne) r3, [r1], #4 @ Shouldnt fault
- strne r3, [r0], #4
- ands ip, ip, #3
- beq .Lcfu_0fupi
-.Lcfu_0nowords: teq ip, #0
- beq .Lcfu_finished
-.Lcfu_nowords: cmp ip, #2
-USER( TUSER( ldrb) r3, [r1], #1) @ May fault
- strb r3, [r0], #1
-USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
- strgeb r3, [r0], #1
-USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
- strgtb r3, [r0], #1
- b .Lcfu_finished
-
-.Lcfu_not_enough:
- movs ip, r2
- bne .Lcfu_nowords
-.Lcfu_finished: mov r0, #0
- add sp, sp, #8
- ldmfd sp!, {r4 - r7, pc}
-
-.Lcfu_src_not_aligned:
- bic r1, r1, #3
-USER( TUSER( ldr) r7, [r1], #4) @ May fault
- cmp ip, #2
- bgt .Lcfu_3fupi
- beq .Lcfu_2fupi
-.Lcfu_1fupi: subs r2, r2, #4
- addmi ip, r2, #4
- bmi .Lcfu_1nowords
- mov r3, r7, pull #8
-USER( TUSER( ldr) r7, [r1], #4) @ May fault
- orr r3, r3, r7, push #24
- str r3, [r0], #4
- mov ip, r1, lsl #32 - PAGE_SHIFT
- rsb ip, ip, #0
- movs ip, ip, lsr #32 - PAGE_SHIFT
- beq .Lcfu_1fupi
- cmp r2, ip
- movlt ip, r2
- sub r2, r2, ip
- subs ip, ip, #16
- blt .Lcfu_1rem8lp
-
-.Lcfu_1cpy8lp: mov r3, r7, pull #8
- ldmia r1!, {r4 - r7} @ Shouldnt fault
- subs ip, ip, #16
- orr r3, r3, r4, push #24
- mov r4, r4, pull #8
- orr r4, r4, r5, push #24
- mov r5, r5, pull #8
- orr r5, r5, r6, push #24
- mov r6, r6, pull #8
- orr r6, r6, r7, push #24
- stmia r0!, {r3 - r6}
- bpl .Lcfu_1cpy8lp
-
-.Lcfu_1rem8lp: tst ip, #8
- movne r3, r7, pull #8
- ldmneia r1!, {r4, r7} @ Shouldnt fault
- orrne r3, r3, r4, push #24
- movne r4, r4, pull #8
- orrne r4, r4, r7, push #24
- stmneia r0!, {r3 - r4}
- tst ip, #4
- movne r3, r7, pull #8
-USER( TUSER( ldrne) r7, [r1], #4) @ May fault
- orrne r3, r3, r7, push #24
- strne r3, [r0], #4
- ands ip, ip, #3
- beq .Lcfu_1fupi
-.Lcfu_1nowords: mov r3, r7, get_byte_1
- teq ip, #0
- beq .Lcfu_finished
- cmp ip, #2
- strb r3, [r0], #1
- movge r3, r7, get_byte_2
- strgeb r3, [r0], #1
- movgt r3, r7, get_byte_3
- strgtb r3, [r0], #1
- b .Lcfu_finished
-
-.Lcfu_2fupi: subs r2, r2, #4
- addmi ip, r2, #4
- bmi .Lcfu_2nowords
- mov r3, r7, pull #16
-USER( TUSER( ldr) r7, [r1], #4) @ May fault
- orr r3, r3, r7, push #16
- str r3, [r0], #4
- mov ip, r1, lsl #32 - PAGE_SHIFT
- rsb ip, ip, #0
- movs ip, ip, lsr #32 - PAGE_SHIFT
- beq .Lcfu_2fupi
- cmp r2, ip
- movlt ip, r2
- sub r2, r2, ip
- subs ip, ip, #16
- blt .Lcfu_2rem8lp
-
-
-.Lcfu_2cpy8lp: mov r3, r7, pull #16
- ldmia r1!, {r4 - r7} @ Shouldnt fault
- subs ip, ip, #16
- orr r3, r3, r4, push #16
- mov r4, r4, pull #16
- orr r4, r4, r5, push #16
- mov r5, r5, pull #16
- orr r5, r5, r6, push #16
- mov r6, r6, pull #16
- orr r6, r6, r7, push #16
- stmia r0!, {r3 - r6}
- bpl .Lcfu_2cpy8lp
-
-.Lcfu_2rem8lp: tst ip, #8
- movne r3, r7, pull #16
- ldmneia r1!, {r4, r7} @ Shouldnt fault
- orrne r3, r3, r4, push #16
- movne r4, r4, pull #16
- orrne r4, r4, r7, push #16
- stmneia r0!, {r3 - r4}
- tst ip, #4
- movne r3, r7, pull #16
-USER( TUSER( ldrne) r7, [r1], #4) @ May fault
- orrne r3, r3, r7, push #16
- strne r3, [r0], #4
- ands ip, ip, #3
- beq .Lcfu_2fupi
-.Lcfu_2nowords: mov r3, r7, get_byte_2
- teq ip, #0
- beq .Lcfu_finished
- cmp ip, #2
- strb r3, [r0], #1
- movge r3, r7, get_byte_3
- strgeb r3, [r0], #1
-USER( TUSER( ldrgtb) r3, [r1], #0) @ May fault
- strgtb r3, [r0], #1
- b .Lcfu_finished
-
-.Lcfu_3fupi: subs r2, r2, #4
- addmi ip, r2, #4
- bmi .Lcfu_3nowords
- mov r3, r7, pull #24
-USER( TUSER( ldr) r7, [r1], #4) @ May fault
- orr r3, r3, r7, push #8
- str r3, [r0], #4
- mov ip, r1, lsl #32 - PAGE_SHIFT
- rsb ip, ip, #0
- movs ip, ip, lsr #32 - PAGE_SHIFT
- beq .Lcfu_3fupi
- cmp r2, ip
- movlt ip, r2
- sub r2, r2, ip
- subs ip, ip, #16
- blt .Lcfu_3rem8lp
-
-.Lcfu_3cpy8lp: mov r3, r7, pull #24
- ldmia r1!, {r4 - r7} @ Shouldnt fault
- orr r3, r3, r4, push #8
- mov r4, r4, pull #24
- orr r4, r4, r5, push #8
- mov r5, r5, pull #24
- orr r5, r5, r6, push #8
- mov r6, r6, pull #24
- orr r6, r6, r7, push #8
- stmia r0!, {r3 - r6}
- subs ip, ip, #16
- bpl .Lcfu_3cpy8lp
-
-.Lcfu_3rem8lp: tst ip, #8
- movne r3, r7, pull #24
- ldmneia r1!, {r4, r7} @ Shouldnt fault
- orrne r3, r3, r4, push #8
- movne r4, r4, pull #24
- orrne r4, r4, r7, push #8
- stmneia r0!, {r3 - r4}
- tst ip, #4
- movne r3, r7, pull #24
-USER( TUSER( ldrne) r7, [r1], #4) @ May fault
- orrne r3, r3, r7, push #8
- strne r3, [r0], #4
- ands ip, ip, #3
- beq .Lcfu_3fupi
-.Lcfu_3nowords: mov r3, r7, get_byte_3
- teq ip, #0
- beq .Lcfu_finished
- cmp ip, #2
- strb r3, [r0], #1
-USER( TUSER( ldrgeb) r3, [r1], #1) @ May fault
- strgeb r3, [r0], #1
-USER( TUSER( ldrgtb) r3, [r1], #1) @ May fault
- strgtb r3, [r0], #1
- b .Lcfu_finished
-ENDPROC(__copy_from_user)
-
- .pushsection .fixup,"ax"
- .align 0
- /*
- * We took an exception. r0 contains a pointer to
- * the byte not copied.
- */
-9001: ldr r2, [sp], #4 @ void *to
- sub r2, r0, r2 @ bytes copied
- ldr r1, [sp], #4 @ unsigned long count
- subs r4, r1, r2 @ bytes left to copy
- movne r1, r4
- blne __memzero
- mov r0, r4
- ldmfd sp!, {r4 - r7, pc}
- .popsection
-
.write = cns3xxx_pci_write_config,
};
-static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
-{
- return pci_scan_root_bus(NULL, sys->busnr, &cns3xxx_pcie_ops, sys,
- &sys->resources);
-}
-
static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
.irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
.hw_pci = {
.domain = 0,
- .swizzle = pci_std_swizzle,
.nr_controllers = 1,
+ .ops = &cns3xxx_pcie_ops,
.setup = cns3xxx_pci_setup,
- .scan = cns3xxx_pci_scan_bus,
.map_irq = cns3xxx_pcie_map_irq,
},
},
.irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
.hw_pci = {
.domain = 1,
- .swizzle = pci_std_swizzle,
.nr_controllers = 1,
+ .ops = &cns3xxx_pcie_ops,
.setup = cns3xxx_pci_setup,
- .scan = cns3xxx_pci_scan_bus,
.map_irq = cns3xxx_pcie_map_irq,
},
},
return 0;
pp = &pcie_port[nr];
+ sys->private_data = pp;
pp->root_bus_nr = sys->busnr;
/*
return 1;
}
-static struct pcie_port *bus_to_port(int bus)
-{
- int i;
-
- for (i = num_pcie_ports - 1; i >= 0; i--) {
- int rbus = pcie_port[i].root_bus_nr;
- if (rbus != -1 && rbus <= bus)
- break;
- }
-
- return i >= 0 ? pcie_port + i : NULL;
-}
-
static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
{
/*
static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 *val)
{
- struct pcie_port *pp = bus_to_port(bus->number);
+ struct pci_sys_data *sys = bus->sysdata;
+ struct pcie_port *pp = sys->private_data;
unsigned long flags;
int ret;
static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
- struct pcie_port *pp = bus_to_port(bus->number);
+ struct pci_sys_data *sys = bus->sysdata;
+ struct pcie_port *pp = sys->private_data;
unsigned long flags;
int ret;
static int __init dove_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
- struct pcie_port *pp = bus_to_port(dev->bus->number);
+ struct pci_sys_data *sys = dev->sysdata;
+ struct pcie_port *pp = sys->private_data;
return pp->index ? IRQ_DOVE_PCIE1 : IRQ_DOVE_PCIE0;
}
static struct hw_pci dove_pci __initdata = {
.nr_controllers = 2,
- .swizzle = pci_std_swizzle,
.setup = dove_pcie_setup,
.scan = dove_pcie_scan_bus,
.map_irq = dove_pcie_map_irq,
/* cats host-specific stuff */
static int irqmap_cats[] __initdata = { IRQ_PCI, IRQ_IN0, IRQ_IN1, IRQ_IN3 };
+static u8 cats_no_swizzle(struct pci_dev *dev, u8 *pin)
+{
+ return 0;
+}
+
static int __init cats_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (dev->irq >= 255)
* cards being used (ie, pci-pci bridge based cards)?
*/
static struct hw_pci cats_pci __initdata = {
- .swizzle = NULL,
+ .swizzle = cats_no_swizzle,
.map_irq = cats_map_irq,
.nr_controllers = 1,
+ .ops = &dc21285_ops,
.setup = dc21285_setup,
- .scan = dc21285_scan_bus,
.preinit = dc21285_preinit,
.postinit = dc21285_postinit,
};
return PCIBIOS_SUCCESSFUL;
}
-static struct pci_ops dc21285_ops = {
+struct pci_ops dc21285_ops = {
.read = dc21285_read_config,
.write = dc21285_write_config,
};
return 1;
}
-struct pci_bus * __init dc21285_scan_bus(int nr, struct pci_sys_data *sys)
-{
- return pci_scan_root_bus(NULL, 0, &dc21285_ops, sys, &sys->resources);
-}
-
#define dc21285_request_irq(_a, _b, _c, _d, _e) \
WARN_ON(request_irq(_a, _b, _c, _d, _e) < 0)
}
static struct hw_pci ebsa285_pci __initdata = {
- .swizzle = pci_std_swizzle,
.map_irq = ebsa285_map_irq,
.nr_controllers = 1,
+ .ops = &dc21285_ops,
.setup = dc21285_setup,
- .scan = dc21285_scan_bus,
.preinit = dc21285_preinit,
.postinit = dc21285_postinit,
};
}
static struct hw_pci netwinder_pci __initdata = {
- .swizzle = pci_std_swizzle,
.map_irq = netwinder_map_irq,
.nr_controllers = 1,
+ .ops = &dc21285_ops,
.setup = dc21285_setup,
- .scan = dc21285_scan_bus,
.preinit = dc21285_preinit,
.postinit = dc21285_postinit,
};
static struct hw_pci personal_server_pci __initdata = {
.map_irq = personal_server_map_irq,
.nr_controllers = 1,
+ .ops = &dc21285_ops,
.setup = dc21285_setup,
- .scan = dc21285_scan_bus,
.preinit = dc21285_preinit,
.postinit = dc21285_postinit,
};
struct impd1_device *idev = impd1_devs + i;
struct amba_device *d;
unsigned long pc_base;
+ char devname[32];
pc_base = dev->resource.start + idev->offset;
-
- d = amba_device_alloc(NULL, pc_base, SZ_4K);
- if (!d)
+ snprintf(devname, 32, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
+ d = amba_ahb_device_add(&dev->dev, devname, pc_base, SZ_4K,
+ dev->irq, dev->irq,
+ idev->platform_data, idev->id);
+ if (IS_ERR(d)) {
+ dev_err(&dev->dev, "unable to register device: %ld\n", PTR_ERR(d));
continue;
-
- dev_set_name(&d->dev, "lm%x:%5.5lx", dev->id, idev->offset >> 12);
- d->dev.parent = &dev->dev;
- d->irq[0] = dev->irq;
- d->irq[1] = dev->irq;
- d->periphid = idev->id;
- d->dev.platform_data = idev->platform_data;
-
- ret = amba_device_add(d, &dev->resource);
- if (ret) {
- dev_err(&d->dev, "unable to register device: %d\n", ret);
- amba_device_put(d);
}
}
+++ /dev/null
-/*
- * arch/arm/mach-integrator/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for Integrator platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <mach/irqs.h>
-
- .macro get_irqnr_preamble, base, tmp
- .endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-/* FIXME: should not be using soo many LDRs here */
- ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
- mov \irqnr, #IRQ_PIC_START
- ldr \irqstat, [\base, #IRQ_STATUS] @ get masked status
- ldr \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE)
- teq \irqstat, #0
- ldreq \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)]
- moveq \irqnr, #IRQ_CIC_START
-
-1001: tst \irqstat, #15
- bne 1002f
- add \irqnr, \irqnr, #4
- movs \irqstat, \irqstat, lsr #4
- bne 1001b
-1002: tst \irqstat, #1
- bne 1003f
- add \irqnr, \irqnr, #1
- movs \irqstat, \irqstat, lsr #1
- bne 1002b
-1003: /* EQ will be set if no irqs pending */
- .endm
-
/*
* Interrupt numbers
*/
-#define IRQ_PIC_START 0
-#define IRQ_SOFTINT 0
-#define IRQ_UARTINT0 1
-#define IRQ_UARTINT1 2
-#define IRQ_KMIINT0 3
-#define IRQ_KMIINT1 4
-#define IRQ_TIMERINT0 5
-#define IRQ_TIMERINT1 6
-#define IRQ_TIMERINT2 7
-#define IRQ_RTCINT 8
-#define IRQ_AP_EXPINT0 9
-#define IRQ_AP_EXPINT1 10
-#define IRQ_AP_EXPINT2 11
-#define IRQ_AP_EXPINT3 12
-#define IRQ_AP_PCIINT0 13
-#define IRQ_AP_PCIINT1 14
-#define IRQ_AP_PCIINT2 15
-#define IRQ_AP_PCIINT3 16
-#define IRQ_AP_V3INT 17
-#define IRQ_AP_CPINT0 18
-#define IRQ_AP_CPINT1 19
-#define IRQ_AP_LBUSTIMEOUT 20
-#define IRQ_AP_APCINT 21
-#define IRQ_CP_CLCDCINT 22
-#define IRQ_CP_MMCIINT0 23
-#define IRQ_CP_MMCIINT1 24
-#define IRQ_CP_AACIINT 25
-#define IRQ_CP_CPPLDINT 26
-#define IRQ_CP_ETHINT 27
-#define IRQ_CP_TSPENINT 28
-#define IRQ_PIC_END 31
+#define IRQ_PIC_START 1
+#define IRQ_SOFTINT 1
+#define IRQ_UARTINT0 2
+#define IRQ_UARTINT1 3
+#define IRQ_KMIINT0 4
+#define IRQ_KMIINT1 5
+#define IRQ_TIMERINT0 6
+#define IRQ_TIMERINT1 7
+#define IRQ_TIMERINT2 8
+#define IRQ_RTCINT 9
+#define IRQ_AP_EXPINT0 10
+#define IRQ_AP_EXPINT1 11
+#define IRQ_AP_EXPINT2 12
+#define IRQ_AP_EXPINT3 13
+#define IRQ_AP_PCIINT0 14
+#define IRQ_AP_PCIINT1 15
+#define IRQ_AP_PCIINT2 16
+#define IRQ_AP_PCIINT3 17
+#define IRQ_AP_V3INT 18
+#define IRQ_AP_CPINT0 19
+#define IRQ_AP_CPINT1 20
+#define IRQ_AP_LBUSTIMEOUT 21
+#define IRQ_AP_APCINT 22
+#define IRQ_CP_CLCDCINT 23
+#define IRQ_CP_MMCIINT0 24
+#define IRQ_CP_MMCIINT1 25
+#define IRQ_CP_AACIINT 26
+#define IRQ_CP_CPPLDINT 27
+#define IRQ_CP_ETHINT 28
+#define IRQ_CP_TSPENINT 29
+#define IRQ_PIC_END 29
#define IRQ_CIC_START 32
#define IRQ_CM_SOFTINT 32
#define NR_IRQS_INTEGRATOR_AP 34
#define NR_IRQS_INTEGRATOR_CP 47
-
#define INTEGRATOR_SC_VALID_INT 0x003fffff
-static struct fpga_irq_data sc_irq_data = {
- .base = VA_IC_BASE,
- .irq_start = 0,
- .chip.name = "SC",
-};
-
static void __init ap_init_irq(void)
{
/* Disable all interrupts initially. */
writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR);
writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR);
- fpga_irq_init(-1, INTEGRATOR_SC_VALID_INT, &sc_irq_data);
+ fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
+ -1, INTEGRATOR_SC_VALID_INT, NULL);
}
#ifdef CONFIG_PM
.nr_irqs = NR_IRQS_INTEGRATOR_AP,
.init_early = integrator_init_early,
.init_irq = ap_init_irq,
+ .handle_irq = fpga_handle_irq,
.timer = &ap_timer,
.init_machine = ap_init,
.restart = integrator_restart,
iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
}
-static struct fpga_irq_data cic_irq_data = {
- .base = INTCP_VA_CIC_BASE,
- .irq_start = IRQ_CIC_START,
- .chip.name = "CIC",
-};
-
-static struct fpga_irq_data pic_irq_data = {
- .base = INTCP_VA_PIC_BASE,
- .irq_start = IRQ_PIC_START,
- .chip.name = "PIC",
-};
-
-static struct fpga_irq_data sic_irq_data = {
- .base = INTCP_VA_SIC_BASE,
- .irq_start = IRQ_SIC_START,
- .chip.name = "SIC",
-};
-
static void __init intcp_init_irq(void)
{
- u32 pic_mask, sic_mask;
+ u32 pic_mask, cic_mask, sic_mask;
+ /* These masks are for the HW IRQ registers */
pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
pic_mask |= (~((~0u) << (29 - 22))) << 22;
+ cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
/*
writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
- fpga_irq_init(-1, pic_mask, &pic_irq_data);
+ fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START,
+ -1, pic_mask, NULL);
- fpga_irq_init(-1, ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)),
- &cic_irq_data);
+ fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START,
+ -1, cic_mask, NULL);
- fpga_irq_init(IRQ_CP_CPPLDINT, sic_mask, &sic_irq_data);
+ fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
+ IRQ_CP_CPPLDINT, sic_mask, NULL);
}
/*
.nr_irqs = NR_IRQS_INTEGRATOR_CP,
.init_early = intcp_init_early,
.init_irq = intcp_init_irq,
+ .handle_irq = fpga_handle_irq,
.timer = &cp_timer,
.init_machine = intcp_init,
.restart = integrator_restart,
*/
static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
{
- int pin = *pinp;
+ if (*pinp == 0)
+ *pinp = 1;
- if (pin == 0)
- pin = 1;
-
- while (dev->bus->self) {
- pin = pci_swizzle_interrupt_pin(dev, pin);
- /*
- * move up the chain of bridges, swizzling as we go.
- */
- dev = dev->bus->self;
- }
- *pinp = pin;
-
- return PCI_SLOT(dev->devfn);
+ return pci_common_swizzle(dev, pinp);
}
static int irq_tab[4] __initdata = {
.map_irq = integrator_map_irq,
.setup = pci_v3_setup,
.nr_controllers = 1,
- .scan = pci_v3_scan_bus,
+ .ops = &pci_v3_ops,
.preinit = pci_v3_preinit,
.postinit = pci_v3_postinit,
};
return PCIBIOS_SUCCESSFUL;
}
-static struct pci_ops pci_v3_ops = {
+struct pci_ops pci_v3_ops = {
.read = v3_read_config,
.write = v3_write_config,
};
return ret;
}
-struct pci_bus * __init pci_v3_scan_bus(int nr, struct pci_sys_data *sys)
-{
- return pci_scan_root_bus(NULL, sys->busnr, &pci_v3_ops, sys,
- &sys->resources);
-}
-
/*
* V3_LB_BASE? - local bus address
* V3_LB_MAP? - pci bus address
}
static struct hw_pci iq81340mc_pci __initdata = {
- .swizzle = pci_std_swizzle,
.nr_controllers = 0,
.setup = iop13xx_pci_setup,
.map_irq = iq81340mc_pcix_map_irq,
}
static struct hw_pci iq81340sc_pci __initdata = {
- .swizzle = pci_std_swizzle,
.nr_controllers = 0,
.setup = iop13xx_pci_setup,
.scan = iop13xx_scan_bus,
}
static struct hw_pci em7210_pci __initdata = {
- .swizzle = pci_std_swizzle,
.nr_controllers = 1,
+ .ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
- .scan = iop3xx_pci_scan_bus,
.map_irq = em7210_pci_map_irq,
};
}
static struct hw_pci glantank_pci __initdata = {
- .swizzle = pci_std_swizzle,
.nr_controllers = 1,
+ .ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
- .scan = iop3xx_pci_scan_bus,
.map_irq = glantank_pci_map_irq,
};
}
static struct hw_pci ep80219_pci __initdata = {
- .swizzle = pci_std_swizzle,
.nr_controllers = 1,
+ .ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
- .scan = iop3xx_pci_scan_bus,
.map_irq = ep80219_pci_map_irq,
};
}
static struct hw_pci iq31244_pci __initdata = {
- .swizzle = pci_std_swizzle,
.nr_controllers = 1,
+ .ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
- .scan = iop3xx_pci_scan_bus,
.map_irq = iq31244_pci_map_irq,
};
}
static struct hw_pci iq80321_pci __initdata = {
- .swizzle = pci_std_swizzle,
.nr_controllers = 1,
+ .ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit_cond,
- .scan = iop3xx_pci_scan_bus,
.map_irq = iq80321_pci_map_irq,
};
}
static struct hw_pci n2100_pci __initdata = {
- .swizzle = pci_std_swizzle,
.nr_controllers = 1,
+ .ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit,
- .scan = iop3xx_pci_scan_bus,
.map_irq = n2100_pci_map_irq,
};
}
static struct hw_pci iq80331_pci __initdata = {
- .swizzle = pci_std_swizzle,
.nr_controllers = 1,
+ .ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit_cond,
- .scan = iop3xx_pci_scan_bus,
.map_irq = iq80331_pci_map_irq,
};
}
static struct hw_pci iq80332_pci __initdata = {
- .swizzle = pci_std_swizzle,
.nr_controllers = 1,
+ .ops = &iop3xx_ops,
.setup = iop3xx_pci_setup,
.preinit = iop3xx_pci_preinit_cond,
- .scan = iop3xx_pci_scan_bus,
.map_irq = iq80332_pci_map_irq,
};
.write = enp2611_pci_write_config
};
-static struct pci_bus * __init enp2611_pci_scan_bus(int nr,
- struct pci_sys_data *sys)
-{
- return pci_scan_root_bus(NULL, sys->busnr, &enp2611_pci_ops, sys,
- &sys->resources);
-}
-
static int __init enp2611_pci_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
struct hw_pci enp2611_pci __initdata = {
.nr_controllers = 1,
+ .ops = &enp2611_pci_ops,
.setup = enp2611_pci_setup,
.preinit = enp2611_pci_preinit,
- .scan = enp2611_pci_scan_bus,
.map_irq = enp2611_pci_map_irq,
};
struct pci_sys_data;
+extern struct pci_ops ixp2000_pci_ops;
u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where);
void ixp2000_pci_preinit(void);
int ixp2000_pci_setup(int, struct pci_sys_data*);
-struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*);
int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *);
int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32);
static struct hw_pci ixdp2400_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp2000_pci_ops,
.setup = ixdp2400_pci_setup,
.preinit = ixdp2400_pci_preinit,
.postinit = ixdp2400_pci_postinit,
- .scan = ixp2000_pci_scan_bus,
.map_irq = ixdp2400_pci_map_irq,
};
struct __initdata hw_pci ixdp2800_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp2000_pci_ops,
.setup = ixdp2800_pci_setup,
.preinit = ixdp2800_pci_preinit,
.postinit = ixdp2800_pci_postinit,
- .scan = ixp2000_pci_scan_bus,
.map_irq = ixdp2800_pci_map_irq,
};
struct hw_pci ixdp2x01_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp2000_pci_ops,
.setup = ixdp2x01_pci_setup,
.preinit = ixdp2x01_pci_preinit,
- .scan = ixp2000_pci_scan_bus,
.map_irq = ixdp2x01_pci_map_irq,
};
}
-static struct pci_ops ixp2000_pci_ops = {
+struct pci_ops ixp2000_pci_ops = {
.read = ixp2000_pci_read_config,
.write = ixp2000_pci_write_config
};
-struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
-{
- return pci_scan_root_bus(NULL, sysdata->busnr, &ixp2000_pci_ops,
- sysdata, &sysdata->resources);
-}
-
int ixp2000_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
{
void ixp23xx_restart(char, const char *);
int ixp23xx_pci_setup(int, struct pci_sys_data *);
void ixp23xx_pci_preinit(void);
-struct pci_bus *ixp23xx_pci_scan_bus(int, struct pci_sys_data*);
+extern struct pci_ops ixp23xx_pci_ops;
void ixp23xx_pci_slave_init(void);
extern struct sys_timer ixp23xx_timer;
struct hw_pci ixdp2351_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp23xx_pci_ops,
.preinit = ixp23xx_pci_preinit,
.setup = ixp23xx_pci_setup,
- .scan = ixp23xx_pci_scan_bus,
.map_irq = ixdp2351_map_irq,
};
.write = ixp23xx_pci_write_config,
};
-struct pci_bus *ixp23xx_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
-{
- return pci_scan_root_bus(NULL, sysdata->busnr, &ixp23xx_pci_ops,
- sysdata, &sysdata->resources);
-}
-
int ixp23xx_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
{
volatile unsigned long temp;
static struct hw_pci roadrunner_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp23xx_pci_ops,
.preinit = roadrunner_pci_preinit,
.setup = ixp23xx_pci_setup,
- .scan = ixp23xx_pci_scan_bus,
.map_irq = roadrunner_map_irq,
};
struct hw_pci avila_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp4xx_ops,
.preinit = avila_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
- .scan = ixp4xx_scan_bus,
.map_irq = avila_map_irq,
};
return 1;
}
-struct pci_bus * __devinit ixp4xx_scan_bus(int nr, struct pci_sys_data *sys)
-{
- return pci_scan_root_bus(NULL, sys->busnr, &ixp4xx_ops, sys,
- &sys->resources);
-}
-
int dma_set_coherent_mask(struct device *dev, u64 mask)
{
if (mask >= SZ_64M - 1)
struct hw_pci coyote_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp4xx_ops,
.preinit = coyote_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
- .scan = ixp4xx_scan_bus,
.map_irq = coyote_map_irq,
};
struct hw_pci __initdata dsmg600_pci = {
.nr_controllers = 1,
+ .ops = &ixp4xx_ops,
.preinit = dsmg600_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
- .scan = ixp4xx_scan_bus,
.map_irq = dsmg600_map_irq,
};
struct hw_pci fsg_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp4xx_ops,
.preinit = fsg_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
- .scan = ixp4xx_scan_bus,
.map_irq = fsg_map_irq,
};
struct hw_pci gateway7001_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp4xx_ops,
.preinit = gateway7001_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
- .scan = ixp4xx_scan_bus,
.map_irq = gateway7001_map_irq,
};
static struct hw_pci gmlr_hw_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp4xx_ops,
.preinit = gmlr_pci_preinit,
.postinit = gmlr_pci_postinit,
- .swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
- .scan = ixp4xx_scan_bus,
.map_irq = gmlr_map_irq,
};
struct hw_pci gtwx5715_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp4xx_ops,
.preinit = gtwx5715_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
- .scan = ixp4xx_scan_bus,
.map_irq = gtwx5715_map_irq,
};
extern void ixp4xx_pci_preinit(void);
struct pci_sys_data;
extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
-extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
+extern struct pci_ops ixp4xx_ops;
/*
* GPIO-functions
struct hw_pci ixdp425_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp4xx_ops,
.preinit = ixdp425_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
- .scan = ixp4xx_scan_bus,
.map_irq = ixdp425_map_irq,
};
struct hw_pci ixdpg425_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp4xx_ops,
.preinit = ixdpg425_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
- .scan = ixp4xx_scan_bus,
.map_irq = ixdpg425_map_irq,
};
struct hw_pci miccpt_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp4xx_ops,
.preinit = miccpt_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
- .scan = ixp4xx_scan_bus,
.map_irq = miccpt_map_irq,
};
struct hw_pci __initdata nas100d_pci = {
.nr_controllers = 1,
+ .ops = &ixp4xx_ops,
.preinit = nas100d_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
- .scan = ixp4xx_scan_bus,
.map_irq = nas100d_map_irq,
};
struct hw_pci __initdata nslu2_pci = {
.nr_controllers = 1,
+ .ops = &ixp4xx_ops,
.preinit = nslu2_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
- .scan = ixp4xx_scan_bus,
.map_irq = nslu2_map_irq,
};
struct hw_pci vulcan_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp4xx_ops,
.preinit = vulcan_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
- .scan = ixp4xx_scan_bus,
.map_irq = vulcan_map_irq,
};
struct hw_pci wg302v2_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ixp4xx_ops,
.preinit = wg302v2_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = ixp4xx_setup,
- .scan = ixp4xx_scan_bus,
.map_irq = wg302v2_map_irq,
};
static int pcie_port_map[2];
static int num_pcie_ports;
-static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
-{
- struct pci_sys_data *sys = bus->sysdata;
- return sys->private_data;
-}
-
static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
{
/*
static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 *val)
{
- struct pcie_port *pp = bus_to_port(bus);
+ struct pci_sys_data *sys = bus->sysdata;
+ struct pcie_port *pp = sys->private_data;
unsigned long flags;
int ret;
static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
- struct pcie_port *pp = bus_to_port(bus);
+ struct pci_sys_data *sys = bus->sysdata;
+ struct pcie_port *pp = sys->private_data;
unsigned long flags;
int ret;
static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
- struct pcie_port *pp = bus_to_port(dev->bus);
+ struct pci_sys_data *sys = dev->sysdata;
+ struct pcie_port *pp = sys->private_data;
return pp->irq;
}
static struct hw_pci kirkwood_pci __initdata = {
- .swizzle = pci_std_swizzle,
.setup = kirkwood_pcie_setup,
.scan = kirkwood_pcie_scan_bus,
.map_irq = kirkwood_pcie_map_irq,
.write = ks8695_pci_writeconfig,
};
-static struct pci_bus* __init ks8695_pci_scan_bus(int nr, struct pci_sys_data *sys)
-{
- return pci_scan_root_bus(NULL, sys->busnr, &ks8695_pci_ops, sys,
- &sys->resources);
-}
-
static struct resource pci_mem = {
.name = "PCI Memory space",
.start = KS8695_PCIMEM_PA,
static struct hw_pci ks8695_pci __initdata = {
.nr_controllers = 1,
+ .ops = &ks8695_pci_ops,
.preinit = ks8695_pci_preinit,
.setup = ks8695_pci_setup,
- .scan = ks8695_pci_scan_bus,
.postinit = NULL,
- .swizzle = pci_std_swizzle,
.map_irq = NULL,
};
return 0;
pp = &pcie_port[nr];
+ sys->private_data = pp;
pp->root_bus_nr = sys->busnr;
/*
return 1;
}
-static struct pcie_port *bus_to_port(int bus)
-{
- int i;
-
- for (i = num_pcie_ports - 1; i >= 0; i--) {
- int rbus = pcie_port[i].root_bus_nr;
- if (rbus != -1 && rbus <= bus)
- break;
- }
-
- return i >= 0 ? pcie_port + i : NULL;
-}
-
static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
{
/*
static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
int size, u32 *val)
{
- struct pcie_port *pp = bus_to_port(bus->number);
+ struct pci_sys_data *sys = bus->sysdata;
+ struct pcie_port *pp = sys->private_data;
unsigned long flags;
int ret;
static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
int where, int size, u32 val)
{
- struct pcie_port *pp = bus_to_port(bus->number);
+ struct pci_sys_data *sys = bus->sysdata;
+ struct pcie_port *pp = sys->private_data;
unsigned long flags;
int ret;
static int __init mv78xx0_pcie_map_irq(const struct pci_dev *dev, u8 slot,
u8 pin)
{
- struct pcie_port *pp = bus_to_port(dev->bus->number);
+ struct pci_sys_data *sys = dev->bus->sysdata;
+ struct pcie_port *pp = sys->private_data;
return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;
}
static struct hw_pci mv78xx0_pci __initdata = {
.nr_controllers = 8,
.preinit = mv78xx0_pcie_preinit,
- .swizzle = pci_std_swizzle,
.setup = mv78xx0_pcie_setup,
.scan = mv78xx0_pcie_scan_bus,
.map_irq = mv78xx0_pcie_map_irq,
#include <mach/mx23.h>
#include <mach/devices-common.h>
#include <mach/mxsfb.h>
+#include <linux/amba/bus.h>
-extern const struct amba_device mx23_duart_device __initconst;
-#define mx23_add_duart() \
- mxs_add_duart(&mx23_duart_device)
+static inline int mx23_add_duart(void)
+{
+ struct amba_device *d;
+
+ d = amba_ahb_device_add(NULL, "duart", MX23_DUART_BASE_ADDR, SZ_8K,
+ MX23_INT_DUART, 0, 0, 0);
+ return IS_ERR(d) ? PTR_ERR(d) : 0;
+}
extern const struct mxs_auart_data mx23_auart_data[] __initconst;
#define mx23_add_auart(id) mxs_add_auart(&mx23_auart_data[id])
#include <mach/mx28.h>
#include <mach/devices-common.h>
#include <mach/mxsfb.h>
+#include <linux/amba/bus.h>
-extern const struct amba_device mx28_duart_device __initconst;
-#define mx28_add_duart() \
- mxs_add_duart(&mx28_duart_device)
+static inline int mx28_add_duart(void)
+{
+ struct amba_device *d;
+
+ d = amba_ahb_device_add(NULL, "duart", MX28_DUART_BASE_ADDR, SZ_8K,
+ MX28_INT_DUART, 0, 0, 0);
+ return IS_ERR(d) ? PTR_ERR(d) : 0;
+}
extern const struct mxs_auart_data mx28_auart_data[] __initconst;
#define mx28_add_auart(id) mxs_add_auart(&mx28_auart_data[id])
return pdev;
}
-int __init mxs_add_amba_device(const struct amba_device *dev)
-{
- struct amba_device *adev = amba_device_alloc(dev->dev.init_name,
- dev->res.start, resource_size(&dev->res));
-
- if (!adev) {
- pr_err("%s: failed to allocate memory", __func__);
- return -ENOMEM;
- }
-
- adev->irq[0] = dev->irq[0];
- adev->irq[1] = dev->irq[1];
-
- return amba_device_add(adev, &iomem_resource);
-}
-
struct device mxs_apbh_bus = {
.init_name = "mxs_apbh",
.parent = &platform_bus,
-obj-$(CONFIG_MXS_HAVE_AMBA_DUART) += amba-duart.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_AUART) += platform-auart.o
obj-y += platform-dma.o
obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
+++ /dev/null
-/*
- * Copyright (C) 2009-2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <asm/irq.h>
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/devices-common.h>
-
-#define MXS_AMBA_DUART_DEVICE(name, soc) \
-const struct amba_device name##_device __initconst = { \
- .dev = { \
- .init_name = "duart", \
- }, \
- .res = { \
- .start = soc ## _DUART_BASE_ADDR, \
- .end = (soc ## _DUART_BASE_ADDR) + SZ_8K - 1, \
- .flags = IORESOURCE_MEM, \
- }, \
- .irq = {soc ## _INT_DUART}, \
-}
-
-#ifdef CONFIG_SOC_IMX23
-MXS_AMBA_DUART_DEVICE(mx23_duart, MX23);
-#endif
-
-#ifdef CONFIG_SOC_IMX28
-MXS_AMBA_DUART_DEVICE(mx28_duart, MX28);
-#endif
-
-int __init mxs_add_duart(const struct amba_device *dev)
-{
- return mxs_add_amba_device(dev);
-}
name, id, res, num_resources, data, size_data, 0);
}
-int __init mxs_add_amba_device(const struct amba_device *dev);
-
-/* duart */
-int __init mxs_add_duart(const struct amba_device *dev);
-
/* auart */
struct mxs_auart_data {
int id;
static struct hw_pci db88f5281_pci __initdata = {
.nr_controllers = 2,
.preinit = db88f5281_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = db88f5281_pci_map_irq,
static struct hw_pci dns323_pci __initdata = {
.nr_controllers = 2,
- .swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = dns323_pci_map_irq,
static struct hw_pci kurobox_pro_pci __initdata = {
.nr_controllers = 2,
- .swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = kurobox_pro_pci_map_irq,
static struct hw_pci mss2_pci __initdata = {
.nr_controllers = 2,
- .swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = mss2_pci_map_irq,
static struct hw_pci rd88f5181l_fxo_pci __initdata = {
.nr_controllers = 2,
- .swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = rd88f5181l_fxo_pci_map_irq,
static struct hw_pci rd88f5181l_ge_pci __initdata = {
.nr_controllers = 2,
- .swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = rd88f5181l_ge_pci_map_irq,
static struct hw_pci rd88f5182_pci __initdata = {
.nr_controllers = 2,
.preinit = rd88f5182_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = rd88f5182_pci_map_irq,
static struct hw_pci rd88f6183ap_ge_pci __initdata = {
.nr_controllers = 2,
- .swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = orion5x_pci_map_irq,
static struct hw_pci tsp2_pci __initdata = {
.nr_controllers = 2,
.preinit = tsp2_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = tsp2_pci_map_irq,
static struct hw_pci qnap_ts209_pci __initdata = {
.nr_controllers = 2,
.preinit = qnap_ts209_pci_preinit,
- .swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = qnap_ts209_pci_map_irq,
static struct hw_pci qnap_ts409_pci __initdata = {
.nr_controllers = 2,
- .swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = qnap_ts409_pci_map_irq,
static struct hw_pci wnr854t_pci __initdata = {
.nr_controllers = 2,
- .swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = wnr854t_pci_map_irq,
static struct hw_pci wrt350n_v2_pci __initdata = {
.nr_controllers = 2,
- .swizzle = pci_std_swizzle,
.setup = orion5x_pci_sys_setup,
.scan = orion5x_pci_sys_scan_bus,
.map_irq = wrt350n_v2_pci_map_irq,
}
static struct hw_pci cmx2xx_pci __initdata = {
- .swizzle = pci_std_swizzle,
.map_irq = cmx2xx_pci_map_irq,
.nr_controllers = 1,
+ .ops = &it8152_ops,
.setup = it8152_pci_setup,
- .scan = it8152_pci_scan_bus,
.preinit = cmx2xx_pci_preinit,
};
return NANOENGINE_IRQ_GPIO_PCI;
}
-struct pci_bus * __init pci_nanoengine_scan_bus(int nr, struct pci_sys_data *sys)
-{
- return pci_scan_root_bus(NULL, sys->busnr, &pci_nano_ops, sys,
- &sys->resources);
-}
-
static struct resource pci_io_ports =
DEFINE_RES_IO_NAMED(0x400, 0x400, "PCI IO");
static struct hw_pci nanoengine_pci __initdata = {
.map_irq = pci_nanoengine_map_irq,
.nr_controllers = 1,
- .scan = pci_nanoengine_scan_bus,
+ .ops = &pci_nano_ops,
.setup = pci_nanoengine_setup,
};
static struct hw_pci shark_pci __initdata = {
.setup = via82c505_setup,
- .swizzle = pci_std_swizzle,
.map_irq = shark_map_irq,
.nr_controllers = 1,
- .scan = via82c505_scan_bus,
+ .ops = &via82c505_ops,
.preinit = via82c505_preinit,
};
.nr_controllers = 2,
.setup = tegra_pcie_setup,
.scan = tegra_pcie_scan_bus,
- .swizzle = pci_std_swizzle,
.map_irq = tegra_pcie_map_irq,
};
}
/*
- * read_persistent_clock - Return time from a persistent clock.
+ * tegra_read_persistent_clock - Return time from a persistent clock.
*
* Reads the time from a source which isn't disabled during PM, the
* 32k sync timer. Convert the cycles elapsed since last read into
* tegra_rtc driver could be executing to avoid race conditions
* on the RTC shadow register
*/
-void read_persistent_clock(struct timespec *ts)
+static void tegra_read_persistent_clock(struct timespec *ts)
{
u64 delta;
struct timespec *tsp = &persistent_ts;
tegra_clockevent.irq = tegra_timer_irq.irq;
clockevents_register_device(&tegra_clockevent);
tegra_twd_init();
+ register_persistent_clock(NULL, tegra_read_persistent_clock);
}
struct sys_timer tegra_timer = {
#include <linux/irq.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
#include <plat/gpio-nomadik.h>
#include "devices-common.h"
-struct amba_device *
-dbx500_add_amba_device(struct device *parent, const char *name,
- resource_size_t base, int irq, void *pdata,
- unsigned int periphid)
-{
- struct amba_device *dev;
- int ret;
-
- dev = amba_device_alloc(name, base, SZ_4K);
- if (!dev)
- return ERR_PTR(-ENOMEM);
-
- dev->dma_mask = DMA_BIT_MASK(32);
- dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
-
- dev->irq[0] = irq;
-
- dev->periphid = periphid;
-
- dev->dev.platform_data = pdata;
-
- dev->dev.parent = parent;
-
- ret = amba_device_add(dev, &iomem_resource);
- if (ret) {
- amba_device_put(dev);
- return ERR_PTR(ret);
- }
-
- return dev;
-}
-
static struct platform_device *
dbx500_add_gpio(struct device *parent, int id, resource_size_t addr, int irq,
struct nmk_gpio_platform_data *pdata)
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/sys_soc.h>
+#include <linux/amba/bus.h>
#include <plat/i2c.h>
-extern struct amba_device *
-dbx500_add_amba_device(struct device *parent, const char *name,
- resource_size_t base, int irq, void *pdata,
- unsigned int periphid);
-
struct spi_master_cntlr;
static inline struct amba_device *
resource_size_t base, int irq,
struct spi_master_cntlr *pdata)
{
- return dbx500_add_amba_device(parent, name, base, irq,
- pdata, 0);
+ return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0,
+ pdata, 0);
}
static inline struct amba_device *
int irq, struct spi_master_cntlr *pdata,
u32 periphid)
{
- return dbx500_add_amba_device(parent, name, base, irq,
- pdata, periphid);
+ return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0,
+ pdata, periphid);
}
struct mmci_platform_data;
dbx500_add_sdi(struct device *parent, const char *name, resource_size_t base,
int irq, struct mmci_platform_data *pdata, u32 periphid)
{
- return dbx500_add_amba_device(parent, name, base, irq,
- pdata, periphid);
+ return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0,
+ pdata, periphid);
}
struct amba_pl011_data;
dbx500_add_uart(struct device *parent, const char *name, resource_size_t base,
int irq, struct amba_pl011_data *pdata)
{
- return dbx500_add_amba_device(parent, name, base, irq, pdata, 0);
+ return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0);
}
struct nmk_i2c_controller;
static inline struct amba_device *
dbx500_add_rtc(struct device *parent, resource_size_t base, int irq)
{
- return dbx500_add_amba_device(parent, "rtc-pl031", base, irq, NULL, 0);
+ return amba_apb_device_add(parent, "rtc-pl031", base, SZ_4K, irq,
+ 0, NULL, 0);
}
struct nmk_gpio_platform_data;
db8500_add_ssp(struct device *parent, const char *name, resource_size_t base,
int irq, struct pl022_ssp_controller *pdata)
{
- return dbx500_add_amba_device(parent, name, base, irq, pdata, 0);
+ return amba_ahb_device_add(parent, name, base, SZ_4K, irq, 0, pdata, 0);
}
#define VA_VIC_BASE __io_address(VERSATILE_VIC_BASE)
#define VA_SIC_BASE __io_address(VERSATILE_SIC_BASE)
-static struct fpga_irq_data sic_irq = {
- .base = VA_SIC_BASE,
- .irq_start = IRQ_SIC_START,
- .chip.name = "SIC",
-};
-
#if 1
#define IRQ_MMCI0A IRQ_VICSOURCE22
#define IRQ_AACI IRQ_VICSOURCE24
writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR);
- fpga_irq_init(IRQ_VICSOURCE31, ~PIC_MASK, &sic_irq);
- irq_domain_generate_simple(sic_of_match, VERSATILE_SIC_BASE, IRQ_SIC_START);
+ np = of_find_matching_node_by_address(NULL, sic_of_match,
+ VERSATILE_SIC_BASE);
+
+ fpga_irq_init(VA_SIC_BASE, "SIC", IRQ_SIC_START,
+ IRQ_VICSOURCE31, ~PIC_MASK, np);
/*
* Interrupts on secondary controller from 0 to 8 are routed to
* having a specific name.
*/
struct of_dev_auxdata versatile_auxdata_lookup[] __initdata = {
- OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", NULL),
+ OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI0_BASE, "fpga:05", &mmc0_plat_data),
OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI0_BASE, "fpga:06", NULL),
OF_DEV_AUXDATA("arm,primecell", VERSATILE_KMI1_BASE, "fpga:07", NULL),
OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART3_BASE, "fpga:09", NULL),
+ /* FIXME: this is buggy, the platform data is needed for this MMC instance too */
OF_DEV_AUXDATA("arm,primecell", VERSATILE_MMCI1_BASE, "fpga:0b", NULL),
OF_DEV_AUXDATA("arm,primecell", VERSATILE_CLCD_BASE, "dev:20", &clcd_plat_data),
OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART0_BASE, "dev:f1", NULL),
OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART1_BASE, "dev:f2", NULL),
OF_DEV_AUXDATA("arm,primecell", VERSATILE_UART2_BASE, "dev:f3", NULL),
- OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", NULL),
+ OF_DEV_AUXDATA("arm,primecell", VERSATILE_SSP_BASE, "dev:f4", &ssp0_plat_data),
#if 0
/*
}
-struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
-{
- return pci_scan_root_bus(NULL, sys->busnr, &pci_versatile_ops, sys,
- &sys->resources);
-}
-
void __init pci_versatile_preinit(void)
{
pcibios_min_io = 0x44000000;
* 26 1 29
* 27 1 30
*/
- irq = 27 + ((slot + pin - 1) & 3);
-
- printk("PCI map irq: slot %d, pin %d, devslot %d, irq: %d\n",slot,pin,devslot,irq);
+ irq = 27 + ((slot - 24 + pin - 1) & 3);
return irq;
}
static struct hw_pci versatile_pci __initdata = {
- .swizzle = NULL,
.map_irq = versatile_map_irq,
.nr_controllers = 1,
+ .ops = &pci_versatile_ops,
.setup = pci_versatile_setup,
- .scan = pci_versatile_scan_bus,
.preinit = pci_versatile_preinit,
};
#include <linux/clkdev.h>
#include <linux/mtd/physmap.h>
+#include <asm/arch_timer.h>
#include <asm/mach-types.h>
#include <asm/sizes.h>
+#include <asm/smp_twd.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
}
clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
- versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
}
static struct of_device_id vexpress_irq_match[] __initdata = {
return;
node = of_find_node_by_path(path);
v2m_sp804_init(of_iomap(node, 0), irq_of_parse_and_map(node, 0));
+ if (arch_timer_of_register() != 0)
+ twd_local_timer_of_register();
+
+ if (arch_timer_sched_clock_init() != 0)
+ versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
}
static struct sys_timer v2m_dt_timer = {
# which CPUs we support in the kernel image, and the compiler instruction
# optimiser behaviour.
-# ARM610
-config CPU_ARM610
- bool "Support ARM610 processor" if ARCH_RPC
- select CPU_32v3
- select CPU_CACHE_V3
- select CPU_CACHE_VIVT
- select CPU_CP15_MMU
- select CPU_COPY_V3 if MMU
- select CPU_TLB_V3 if MMU
- select CPU_PABRT_LEGACY
- help
- The ARM610 is the successor to the ARM3 processor
- and was produced by VLSI Technology Inc.
-
- Say Y if you want support for the ARM610 processor.
- Otherwise, say N.
-
# ARM7TDMI
config CPU_ARM7TDMI
bool "Support ARM7TDMI processor"
Say Y if you want support for the ARM7TDMI processor.
Otherwise, say N.
-# ARM710
-config CPU_ARM710
- bool "Support ARM710 processor" if ARCH_RPC
- select CPU_32v3
- select CPU_CACHE_V3
- select CPU_CACHE_VIVT
- select CPU_CP15_MMU
- select CPU_COPY_V3 if MMU
- select CPU_TLB_V3 if MMU
- select CPU_PABRT_LEGACY
- help
- A 32-bit RISC microprocessor based on the ARM7 processor core
- designed by Advanced RISC Machines Ltd. The ARM710 is the
- successor to the ARM610 processor. It was released in
- July 1994 by VLSI Technology Inc.
-
- Say Y if you want support for the ARM710 processor.
- Otherwise, say N.
-
# ARM720T
config CPU_ARM720T
bool "Support ARM720T processor" if ARCH_INTEGRATOR
if MMU
# The copy-page model
-config CPU_COPY_V3
- bool
-
config CPU_COPY_V4WT
bool
bool
# This selects the TLB model
-config CPU_TLB_V3
- bool
- help
- ARM Architecture Version 3 TLB.
-
config CPU_TLB_V4WT
bool
help
config CPU_ICACHE_DISABLE
bool "Disable I-Cache (I-bit)"
- depends on CPU_CP15 && !(CPU_ARM610 || CPU_ARM710 || CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
+ depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
help
Say Y here to disable the processor instruction cache. Unless
you have a reason not to or are unsure, say N.
AFLAGS_cache-v6.o :=-Wa,-march=armv6
AFLAGS_cache-v7.o :=-Wa,-march=armv7-a
-obj-$(CONFIG_CPU_COPY_V3) += copypage-v3.o
obj-$(CONFIG_CPU_COPY_V4WT) += copypage-v4wt.o
obj-$(CONFIG_CPU_COPY_V4WB) += copypage-v4wb.o
obj-$(CONFIG_CPU_COPY_FEROCEON) += copypage-feroceon.o
obj-$(CONFIG_CPU_XSC3) += copypage-xsc3.o
obj-$(CONFIG_CPU_COPY_FA) += copypage-fa.o
-obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o
obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o
obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o
obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o
AFLAGS_tlb-v6.o :=-Wa,-march=armv6
AFLAGS_tlb-v7.o :=-Wa,-march=armv7-a
-obj-$(CONFIG_CPU_ARM610) += proc-arm6_7.o
-obj-$(CONFIG_CPU_ARM710) += proc-arm6_7.o
obj-$(CONFIG_CPU_ARM7TDMI) += proc-arm7tdmi.o
obj-$(CONFIG_CPU_ARM720T) += proc-arm720.o
obj-$(CONFIG_CPU_ARM740T) += proc-arm740.o
* - end - virtual end address
*/
ENTRY(v3_coherent_user_range)
+ mov r0, #0
mov pc, lr
/*
* - end - virtual end address
*/
ENTRY(v4_coherent_user_range)
+ mov r0, #0
mov pc, lr
/*
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
- mov ip, #0
- mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
- mcr p15, 0, ip, c7, c10, 4 @ drain WB
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mcr p15, 0, r0, c7, c10, 4 @ drain WB
mov pc, lr
add r0, r0, #CACHE_DLINESIZE
cmp r0, r1
blo 1b
+ mov r0, #0
mov pc, lr
/*
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
+#include <asm/errno.h>
#include <asm/unwind.h>
#include "proc-macros.S"
1:
USER( mcr p15, 0, r0, c7, c10, 1 ) @ clean D line
add r0, r0, #CACHE_LINE_SIZE
-2:
cmp r0, r1
blo 1b
#endif
/*
* Fault handling for the cache operation above. If the virtual address in r0
- * isn't mapped, just try the next page.
+ * isn't mapped, fail with -EFAULT.
*/
9001:
- mov r0, r0, lsr #12
- mov r0, r0, lsl #12
- add r0, r0, #4096
- b 2b
+ mov r0, #-EFAULT
+ mov pc, lr
UNWIND(.fnend )
ENDPROC(v6_coherent_user_range)
ENDPROC(v6_coherent_kern_range)
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
+#include <asm/errno.h>
#include <asm/unwind.h>
#include "proc-macros.S"
add r12, r12, r2
cmp r12, r1
blo 2b
-3:
mov r0, #0
ALT_SMP(mcr p15, 0, r0, c7, c1, 6) @ invalidate BTB Inner Shareable
ALT_UP(mcr p15, 0, r0, c7, c5, 6) @ invalidate BTB
/*
* Fault handling for the cache operation above. If the virtual address in r0
- * isn't mapped, just try the next page.
+ * isn't mapped, fail with -EFAULT.
*/
9001:
- mov r12, r12, lsr #12
- mov r12, r12, lsl #12
- add r12, r12, #4096
- b 3b
+ mov r0, #-EFAULT
+ mov pc, lr
UNWIND(.fnend )
ENDPROC(v7_coherent_kern_range)
ENDPROC(v7_coherent_user_range)
static DEFINE_RAW_SPINLOCK(cpu_asid_lock);
unsigned int cpu_last_asid = ASID_FIRST_VERSION;
-#ifdef CONFIG_SMP
-DEFINE_PER_CPU(struct mm_struct *, current_mm);
-#endif
#ifdef CONFIG_ARM_LPAE
-#define cpu_set_asid(asid) { \
- unsigned long ttbl, ttbh; \
- asm volatile( \
- " mrrc p15, 0, %0, %1, c2 @ read TTBR0\n" \
- " mov %1, %2, lsl #(48 - 32) @ set ASID\n" \
- " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n" \
- : "=&r" (ttbl), "=&r" (ttbh) \
- : "r" (asid & ~ASID_MASK)); \
+void cpu_set_reserved_ttbr0(void)
+{
+ unsigned long ttbl = __pa(swapper_pg_dir);
+ unsigned long ttbh = 0;
+
+ /*
+ * Set TTBR0 to swapper_pg_dir which contains only global entries. The
+ * ASID is set to 0.
+ */
+ asm volatile(
+ " mcrr p15, 0, %0, %1, c2 @ set TTBR0\n"
+ :
+ : "r" (ttbl), "r" (ttbh));
+ isb();
}
#else
-#define cpu_set_asid(asid) \
- asm(" mcr p15, 0, %0, c13, c0, 1\n" : : "r" (asid))
+void cpu_set_reserved_ttbr0(void)
+{
+ u32 ttb;
+ /* Copy TTBR1 into TTBR0 */
+ asm volatile(
+ " mrc p15, 0, %0, c2, c0, 1 @ read TTBR1\n"
+ " mcr p15, 0, %0, c2, c0, 0 @ set TTBR0\n"
+ : "=r" (ttb));
+ isb();
+}
#endif
/*
* We fork()ed a process, and we need a new context for the child
- * to run in. We reserve version 0 for initial tasks so we will
- * always allocate an ASID. The ASID 0 is reserved for the TTBR
- * register changing sequence.
+ * to run in.
*/
void __init_new_context(struct task_struct *tsk, struct mm_struct *mm)
{
static void flush_context(void)
{
- /* set the reserved ASID before flushing the TLB */
- cpu_set_asid(0);
- isb();
+ cpu_set_reserved_ttbr0();
local_flush_tlb_all();
if (icache_is_vivt_asid_tagged()) {
__flush_icache_all();
{
unsigned int asid;
unsigned int cpu = smp_processor_id();
- struct mm_struct *mm = per_cpu(current_mm, cpu);
-
- /*
- * Check if a current_mm was set on this CPU as it might still
- * be in the early booting stages and using the reserved ASID.
- */
- if (!mm)
- return;
+ struct mm_struct *mm = current->active_mm;
smp_rmb();
asid = cpu_last_asid + cpu + 1;
set_mm_context(mm, asid);
/* set the new ASID */
- cpu_set_asid(mm->context.id);
- isb();
+ cpu_switch_mm(mm->pgd, mm);
}
#else
+++ /dev/null
-/*
- * linux/arch/arm/mm/copypage-v3.c
- *
- * Copyright (C) 1995-1999 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/init.h>
-#include <linux/highmem.h>
-
-/*
- * ARMv3 optimised copy_user_highpage
- *
- * FIXME: do we need to handle cache stuff...
- */
-static void __naked
-v3_copy_user_page(void *kto, const void *kfrom)
-{
- asm("\n\
- stmfd sp!, {r4, lr} @ 2\n\
- mov r2, %2 @ 1\n\
- ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
-1: stmia %1!, {r3, r4, ip, lr} @ 4\n\
- ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
- stmia %1!, {r3, r4, ip, lr} @ 4\n\
- ldmia %0!, {r3, r4, ip, lr} @ 4+1\n\
- stmia %1!, {r3, r4, ip, lr} @ 4\n\
- ldmia %0!, {r3, r4, ip, lr} @ 4\n\
- subs r2, r2, #1 @ 1\n\
- stmia %1!, {r3, r4, ip, lr} @ 4\n\
- ldmneia %0!, {r3, r4, ip, lr} @ 4\n\
- bne 1b @ 1\n\
- ldmfd sp!, {r4, pc} @ 3"
- :
- : "r" (kfrom), "r" (kto), "I" (PAGE_SIZE / 64));
-}
-
-void v3_copy_user_highpage(struct page *to, struct page *from,
- unsigned long vaddr, struct vm_area_struct *vma)
-{
- void *kto, *kfrom;
-
- kto = kmap_atomic(to);
- kfrom = kmap_atomic(from);
- v3_copy_user_page(kto, kfrom);
- kunmap_atomic(kfrom);
- kunmap_atomic(kto);
-}
-
-/*
- * ARMv3 optimised clear_user_page
- *
- * FIXME: do we need to handle cache stuff...
- */
-void v3_clear_user_highpage(struct page *page, unsigned long vaddr)
-{
- void *ptr, *kaddr = kmap_atomic(page);
- asm volatile("\n\
- mov r1, %2 @ 1\n\
- mov r2, #0 @ 1\n\
- mov r3, #0 @ 1\n\
- mov ip, #0 @ 1\n\
- mov lr, #0 @ 1\n\
-1: stmia %0!, {r2, r3, ip, lr} @ 4\n\
- stmia %0!, {r2, r3, ip, lr} @ 4\n\
- stmia %0!, {r2, r3, ip, lr} @ 4\n\
- stmia %0!, {r2, r3, ip, lr} @ 4\n\
- subs r1, r1, #1 @ 1\n\
- bne 1b @ 1"
- : "=r" (ptr)
- : "0" (kaddr), "I" (PAGE_SIZE / 64)
- : "r1", "r2", "r3", "ip", "lr");
- kunmap_atomic(kaddr);
-}
-
-struct cpu_user_fns v3_user_fns __initdata = {
- .cpu_clear_user_highpage = v3_clear_user_highpage,
- .cpu_copy_user_highpage = v3_copy_user_highpage,
-};
index = pgd_index(addr);
- /*
- * FIXME: CP15 C1 is write only on ARMv3 architectures.
- */
pgd = cpu_get_pgd() + index;
pgd_k = init_mm.pgd + index;
cmp r0, r1
blo 1b
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+ mov r0, #0
mov pc, lr
/*
cmp r0, r1
blo 1b
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+ mov r0, #0
mov pc, lr
/*
cmp r0, r1
blo 1b
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+ mov r0, #0
mov pc, lr
/*
cmp r0, r1
blo 1b
mcr p15, 0, ip, c7, c10, 4 @ drain WB
+ mov r0, #0
mov pc, lr
/*
+++ /dev/null
-/*
- * linux/arch/arm/mm/proc-arm6,7.S
- *
- * Copyright (C) 1997-2000 Russell King
- * hacked for non-paged-MM by Hyok S. Choi, 2003.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * These are the low level assembler for performing cache and TLB
- * functions on the ARM610 & ARM710.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/assembler.h>
-#include <asm/asm-offsets.h>
-#include <asm/hwcap.h>
-#include <asm/pgtable-hwdef.h>
-#include <asm/pgtable.h>
-#include <asm/ptrace.h>
-
-#include "proc-macros.S"
-
-ENTRY(cpu_arm6_dcache_clean_area)
-ENTRY(cpu_arm7_dcache_clean_area)
- mov pc, lr
-
-/*
- * Function: arm6_7_data_abort ()
- *
- * Params : r2 = pt_regs
- * : r4 = aborted context pc
- * : r5 = aborted context psr
- *
- * Purpose : obtain information about current aborted instruction
- *
- * Returns : r4-r5, r10-r11, r13 preserved
- */
-
-ENTRY(cpu_arm7_data_abort)
- mrc p15, 0, r1, c5, c0, 0 @ get FSR
- mrc p15, 0, r0, c6, c0, 0 @ get FAR
- ldr r8, [r4] @ read arm instruction
- tst r8, #1 << 20 @ L = 0 -> write?
- orreq r1, r1, #1 << 11 @ yes.
- and r7, r8, #15 << 24
- add pc, pc, r7, lsr #22 @ Now branch to the relevant processing routine
- nop
-
-/* 0 */ b .data_unknown
-/* 1 */ b do_DataAbort @ swp
-/* 2 */ b .data_unknown
-/* 3 */ b .data_unknown
-/* 4 */ b .data_arm_lateldrpostconst @ ldr rd, [rn], #m
-/* 5 */ b .data_arm_lateldrpreconst @ ldr rd, [rn, #m]
-/* 6 */ b .data_arm_lateldrpostreg @ ldr rd, [rn], rm
-/* 7 */ b .data_arm_lateldrprereg @ ldr rd, [rn, rm]
-/* 8 */ b .data_arm_ldmstm @ ldm*a rn, <rlist>
-/* 9 */ b .data_arm_ldmstm @ ldm*b rn, <rlist>
-/* a */ b .data_unknown
-/* b */ b .data_unknown
-/* c */ b do_DataAbort @ ldc rd, [rn], #m @ Same as ldr rd, [rn], #m
-/* d */ b do_DataAbort @ ldc rd, [rn, #m]
-/* e */ b .data_unknown
-/* f */
-.data_unknown: @ Part of jumptable
- mov r0, r4
- mov r1, r8
- b baddataabort
-
-ENTRY(cpu_arm6_data_abort)
- mrc p15, 0, r1, c5, c0, 0 @ get FSR
- mrc p15, 0, r0, c6, c0, 0 @ get FAR
- ldr r8, [r4] @ read arm instruction
- tst r8, #1 << 20 @ L = 0 -> write?
- orreq r1, r1, #1 << 11 @ yes.
- and r7, r8, #14 << 24
- teq r7, #8 << 24 @ was it ldm/stm
- bne do_DataAbort
-
-.data_arm_ldmstm:
- tst r8, #1 << 21 @ check writeback bit
- beq do_DataAbort @ no writeback -> no fixup
- mov r7, #0x11
- orr r7, r7, #0x1100
- and r6, r8, r7
- and r9, r8, r7, lsl #1
- add r6, r6, r9, lsr #1
- and r9, r8, r7, lsl #2
- add r6, r6, r9, lsr #2
- and r9, r8, r7, lsl #3
- add r6, r6, r9, lsr #3
- add r6, r6, r6, lsr #8
- add r6, r6, r6, lsr #4
- and r6, r6, #15 @ r6 = no. of registers to transfer.
- and r9, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
- tst r8, #1 << 23 @ Check U bit
- subne r7, r7, r6, lsl #2 @ Undo increment
- addeq r7, r7, r6, lsl #2 @ Undo decrement
- str r7, [r2, r9, lsr #14] @ Put register 'Rn'
- b do_DataAbort
-
-.data_arm_apply_r6_and_rn:
- and r9, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
- tst r8, #1 << 23 @ Check U bit
- subne r7, r7, r6 @ Undo incrmenet
- addeq r7, r7, r6 @ Undo decrement
- str r7, [r2, r9, lsr #14] @ Put register 'Rn'
- b do_DataAbort
-
-.data_arm_lateldrpreconst:
- tst r8, #1 << 21 @ check writeback bit
- beq do_DataAbort @ no writeback -> no fixup
-.data_arm_lateldrpostconst:
- movs r6, r8, lsl #20 @ Get offset
- beq do_DataAbort @ zero -> no fixup
- and r9, r8, #15 << 16 @ Extract 'n' from instruction
- ldr r7, [r2, r9, lsr #14] @ Get register 'Rn'
- tst r8, #1 << 23 @ Check U bit
- subne r7, r7, r6, lsr #20 @ Undo increment
- addeq r7, r7, r6, lsr #20 @ Undo decrement
- str r7, [r2, r9, lsr #14] @ Put register 'Rn'
- b do_DataAbort
-
-.data_arm_lateldrprereg:
- tst r8, #1 << 21 @ check writeback bit
- beq do_DataAbort @ no writeback -> no fixup
-.data_arm_lateldrpostreg:
- and r7, r8, #15 @ Extract 'm' from instruction
- ldr r6, [r2, r7, lsl #2] @ Get register 'Rm'
- mov r9, r8, lsr #7 @ get shift count
- ands r9, r9, #31
- and r7, r8, #0x70 @ get shift type
- orreq r7, r7, #8 @ shift count = 0
- add pc, pc, r7
- nop
-
- mov r6, r6, lsl r9 @ 0: LSL #!0
- b .data_arm_apply_r6_and_rn
- b .data_arm_apply_r6_and_rn @ 1: LSL #0
- nop
- b .data_unknown @ 2: MUL?
- nop
- b .data_unknown @ 3: MUL?
- nop
- mov r6, r6, lsr r9 @ 4: LSR #!0
- b .data_arm_apply_r6_and_rn
- mov r6, r6, lsr #32 @ 5: LSR #32
- b .data_arm_apply_r6_and_rn
- b .data_unknown @ 6: MUL?
- nop
- b .data_unknown @ 7: MUL?
- nop
- mov r6, r6, asr r9 @ 8: ASR #!0
- b .data_arm_apply_r6_and_rn
- mov r6, r6, asr #32 @ 9: ASR #32
- b .data_arm_apply_r6_and_rn
- b .data_unknown @ A: MUL?
- nop
- b .data_unknown @ B: MUL?
- nop
- mov r6, r6, ror r9 @ C: ROR #!0
- b .data_arm_apply_r6_and_rn
- mov r6, r6, rrx @ D: RRX
- b .data_arm_apply_r6_and_rn
- b .data_unknown @ E: MUL?
- nop
- b .data_unknown @ F: MUL?
-
-/*
- * Function: arm6_7_proc_init (void)
- * : arm6_7_proc_fin (void)
- *
- * Notes : This processor does not require these
- */
-ENTRY(cpu_arm6_proc_init)
-ENTRY(cpu_arm7_proc_init)
- mov pc, lr
-
-ENTRY(cpu_arm6_proc_fin)
-ENTRY(cpu_arm7_proc_fin)
- mov r0, #0x31 @ ....S..DP...M
- mcr p15, 0, r0, c1, c0, 0 @ disable caches
- mov pc, lr
-
-ENTRY(cpu_arm6_do_idle)
-ENTRY(cpu_arm7_do_idle)
- mov pc, lr
-
-/*
- * Function: arm6_7_switch_mm(unsigned long pgd_phys)
- * Params : pgd_phys Physical address of page table
- * Purpose : Perform a task switch, saving the old processes state, and restoring
- * the new.
- */
-ENTRY(cpu_arm6_switch_mm)
-ENTRY(cpu_arm7_switch_mm)
-#ifdef CONFIG_MMU
- mov r1, #0
- mcr p15, 0, r1, c7, c0, 0 @ flush cache
- mcr p15, 0, r0, c2, c0, 0 @ update page table ptr
- mcr p15, 0, r1, c5, c0, 0 @ flush TLBs
-#endif
- mov pc, lr
-
-/*
- * Function: arm6_7_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext)
- * Params : r0 = Address to set
- * : r1 = value to set
- * Purpose : Set a PTE and flush it out of any WB cache
- */
- .align 5
-ENTRY(cpu_arm6_set_pte_ext)
-ENTRY(cpu_arm7_set_pte_ext)
-#ifdef CONFIG_MMU
- armv3_set_pte_ext wc_disable=0
-#endif /* CONFIG_MMU */
- mov pc, lr
-
-/*
- * Function: _arm6_7_reset
- * Params : r0 = address to jump to
- * Notes : This sets up everything for a reset
- */
- .pushsection .idmap.text, "ax"
-ENTRY(cpu_arm6_reset)
-ENTRY(cpu_arm7_reset)
- mov r1, #0
- mcr p15, 0, r1, c7, c0, 0 @ flush cache
-#ifdef CONFIG_MMU
- mcr p15, 0, r1, c5, c0, 0 @ flush TLB
-#endif
- mov r1, #0x30
- mcr p15, 0, r1, c1, c0, 0 @ turn off MMU etc
- mov pc, r0
-ENDPROC(cpu_arm6_reset)
-ENDPROC(cpu_arm7_reset)
- .popsection
-
- __CPUINIT
-
- .type __arm6_setup, #function
-__arm6_setup: mov r0, #0
- mcr p15, 0, r0, c7, c0 @ flush caches on v3
-#ifdef CONFIG_MMU
- mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
- mov r0, #0x3d @ . ..RS BLDP WCAM
- orr r0, r0, #0x100 @ . ..01 0011 1101
-#else
- mov r0, #0x3c @ . ..RS BLDP WCA.
-#endif
- mov pc, lr
- .size __arm6_setup, . - __arm6_setup
-
- .type __arm7_setup, #function
-__arm7_setup: mov r0, #0
- mcr p15, 0, r0, c7, c0 @ flush caches on v3
-#ifdef CONFIG_MMU
- mcr p15, 0, r0, c5, c0 @ flush TLBs on v3
- mcr p15, 0, r0, c3, c0 @ load domain access register
- mov r0, #0x7d @ . ..RS BLDP WCAM
- orr r0, r0, #0x100 @ . ..01 0111 1101
-#else
- mov r0, #0x7c @ . ..RS BLDP WCA.
-#endif
- mov pc, lr
- .size __arm7_setup, . - __arm7_setup
-
- __INITDATA
-
- @ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
- define_processor_functions arm6, dabort=cpu_arm6_data_abort, pabort=legacy_pabort
- define_processor_functions arm7, dabort=cpu_arm7_data_abort, pabort=legacy_pabort
-
- .section ".rodata"
-
- string cpu_arch_name, "armv3"
- string cpu_elf_name, "v3"
- string cpu_arm6_name, "ARM6"
- string cpu_arm610_name, "ARM610"
- string cpu_arm7_name, "ARM7"
- string cpu_arm710_name, "ARM710"
-
- .align
-
- .section ".proc.info.init", #alloc, #execinstr
-
-.macro arm67_proc_info name:req, cpu_val:req, cpu_mask:req, cpu_name:req, \
- cpu_mm_mmu_flags:req, cpu_flush:req, cpu_proc_funcs:req
- .type __\name\()_proc_info, #object
-__\name\()_proc_info:
- .long \cpu_val
- .long \cpu_mask
- .long \cpu_mm_mmu_flags
- .long PMD_TYPE_SECT | \
- PMD_BIT4 | \
- PMD_SECT_AP_WRITE | \
- PMD_SECT_AP_READ
- b \cpu_flush
- .long cpu_arch_name
- .long cpu_elf_name
- .long HWCAP_SWP | HWCAP_26BIT
- .long \cpu_name
- .long \cpu_proc_funcs
- .long v3_tlb_fns
- .long v3_user_fns
- .long v3_cache_fns
- .size __\name\()_proc_info, . - __\name\()_proc_info
-.endm
-
- arm67_proc_info arm6, 0x41560600, 0xfffffff0, cpu_arm6_name, \
- 0x00000c1e, __arm6_setup, arm6_processor_functions
- arm67_proc_info arm610, 0x41560610, 0xfffffff0, cpu_arm610_name, \
- 0x00000c1e, __arm6_setup, arm6_processor_functions
- arm67_proc_info arm7, 0x41007000, 0xffffff00, cpu_arm7_name, \
- 0x00000c1e, __arm7_setup, arm7_processor_functions
- arm67_proc_info arm710, 0x41007100, 0xfff8ff00, cpu_arm710_name, \
- PMD_TYPE_SECT | \
- PMD_SECT_BUFFERABLE | \
- PMD_SECT_CACHEABLE | \
- PMD_BIT4 | \
- PMD_SECT_AP_WRITE | \
- PMD_SECT_AP_READ, \
- __arm7_setup, arm7_processor_functions
cmp r0, r1
blo 1b
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+ mov r0, #0
mov pc, lr
/*
cmp r0, r1
blo 1b
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+ mov r0, #0
mov pc, lr
/*
cmp r0, r1
blo 1b
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+ mov r0, #0
mov pc, lr
/*
cmp r0, r1
blo 1b
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+ mov r0, #0
mov pc, lr
/*
* - size - region size
*/
ENTRY(arm940_flush_kern_dcache_area)
- mov ip, #0
+ mov r0, #0
mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
bcs 2b @ entries 63 to 0
subs r1, r1, #1 << 4
bcs 1b @ segments 7 to 0
- mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
- mcr p15, 0, ip, c7, c10, 4 @ drain WB
+ mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
+ mcr p15, 0, r0, c7, c10, 4 @ drain WB
mov pc, lr
/*
cmp r0, r1
blo 1b
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+ mov r0, #0
mov pc, lr
/*
cmp r0, r1
blo 1b
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+ mov r0, #0
mov pc, lr
/*
cmp r0, r1
blo 1b
mcr p15, 0, r0, c7, c10, 4 @ drain WB
+ mov r0, #0
mov pc, lr
/*
#ifdef CONFIG_ARM_ERRATA_430973
mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
#endif
-#ifdef CONFIG_ARM_ERRATA_754322
- dsb
-#endif
- mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
- isb
-1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
- isb
#ifdef CONFIG_ARM_ERRATA_754322
dsb
#endif
mcr p15, 0, r1, c13, c0, 1 @ set context ID
isb
+ mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
+ isb
#endif
mov pc, lr
ENDPROC(cpu_v7_switch_mm)
+++ /dev/null
-/*
- * linux/arch/arm/mm/tlbv3.S
- *
- * Copyright (C) 1997-2002 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * ARM architecture version 3 TLB handling functions.
- *
- * Processors: ARM610, ARM710.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-#include <asm/asm-offsets.h>
-#include <asm/tlbflush.h>
-#include "proc-macros.S"
-
- .align 5
-/*
- * v3_flush_user_tlb_range(start, end, mm)
- *
- * Invalidate a range of TLB entries in the specified address space.
- *
- * - start - range start address
- * - end - range end address
- * - mm - mm_struct describing address space
- */
- .align 5
-ENTRY(v3_flush_user_tlb_range)
- vma_vm_mm r2, r2
- act_mm r3 @ get current->active_mm
- teq r2, r3 @ == mm ?
- movne pc, lr @ no, we dont do anything
-ENTRY(v3_flush_kern_tlb_range)
- bic r0, r0, #0x0ff
- bic r0, r0, #0xf00
-1: mcr p15, 0, r0, c6, c0, 0 @ invalidate TLB entry
- add r0, r0, #PAGE_SZ
- cmp r0, r1
- blo 1b
- mov pc, lr
-
- __INITDATA
-
- /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
- define_tlb_functions v3, v3_tlb_flags
return PCIBIOS_SUCCESSFUL;
}
-static struct pci_ops iop3xx_ops = {
+struct pci_ops iop3xx_ops = {
.read = iop3xx_read_config,
.write = iop3xx_write_config,
};
return 1;
}
-struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *sys)
-{
- return pci_scan_root_bus(NULL, sys->busnr, &iop3xx_ops, sys,
- &sys->resources);
-}
-
void __init iop3xx_atu_setup(void)
{
/* BAR 0 ( Disabled ) */
#include <linux/io.h>
#include <linux/clocksource.h>
+#include <asm/mach/time.h>
#include <asm/sched_clock.h>
#include <plat/hardware.h>
}
/**
- * read_persistent_clock - Return time from a persistent clock.
+ * omap_read_persistent_clock - Return time from a persistent clock.
*
* Reads the time from a source which isn't disabled during PM, the
* 32k sync timer. Convert the cycles elapsed since last read into
static struct timespec persistent_ts;
static cycles_t cycles, last_cycles;
static unsigned int persistent_mult, persistent_shift;
-void read_persistent_clock(struct timespec *ts)
+static void omap_read_persistent_clock(struct timespec *ts)
{
unsigned long long nsecs;
cycles_t delta;
printk(err, "32k_counter");
setup_sched_clock(omap_32k_read_sched_clock, 32, 32768);
+ register_persistent_clock(NULL, omap_read_persistent_clock);
}
return 0;
}
config PLAT_VERSATILE_FPGA_IRQ
bool
+ select IRQ_DOMAIN
+
+config PLAT_VERSATILE_FPGA_IRQ_NR
+ int
+ default 4
+ depends on PLAT_VERSATILE_FPGA_IRQ
config PLAT_VERSATILE_LEDS
def_bool y if LEDS_CLASS
*/
#include <linux/irq.h>
#include <linux/io.h>
+#include <linux/irqdomain.h>
+#include <linux/module.h>
+#include <asm/exception.h>
#include <asm/mach/irq.h>
#include <plat/fpga-irq.h>
#define IRQ_ENABLE_SET 0x08
#define IRQ_ENABLE_CLEAR 0x0c
+/**
+ * struct fpga_irq_data - irq data container for the FPGA IRQ controller
+ * @base: memory offset in virtual memory
+ * @irq_start: first IRQ number handled by this instance
+ * @chip: chip container for this instance
+ * @domain: IRQ domain for this instance
+ * @valid: mask for valid IRQs on this controller
+ * @used_irqs: number of active IRQs on this controller
+ */
+struct fpga_irq_data {
+ void __iomem *base;
+ unsigned int irq_start;
+ struct irq_chip chip;
+ u32 valid;
+ struct irq_domain *domain;
+ u8 used_irqs;
+};
+
+/* we cannot allocate memory when the controllers are initially registered */
+static struct fpga_irq_data fpga_irq_devices[CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR];
+static int fpga_irq_id;
+
static void fpga_irq_mask(struct irq_data *d)
{
struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
- u32 mask = 1 << (d->irq - f->irq_start);
+ u32 mask = 1 << d->hwirq;
writel(mask, f->base + IRQ_ENABLE_CLEAR);
}
static void fpga_irq_unmask(struct irq_data *d)
{
struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
- u32 mask = 1 << (d->irq - f->irq_start);
+ u32 mask = 1 << d->hwirq;
writel(mask, f->base + IRQ_ENABLE_SET);
}
do {
irq = ffs(status) - 1;
status &= ~(1 << irq);
-
- generic_handle_irq(irq + f->irq_start);
+ generic_handle_irq(irq_find_mapping(f->domain, irq));
} while (status);
}
-void __init fpga_irq_init(int parent_irq, u32 valid, struct fpga_irq_data *f)
+/*
+ * Handle each interrupt in a single FPGA IRQ controller. Returns non-zero
+ * if we've handled at least one interrupt. This does a single read of the
+ * status register and handles all interrupts in order from LSB first.
+ */
+static int handle_one_fpga(struct fpga_irq_data *f, struct pt_regs *regs)
+{
+ int handled = 0;
+ int irq;
+ u32 status;
+
+ while ((status = readl(f->base + IRQ_STATUS))) {
+ irq = ffs(status) - 1;
+ handle_IRQ(irq_find_mapping(f->domain, irq), regs);
+ handled = 1;
+ }
+
+ return handled;
+}
+
+/*
+ * Keep iterating over all registered FPGA IRQ controllers until there are
+ * no pending interrupts.
+ */
+asmlinkage void __exception_irq_entry fpga_handle_irq(struct pt_regs *regs)
{
- unsigned int i;
+ int i, handled;
+ do {
+ for (i = 0, handled = 0; i < fpga_irq_id; ++i)
+ handled |= handle_one_fpga(&fpga_irq_devices[i], regs);
+ } while (handled);
+}
+
+static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
+ irq_hw_number_t hwirq)
+{
+ struct fpga_irq_data *f = d->host_data;
+
+ /* Skip invalid IRQs, only register handlers for the real ones */
+ if (!(f->valid & (1 << hwirq)))
+ return -ENOTSUPP;
+ irq_set_chip_data(irq, f);
+ irq_set_chip_and_handler(irq, &f->chip,
+ handle_level_irq);
+ set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+ f->used_irqs++;
+ return 0;
+}
+
+static struct irq_domain_ops fpga_irqdomain_ops = {
+ .map = fpga_irqdomain_map,
+ .xlate = irq_domain_xlate_onetwocell,
+};
+
+void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
+ int parent_irq, u32 valid, struct device_node *node)
+{
+ struct fpga_irq_data *f;
+
+ if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
+ printk(KERN_ERR "%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__);
+ return;
+ }
+
+ f = &fpga_irq_devices[fpga_irq_id];
+ f->base = base;
+ f->irq_start = irq_start;
+ f->chip.name = name;
f->chip.irq_ack = fpga_irq_mask;
f->chip.irq_mask = fpga_irq_mask;
f->chip.irq_unmask = fpga_irq_unmask;
+ f->valid = valid;
if (parent_irq != -1) {
irq_set_handler_data(parent_irq, f);
irq_set_chained_handler(parent_irq, fpga_irq_handle);
}
- for (i = 0; i < 32; i++) {
- if (valid & (1 << i)) {
- unsigned int irq = f->irq_start + i;
+ f->domain = irq_domain_add_legacy(node, fls(valid), f->irq_start, 0,
+ &fpga_irqdomain_ops, f);
+ pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
+ fpga_irq_id, name, base, f->used_irqs);
- irq_set_chip_data(irq, f);
- irq_set_chip_and_handler(irq, &f->chip,
- handle_level_irq);
- set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
- }
- }
+ fpga_irq_id++;
}
#ifndef PLAT_FPGA_IRQ_H
#define PLAT_FPGA_IRQ_H
-struct fpga_irq_data {
- void __iomem *base;
- unsigned int irq_start;
- struct irq_chip chip;
-};
+struct device_node;
+struct pt_regs;
-void fpga_irq_init(int, u32, struct fpga_irq_data *);
+void fpga_handle_irq(struct pt_regs *regs);
+void fpga_irq_init(void __iomem *, const char *, int, int, u32,
+ struct device_node *node);
#endif
# are merged into mainline or have been edited in the machine database
# within the last 12 months. References to machine_is_NAME() do not count!
#
-# Last update: Tue Dec 6 11:07:38 2011
+# Last update: Thu Apr 26 08:44:23 2012
#
# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
#
snapper_cl15 MACH_SNAPPER_CL15 SNAPPER_CL15 986
omap_palmz71 MACH_OMAP_PALMZ71 OMAP_PALMZ71 993
smdk2412 MACH_SMDK2412 SMDK2412 1009
+bkde303 MACH_BKDE303 BKDE303 1021
smdk2413 MACH_SMDK2413 SMDK2413 1022
aml_m5900 MACH_AML_M5900 AML_M5900 1024
balloon3 MACH_BALLOON3 BALLOON3 1029
at91sam9g10ek MACH_AT91SAM9G10EK AT91SAM9G10EK 2159
omap_4430sdp MACH_OMAP_4430SDP OMAP_4430SDP 2160
magx_zn5 MACH_MAGX_ZN5 MAGX_ZN5 2162
-btmavb101 MACH_BTMAVB101 BTMAVB101 2172
-btmawb101 MACH_BTMAWB101 BTMAWB101 2173
tx25 MACH_TX25 TX25 2177
omap3_torpedo MACH_OMAP3_TORPEDO OMAP3_TORPEDO 2178
anw6410 MACH_ANW6410 ANW6410 2183
net5big_v2 MACH_NET5BIG_V2 NET5BIG_V2 2206
inetspace_v2 MACH_INETSPACE_V2 INETSPACE_V2 2208
at91sam9g45ekes MACH_AT91SAM9G45EKES AT91SAM9G45EKES 2212
-pc7302 MACH_PC7302 PC7302 2220
spear600 MACH_SPEAR600 SPEAR600 2236
spear300 MACH_SPEAR300 SPEAR300 2237
lilly1131 MACH_LILLY1131 LILLY1131 2239
bigdisk MACH_BIGDISK BIGDISK 2283
at91sam9g20ek_2mmc MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC 2288
bcmring MACH_BCMRING BCMRING 2289
-dp6xx MACH_DP6XX DP6XX 2302
mahimahi MACH_MAHIMAHI MAHIMAHI 2304
smdk6442 MACH_SMDK6442 SMDK6442 2324
openrd_base MACH_OPENRD_BASE OPENRD_BASE 2325
smartq5 MACH_SMARTQ5 SMARTQ5 2534
davinci_dm6467tevm MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM 2548
mxt_td60 MACH_MXT_TD60 MXT_TD60 2550
-riot_bei2 MACH_RIOT_BEI2 RIOT_BEI2 2576
-riot_x37 MACH_RIOT_X37 RIOT_X37 2578
pca101 MACH_PCA101 PCA101 2595
capc7117 MACH_CAPC7117 CAPC7117 2612
icontrol MACH_ICONTROL ICONTROL 2624
aquila MACH_AQUILA AQUILA 2676
esata_sheevaplug MACH_ESATA_SHEEVAPLUG ESATA_SHEEVAPLUG 2678
msm7x30_surf MACH_MSM7X30_SURF MSM7X30_SURF 2679
-ea2478devkit MACH_EA2478DEVKIT EA2478DEVKIT 2683
terastation_wxl MACH_TERASTATION_WXL TERASTATION_WXL 2697
msm7x25_surf MACH_MSM7X25_SURF MSM7X25_SURF 2703
msm7x25_ffa MACH_MSM7X25_FFA MSM7X25_FFA 2704
msm8x60_surf MACH_MSM8X60_SURF MSM8X60_SURF 2755
msm8x60_sim MACH_MSM8X60_SIM MSM8X60_SIM 2756
tcc8000_sdk MACH_TCC8000_SDK TCC8000_SDK 2758
-nanos MACH_NANOS NANOS 2759
-stamp9g45 MACH_STAMP9G45 STAMP9G45 2761
cns3420vb MACH_CNS3420VB CNS3420VB 2776
omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791
ti8168evm MACH_TI8168EVM TI8168EVM 2800
eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822
eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823
smdkc210 MACH_SMDKC210 SMDKC210 2838
-pca102 MACH_PCA102 PCA102 2843
+pcaal1 MACH_PCAAL1 PCAAL1 2843
t5325 MACH_T5325 T5325 2846
income MACH_INCOME INCOME 2849
-vvbox_sdorig2 MACH_VVBOX_SDORIG2 VVBOX_SDORIG2 2857
-vvbox_sdlite2 MACH_VVBOX_SDLITE2 VVBOX_SDLITE2 2858
-vvbox_sdpro4 MACH_VVBOX_SDPRO4 VVBOX_SDPRO4 2859
mx257sx MACH_MX257SX MX257SX 2861
goni MACH_GONI GONI 2862
bv07 MACH_BV07 BV07 2882
miccpt MACH_MICCPT MICCPT 2886
mic256 MACH_MIC256 MIC256 2887
u5500 MACH_U5500 U5500 2890
+pov15hd MACH_POV15HD POV15HD 2910
linkstation_lschl MACH_LINKSTATION_LSCHL LINKSTATION_LSCHL 2913
smdkv310 MACH_SMDKV310 SMDKV310 2925
wm8505_7in_netbook MACH_WM8505_7IN_NETBOOK WM8505_7IN_NETBOOK 2928
mackerel MACH_MACKEREL MACKEREL 3211
kaen MACH_KAEN KAEN 3217
nokia_rm680 MACH_NOKIA_RM680 NOKIA_RM680 3220
-dm6446_adbox MACH_DM6446_ADBOX DM6446_ADBOX 3226
-quad_salsa MACH_QUAD_SALSA QUAD_SALSA 3227
-abb_gma_1_1 MACH_ABB_GMA_1_1 ABB_GMA_1_1 3228
-svcid MACH_SVCID SVCID 3229
msm8960_sim MACH_MSM8960_SIM MSM8960_SIM 3230
msm8960_rumi3 MACH_MSM8960_RUMI3 MSM8960_RUMI3 3231
-icon_g MACH_ICON_G ICON_G 3232
-mb3 MACH_MB3 MB3 3233
gsia18s MACH_GSIA18S GSIA18S 3234
-pivicc MACH_PIVICC PIVICC 3235
-pcm048 MACH_PCM048 PCM048 3236
-dds MACH_DDS DDS 3237
-chalten_xa1 MACH_CHALTEN_XA1 CHALTEN_XA1 3238
-ts48xx MACH_TS48XX TS48XX 3239
-tonga2_tfttimer MACH_TONGA2_TFTTIMER TONGA2_TFTTIMER 3240
-whistler MACH_WHISTLER WHISTLER 3241
-asl_phoenix MACH_ASL_PHOENIX ASL_PHOENIX 3242
-at91sam9263otlite MACH_AT91SAM9263OTLITE AT91SAM9263OTLITE 3243
-ddplug MACH_DDPLUG DDPLUG 3244
-d2plug MACH_D2PLUG D2PLUG 3245
-kzm9d MACH_KZM9D KZM9D 3246
-verdi_lte MACH_VERDI_LTE VERDI_LTE 3247
-nanozoom MACH_NANOZOOM NANOZOOM 3248
-dm3730_som_lv MACH_DM3730_SOM_LV DM3730_SOM_LV 3249
-dm3730_torpedo MACH_DM3730_TORPEDO DM3730_TORPEDO 3250
-anchovy MACH_ANCHOVY ANCHOVY 3251
-re2rev20 MACH_RE2REV20 RE2REV20 3253
-re2rev21 MACH_RE2REV21 RE2REV21 3254
-cns21xx MACH_CNS21XX CNS21XX 3255
-rider MACH_RIDER RIDER 3257
-nsk330 MACH_NSK330 NSK330 3258
-cns2133evb MACH_CNS2133EVB CNS2133EVB 3259
-z3_816x_mod MACH_Z3_816X_MOD Z3_816X_MOD 3260
-z3_814x_mod MACH_Z3_814X_MOD Z3_814X_MOD 3261
-beect MACH_BEECT BEECT 3262
-dma_thunderbug MACH_DMA_THUNDERBUG DMA_THUNDERBUG 3263
-omn_at91sam9g20 MACH_OMN_AT91SAM9G20 OMN_AT91SAM9G20 3264
-mx25_e2s_uc MACH_MX25_E2S_UC MX25_E2S_UC 3265
-mione MACH_MIONE MIONE 3266
-top9000_tcu MACH_TOP9000_TCU TOP9000_TCU 3267
-top9000_bsl MACH_TOP9000_BSL TOP9000_BSL 3268
-kingdom MACH_KINGDOM KINGDOM 3269
-armadillo460 MACH_ARMADILLO460 ARMADILLO460 3270
-lq2 MACH_LQ2 LQ2 3271
-sweda_tms2 MACH_SWEDA_TMS2 SWEDA_TMS2 3272
mx53_loco MACH_MX53_LOCO MX53_LOCO 3273
-acer_a8 MACH_ACER_A8 ACER_A8 3275
-acer_gauguin MACH_ACER_GAUGUIN ACER_GAUGUIN 3276
-guppy MACH_GUPPY GUPPY 3277
-mx61_ard MACH_MX61_ARD MX61_ARD 3278
tx53 MACH_TX53 TX53 3279
-omapl138_case_a3 MACH_OMAPL138_CASE_A3 OMAPL138_CASE_A3 3280
-uemd MACH_UEMD UEMD 3281
-ccwmx51mut MACH_CCWMX51MUT CCWMX51MUT 3282
-rockhopper MACH_ROCKHOPPER ROCKHOPPER 3283
encore MACH_ENCORE ENCORE 3284
-hkdkc100 MACH_HKDKC100 HKDKC100 3285
-ts42xx MACH_TS42XX TS42XX 3286
-aebl MACH_AEBL AEBL 3287
wario MACH_WARIO WARIO 3288
-gfs_spm MACH_GFS_SPM GFS_SPM 3289
cm_t3730 MACH_CM_T3730 CM_T3730 3290
-isc3 MACH_ISC3 ISC3 3291
-rascal MACH_RASCAL RASCAL 3292
hrefv60 MACH_HREFV60 HREFV60 3293
-tpt_2_0 MACH_TPT_2_0 TPT_2_0 3294
-splendor MACH_SPLENDOR SPLENDOR 3296
-msm8x60_qt MACH_MSM8X60_QT MSM8X60_QT 3298
-htc_hd_mini MACH_HTC_HD_MINI HTC_HD_MINI 3299
-athene MACH_ATHENE ATHENE 3300
-deep_r_ek_1 MACH_DEEP_R_EK_1 DEEP_R_EK_1 3301
-vivow_ct MACH_VIVOW_CT VIVOW_CT 3302
-nery_1000 MACH_NERY_1000 NERY_1000 3303
-rfl109145_ssrv MACH_RFL109145_SSRV RFL109145_SSRV 3304
-nmh MACH_NMH NMH 3305
-wn802t MACH_WN802T WN802T 3306
-dragonet MACH_DRAGONET DRAGONET 3307
-at91sam9263desk16l MACH_AT91SAM9263DESK16L AT91SAM9263DESK16L 3309
-bcmhana_sv MACH_BCMHANA_SV BCMHANA_SV 3310
-bcmhana_tablet MACH_BCMHANA_TABLET BCMHANA_TABLET 3311
-koi MACH_KOI KOI 3312
-ts4800 MACH_TS4800 TS4800 3313
-tqma9263 MACH_TQMA9263 TQMA9263 3314
-holiday MACH_HOLIDAY HOLIDAY 3315
-pcats_overlay MACH_PCATS_OVERLAY PCATS_OVERLAY 3317
-hwgw6410 MACH_HWGW6410 HWGW6410 3318
-shenzhou MACH_SHENZHOU SHENZHOU 3319
-cwme9210 MACH_CWME9210 CWME9210 3320
-cwme9210js MACH_CWME9210JS CWME9210JS 3321
-colibri_tegra2 MACH_COLIBRI_TEGRA2 COLIBRI_TEGRA2 3323
-w21 MACH_W21 W21 3324
-polysat1 MACH_POLYSAT1 POLYSAT1 3325
-dataway MACH_DATAWAY DATAWAY 3326
-cobral138 MACH_COBRAL138 COBRAL138 3327
-roverpcs8 MACH_ROVERPCS8 ROVERPCS8 3328
-marvelc MACH_MARVELC MARVELC 3329
-navefihid MACH_NAVEFIHID NAVEFIHID 3330
-dm365_cv100 MACH_DM365_CV100 DM365_CV100 3331
-able MACH_ABLE ABLE 3332
-legacy MACH_LEGACY LEGACY 3333
-icong MACH_ICONG ICONG 3334
-rover_g8 MACH_ROVER_G8 ROVER_G8 3335
-t5388p MACH_T5388P T5388P 3336
-dingo MACH_DINGO DINGO 3337
-goflexhome MACH_GOFLEXHOME GOFLEXHOME 3338
-lanreadyfn511 MACH_LANREADYFN511 LANREADYFN511 3340
-omap3_baia MACH_OMAP3_BAIA OMAP3_BAIA 3341
-omap3smartdisplay MACH_OMAP3SMARTDISPLAY OMAP3SMARTDISPLAY 3342
-xilinx MACH_XILINX XILINX 3343
-a2f MACH_A2F A2F 3344
-sky25 MACH_SKY25 SKY25 3345
-ccmx53 MACH_CCMX53 CCMX53 3346
-ccmx53js MACH_CCMX53JS CCMX53JS 3347
-ccwmx53 MACH_CCWMX53 CCWMX53 3348
-ccwmx53js MACH_CCWMX53JS CCWMX53JS 3349
-frisms MACH_FRISMS FRISMS 3350
-msm7x27a_ffa MACH_MSM7X27A_FFA MSM7X27A_FFA 3351
-msm7x27a_surf MACH_MSM7X27A_SURF MSM7X27A_SURF 3352
-msm7x27a_rumi3 MACH_MSM7X27A_RUMI3 MSM7X27A_RUMI3 3353
-dimmsam9g20 MACH_DIMMSAM9G20 DIMMSAM9G20 3354
-dimm_imx28 MACH_DIMM_IMX28 DIMM_IMX28 3355
-amk_a4 MACH_AMK_A4 AMK_A4 3356
-gnet_sgme MACH_GNET_SGME GNET_SGME 3357
-shooter_u MACH_SHOOTER_U SHOOTER_U 3358
-vmx53 MACH_VMX53 VMX53 3359
-rhino MACH_RHINO RHINO 3360
armlex4210 MACH_ARMLEX4210 ARMLEX4210 3361
-swarcoextmodem MACH_SWARCOEXTMODEM SWARCOEXTMODEM 3362
snowball MACH_SNOWBALL SNOWBALL 3363
-pcm049 MACH_PCM049 PCM049 3364
-vigor MACH_VIGOR VIGOR 3365
-oslo_amundsen MACH_OSLO_AMUNDSEN OSLO_AMUNDSEN 3366
-gsl_diamond MACH_GSL_DIAMOND GSL_DIAMOND 3367
-cv2201 MACH_CV2201 CV2201 3368
-cv2202 MACH_CV2202 CV2202 3369
-cv2203 MACH_CV2203 CV2203 3370
-vit_ibox MACH_VIT_IBOX VIT_IBOX 3371
-dm6441_esp MACH_DM6441_ESP DM6441_ESP 3372
-at91sam9x5ek MACH_AT91SAM9X5EK AT91SAM9X5EK 3373
-libra MACH_LIBRA LIBRA 3374
-easycrrh MACH_EASYCRRH EASYCRRH 3375
-tripel MACH_TRIPEL TRIPEL 3376
-endian_mini MACH_ENDIAN_MINI ENDIAN_MINI 3377
xilinx_ep107 MACH_XILINX_EP107 XILINX_EP107 3378
nuri MACH_NURI NURI 3379
-janus MACH_JANUS JANUS 3380
-ddnas MACH_DDNAS DDNAS 3381
-tag MACH_TAG TAG 3382
-tagw MACH_TAGW TAGW 3383
-nitrogen_vm_imx51 MACH_NITROGEN_VM_IMX51 NITROGEN_VM_IMX51 3384
-viprinet MACH_VIPRINET VIPRINET 3385
-bockw MACH_BOCKW BOCKW 3386
-eva2000 MACH_EVA2000 EVA2000 3387
-steelyard MACH_STEELYARD STEELYARD 3388
-nsslsboard MACH_NSSLSBOARD NSSLSBOARD 3392
-geneva_b5 MACH_GENEVA_B5 GENEVA_B5 3393
-spear1340 MACH_SPEAR1340 SPEAR1340 3394
-rexmas MACH_REXMAS REXMAS 3395
-msm8960_cdp MACH_MSM8960_CDP MSM8960_CDP 3396
-msm8960_fluid MACH_MSM8960_FLUID MSM8960_FLUID 3398
-msm8960_apq MACH_MSM8960_APQ MSM8960_APQ 3399
-helios_v2 MACH_HELIOS_V2 HELIOS_V2 3400
-mif10p MACH_MIF10P MIF10P 3401
-iam28 MACH_IAM28 IAM28 3402
-picasso MACH_PICASSO PICASSO 3403
-mr301a MACH_MR301A MR301A 3404
-notle MACH_NOTLE NOTLE 3405
-eelx2 MACH_EELX2 EELX2 3406
-moon MACH_MOON MOON 3407
-ruby MACH_RUBY RUBY 3408
-goldengate MACH_GOLDENGATE GOLDENGATE 3409
-ctbu_gen2 MACH_CTBU_GEN2 CTBU_GEN2 3410
-kmp_am17_01 MACH_KMP_AM17_01 KMP_AM17_01 3411
wtplug MACH_WTPLUG WTPLUG 3412
-mx27su2 MACH_MX27SU2 MX27SU2 3413
-nb31 MACH_NB31 NB31 3414
-hjsdu MACH_HJSDU HJSDU 3415
-td3_rev1 MACH_TD3_REV1 TD3_REV1 3416
-eag_ci4000 MACH_EAG_CI4000 EAG_CI4000 3417
-net5big_nand_v2 MACH_NET5BIG_NAND_V2 NET5BIG_NAND_V2 3418
-cpx2 MACH_CPX2 CPX2 3419
-net2big_nand_v2 MACH_NET2BIG_NAND_V2 NET2BIG_NAND_V2 3420
-ecuv5 MACH_ECUV5 ECUV5 3421
-hsgx6d MACH_HSGX6D HSGX6D 3422
-dawad7 MACH_DAWAD7 DAWAD7 3423
-sam9repeater MACH_SAM9REPEATER SAM9REPEATER 3424
-gt_i5700 MACH_GT_I5700 GT_I5700 3425
-ctera_plug_c2 MACH_CTERA_PLUG_C2 CTERA_PLUG_C2 3426
-marvelct MACH_MARVELCT MARVELCT 3427
-ag11005 MACH_AG11005 AG11005 3428
-vangogh MACH_VANGOGH VANGOGH 3430
-matrix505 MACH_MATRIX505 MATRIX505 3431
-oce_nigma MACH_OCE_NIGMA OCE_NIGMA 3432
-t55 MACH_T55 T55 3433
-bio3k MACH_BIO3K BIO3K 3434
-expressct MACH_EXPRESSCT EXPRESSCT 3435
-cardhu MACH_CARDHU CARDHU 3436
-aruba MACH_ARUBA ARUBA 3437
-bonaire MACH_BONAIRE BONAIRE 3438
-nuc700evb MACH_NUC700EVB NUC700EVB 3439
-nuc710evb MACH_NUC710EVB NUC710EVB 3440
-nuc740evb MACH_NUC740EVB NUC740EVB 3441
-nuc745evb MACH_NUC745EVB NUC745EVB 3442
-transcede MACH_TRANSCEDE TRANSCEDE 3443
-mora MACH_MORA MORA 3444
-nda_evm MACH_NDA_EVM NDA_EVM 3445
-timu MACH_TIMU TIMU 3446
-expressh MACH_EXPRESSH EXPRESSH 3447
veridis_a300 MACH_VERIDIS_A300 VERIDIS_A300 3448
-dm368_leopard MACH_DM368_LEOPARD DM368_LEOPARD 3449
-omap_mcop MACH_OMAP_MCOP OMAP_MCOP 3450
-tritip MACH_TRITIP TRITIP 3451
-sm1k MACH_SM1K SM1K 3452
-monch MACH_MONCH MONCH 3453
-curacao MACH_CURACAO CURACAO 3454
origen MACH_ORIGEN ORIGEN 3455
-epc10 MACH_EPC10 EPC10 3456
-sgh_i740 MACH_SGH_I740 SGH_I740 3457
-tuna MACH_TUNA TUNA 3458
-mx51_tulip MACH_MX51_TULIP MX51_TULIP 3459
-mx51_aster7 MACH_MX51_ASTER7 MX51_ASTER7 3460
-acro37xbrd MACH_ACRO37XBRD ACRO37XBRD 3461
-elke MACH_ELKE ELKE 3462
-sbc6000x MACH_SBC6000X SBC6000X 3463
-r1801e MACH_R1801E R1801E 3464
-h1600 MACH_H1600 H1600 3465
-mini210 MACH_MINI210 MINI210 3466
-mini8168 MACH_MINI8168 MINI8168 3467
-pc7308 MACH_PC7308 PC7308 3468
-kmm2m01 MACH_KMM2M01 KMM2M01 3470
-mx51erebus MACH_MX51EREBUS MX51EREBUS 3471
wm8650refboard MACH_WM8650REFBOARD WM8650REFBOARD 3472
-tuxrail MACH_TUXRAIL TUXRAIL 3473
-arthur MACH_ARTHUR ARTHUR 3474
-doorboy MACH_DOORBOY DOORBOY 3475
xarina MACH_XARINA XARINA 3476
-roverx7 MACH_ROVERX7 ROVERX7 3477
sdvr MACH_SDVR SDVR 3478
acer_maya MACH_ACER_MAYA ACER_MAYA 3479
pico MACH_PICO PICO 3480
amp MACH_AMP AMP 3709
gnet_amp MACH_GNET_AMP GNET_AMP 3710
toques MACH_TOQUES TOQUES 3711
+apx4devkit MACH_APX4DEVKIT APX4DEVKIT 3712
dct_storm MACH_DCT_STORM DCT_STORM 3713
owl MACH_OWL OWL 3715
cogent_csb1741 MACH_COGENT_CSB1741 COGENT_CSB1741 3716
omap3_devkit8500 MACH_OMAP3_DEVKIT8500 OMAP3_DEVKIT8500 3779
edgetd MACH_EDGETD EDGETD 3780
copperyard MACH_COPPERYARD COPPERYARD 3781
-edge MACH_EDGE EDGE 3782
edge_u MACH_EDGE_U EDGE_U 3783
edge_td MACH_EDGE_TD EDGE_TD 3784
wdss MACH_WDSS WDSS 3785
pov2 MACH_POV2 POV2 3889
ipod_touch_2g MACH_IPOD_TOUCH_2G IPOD_TOUCH_2G 3890
da850_pqab MACH_DA850_PQAB DA850_PQAB 3891
+fermi MACH_FERMI FERMI 3892
+ccardwmx28 MACH_CCARDWMX28 CCARDWMX28 3893
+ccardmx28 MACH_CCARDMX28 CCARDMX28 3894
+fs20_fcm2050 MACH_FS20_FCM2050 FS20_FCM2050 3895
+kinetis MACH_KINETIS KINETIS 3896
+kai MACH_KAI KAI 3897
+bcthb2 MACH_BCTHB2 BCTHB2 3898
+inels3_cu MACH_INELS3_CU INELS3_CU 3899
+da850_apollo MACH_DA850_APOLLO DA850_APOLLO 3901
+tracnas MACH_TRACNAS TRACNAS 3902
+mityarm335x MACH_MITYARM335X MITYARM335X 3903
+xcgz7x MACH_XCGZ7X XCGZ7X 3904
+cubox MACH_CUBOX CUBOX 3905
+terminator MACH_TERMINATOR TERMINATOR 3906
+eye03 MACH_EYE03 EYE03 3907
+kota3 MACH_KOTA3 KOTA3 3908
+pscpe MACH_PSCPE PSCPE 3910
+akt1100 MACH_AKT1100 AKT1100 3911
+pcaaxl2 MACH_PCAAXL2 PCAAXL2 3912
+primodd_ct MACH_PRIMODD_CT PRIMODD_CT 3913
+nsbc MACH_NSBC NSBC 3914
+meson2_skt MACH_MESON2_SKT MESON2_SKT 3915
+meson2_ref MACH_MESON2_REF MESON2_REF 3916
+ccardwmx28js MACH_CCARDWMX28JS CCARDWMX28JS 3917
+ccardmx28js MACH_CCARDMX28JS CCARDMX28JS 3918
+indico MACH_INDICO INDICO 3919
+msm8960dt MACH_MSM8960DT MSM8960DT 3920
+primods MACH_PRIMODS PRIMODS 3921
+beluga_m1388 MACH_BELUGA_M1388 BELUGA_M1388 3922
+primotd MACH_PRIMOTD PRIMOTD 3923
+varan_master MACH_VARAN_MASTER VARAN_MASTER 3924
+primodd MACH_PRIMODD PRIMODD 3925
+jetduo MACH_JETDUO JETDUO 3926
+mx53_umobo MACH_MX53_UMOBO MX53_UMOBO 3927
+trats MACH_TRATS TRATS 3928
+starcraft MACH_STARCRAFT STARCRAFT 3929
+qseven_tegra2 MACH_QSEVEN_TEGRA2 QSEVEN_TEGRA2 3930
+lichee_sun4i_devbd MACH_LICHEE_SUN4I_DEVBD LICHEE_SUN4I_DEVBD 3931
+movenow MACH_MOVENOW MOVENOW 3932
+golf_u MACH_GOLF_U GOLF_U 3933
+msm7627a_evb MACH_MSM7627A_EVB MSM7627A_EVB 3934
+rambo MACH_RAMBO RAMBO 3935
+golfu MACH_GOLFU GOLFU 3936
+mango310 MACH_MANGO310 MANGO310 3937
+dns343 MACH_DNS343 DNS343 3938
+var_som_om44 MACH_VAR_SOM_OM44 VAR_SOM_OM44 3939
+naon MACH_NAON NAON 3940
+vp4000 MACH_VP4000 VP4000 3941
+impcard MACH_IMPCARD IMPCARD 3942
+smoovcam MACH_SMOOVCAM SMOOVCAM 3943
+cobham3725 MACH_COBHAM3725 COBHAM3725 3944
+cobham3730 MACH_COBHAM3730 COBHAM3730 3945
+cobham3703 MACH_COBHAM3703 COBHAM3703 3946
+quetzal MACH_QUETZAL QUETZAL 3947
+apq8064_cdp MACH_APQ8064_CDP APQ8064_CDP 3948
+apq8064_mtp MACH_APQ8064_MTP APQ8064_MTP 3949
+apq8064_fluid MACH_APQ8064_FLUID APQ8064_FLUID 3950
+apq8064_liquid MACH_APQ8064_LIQUID APQ8064_LIQUID 3951
+mango210 MACH_MANGO210 MANGO210 3952
+mango100 MACH_MANGO100 MANGO100 3953
+mango24 MACH_MANGO24 MANGO24 3954
+mango64 MACH_MANGO64 MANGO64 3955
+nsa320 MACH_NSA320 NSA320 3956
+elv_ccu2 MACH_ELV_CCU2 ELV_CCU2 3957
+triton_x00 MACH_TRITON_X00 TRITON_X00 3958
+triton_1500_2000 MACH_TRITON_1500_2000 TRITON_1500_2000 3959
+pogoplugv4 MACH_POGOPLUGV4 POGOPLUGV4 3960
+venus_cl MACH_VENUS_CL VENUS_CL 3961
+vulcano_g20 MACH_VULCANO_G20 VULCANO_G20 3962
+sgs_i9100 MACH_SGS_I9100 SGS_I9100 3963
+stsv2 MACH_STSV2 STSV2 3964
+csb1724 MACH_CSB1724 CSB1724 3965
+omapl138_lcdk MACH_OMAPL138_LCDK OMAPL138_LCDK 3966
+pvd_mx25 MACH_PVD_MX25 PVD_MX25 3968
+meson6_skt MACH_MESON6_SKT MESON6_SKT 3969
+meson6_ref MACH_MESON6_REF MESON6_REF 3970
+pxm MACH_PXM PXM 3971
+pogoplugv3 MACH_POGOPLUGV3 POGOPLUGV3 3973
+mlp89626 MACH_MLP89626 MLP89626 3974
+iomegahmndce MACH_IOMEGAHMNDCE IOMEGAHMNDCE 3975
+pogoplugv3pci MACH_POGOPLUGV3PCI POGOPLUGV3PCI 3976
+bntv250 MACH_BNTV250 BNTV250 3977
+mx53_qseven MACH_MX53_QSEVEN MX53_QSEVEN 3978
+gtl_it1100 MACH_GTL_IT1100 GTL_IT1100 3979
+mx6q_sabresd MACH_MX6Q_SABRESD MX6Q_SABRESD 3980
+mt4 MACH_MT4 MT4 3981
+jumbo_d MACH_JUMBO_D JUMBO_D 3982
+jumbo_i MACH_JUMBO_I JUMBO_I 3983
+fs20_dmp MACH_FS20_DMP FS20_DMP 3984
+dns320 MACH_DNS320 DNS320 3985
+mx28bacos MACH_MX28BACOS MX28BACOS 3986
+tl80 MACH_TL80 TL80 3987
+polatis_nic_1001 MACH_POLATIS_NIC_1001 POLATIS_NIC_1001 3988
+tely MACH_TELY TELY 3989
+u8520 MACH_U8520 U8520 3990
+manta MACH_MANTA MANTA 3991
+mpq8064_cdp MACH_MPQ8064_CDP MPQ8064_CDP 3993
+mpq8064_dtv MACH_MPQ8064_DTV MPQ8064_DTV 3995
+dm368som MACH_DM368SOM DM368SOM 3996
+gprisb2 MACH_GPRISB2 GPRISB2 3997
+chammid MACH_CHAMMID CHAMMID 3998
+seoul2 MACH_SEOUL2 SEOUL2 3999
+omap4_nooktablet MACH_OMAP4_NOOKTABLET OMAP4_NOOKTABLET 4000
+aalto MACH_AALTO AALTO 4001
+metro MACH_METRO METRO 4002
+cydm3730 MACH_CYDM3730 CYDM3730 4003
+tqma53 MACH_TQMA53 TQMA53 4004
+msm7627a_qrd3 MACH_MSM7627A_QRD3 MSM7627A_QRD3 4005
+mx28_canby MACH_MX28_CANBY MX28_CANBY 4006
+tiger MACH_TIGER TIGER 4007
+pcats_9307_type_a MACH_PCATS_9307_TYPE_A PCATS_9307_TYPE_A 4008
+pcats_9307_type_o MACH_PCATS_9307_TYPE_O PCATS_9307_TYPE_O 4009
+pcats_9307_type_r MACH_PCATS_9307_TYPE_R PCATS_9307_TYPE_R 4010
+streamplug MACH_STREAMPLUG STREAMPLUG 4011
+icechicken_dev MACH_ICECHICKEN_DEV ICECHICKEN_DEV 4012
+hedgehog MACH_HEDGEHOG HEDGEHOG 4013
+yusend_obc MACH_YUSEND_OBC YUSEND_OBC 4014
+imxninja MACH_IMXNINJA IMXNINJA 4015
+omap4_jarod MACH_OMAP4_JAROD OMAP4_JAROD 4016
+eco5_pk MACH_ECO5_PK ECO5_PK 4017
+qj2440 MACH_QJ2440 QJ2440 4018
+mx6q_mercury MACH_MX6Q_MERCURY MX6Q_MERCURY 4019
+cm6810 MACH_CM6810 CM6810 4020
+omap4_torpedo MACH_OMAP4_TORPEDO OMAP4_TORPEDO 4021
+nsa310 MACH_NSA310 NSA310 4022
+tmx536 MACH_TMX536 TMX536 4023
+ktt20 MACH_KTT20 KTT20 4024
+dragonix MACH_DRAGONIX DRAGONIX 4025
+lungching MACH_LUNGCHING LUNGCHING 4026
+bulogics MACH_BULOGICS BULOGICS 4027
+mx535_sx MACH_MX535_SX MX535_SX 4028
+ngui3250 MACH_NGUI3250 NGUI3250 4029
+salutec_dac MACH_SALUTEC_DAC SALUTEC_DAC 4030
+loco MACH_LOCO LOCO 4031
+ctera_plug_usi MACH_CTERA_PLUG_USI CTERA_PLUG_USI 4032
+scepter MACH_SCEPTER SCEPTER 4033
+sga MACH_SGA SGA 4034
+p_81_j5 MACH_P_81_J5 P_81_J5 4035
+p_81_o4 MACH_P_81_O4 P_81_O4 4036
+msm8625_surf MACH_MSM8625_SURF MSM8625_SURF 4037
+carallon_shark MACH_CARALLON_SHARK CARALLON_SHARK 4038
+ordog MACH_ORDOG ORDOG 4040
+puente_io MACH_PUENTE_IO PUENTE_IO 4041
+msm8625_evb MACH_MSM8625_EVB MSM8625_EVB 4042
+ev_am1707 MACH_EV_AM1707 EV_AM1707 4043
+ev_am1707e2 MACH_EV_AM1707E2 EV_AM1707E2 4044
+ev_am3517e2 MACH_EV_AM3517E2 EV_AM3517E2 4045
+calabria MACH_CALABRIA CALABRIA 4046
+ev_imx287 MACH_EV_IMX287 EV_IMX287 4047
+erau MACH_ERAU ERAU 4048
+sichuan MACH_SICHUAN SICHUAN 4049
+davinci_da850 MACH_DAVINCI_DA850 DAVINCI_DA850 4051
+omap138_trunarc MACH_OMAP138_TRUNARC OMAP138_TRUNARC 4052
+bcm4761 MACH_BCM4761 BCM4761 4053
+picasso_e2 MACH_PICASSO_E2 PICASSO_E2 4054
+picasso_mf MACH_PICASSO_MF PICASSO_MF 4055
+miro MACH_MIRO MIRO 4056
+at91sam9g20ewon3 MACH_AT91SAM9G20EWON3 AT91SAM9G20EWON3 4057
+yoyo MACH_YOYO YOYO 4058
+windjkl MACH_WINDJKL WINDJKL 4059
+monarudo MACH_MONARUDO MONARUDO 4060
+batan MACH_BATAN BATAN 4061
+tadao MACH_TADAO TADAO 4062
+baso MACH_BASO BASO 4063
+mahon MACH_MAHON MAHON 4064
+villec2 MACH_VILLEC2 VILLEC2 4065
+asi1230 MACH_ASI1230 ASI1230 4066
+alaska MACH_ALASKA ALASKA 4067
+swarco_shdsl2 MACH_SWARCO_SHDSL2 SWARCO_SHDSL2 4068
+oxrtu MACH_OXRTU OXRTU 4069
+omap5_panda MACH_OMAP5_PANDA OMAP5_PANDA 4070
+c8000 MACH_C8000 C8000 4072
+bje_display3_5 MACH_BJE_DISPLAY3_5 BJE_DISPLAY3_5 4073
+picomod7 MACH_PICOMOD7 PICOMOD7 4074
+picocom5 MACH_PICOCOM5 PICOCOM5 4075
+qblissa8 MACH_QBLISSA8 QBLISSA8 4076
+armstonea8 MACH_ARMSTONEA8 ARMSTONEA8 4077
+netdcu14 MACH_NETDCU14 NETDCU14 4078
+at91sam9x5_epiphan MACH_AT91SAM9X5_EPIPHAN AT91SAM9X5_EPIPHAN 4079
+p2u MACH_P2U P2U 4080
+doris MACH_DORIS DORIS 4081
+j49 MACH_J49 J49 4082
+vdss2e MACH_VDSS2E VDSS2E 4083
+vc300 MACH_VC300 VC300 4084
+ns115_pad_test MACH_NS115_PAD_TEST NS115_PAD_TEST 4085
+ns115_pad_ref MACH_NS115_PAD_REF NS115_PAD_REF 4086
+ns115_phone_test MACH_NS115_PHONE_TEST NS115_PHONE_TEST 4087
+ns115_phone_ref MACH_NS115_PHONE_REF NS115_PHONE_REF 4088
+golfc MACH_GOLFC GOLFC 4089
+xerox_olympus MACH_XEROX_OLYMPUS XEROX_OLYMPUS 4090
+mx6sl_arm2 MACH_MX6SL_ARM2 MX6SL_ARM2 4091
+csb1701_csb1726 MACH_CSB1701_CSB1726 CSB1701_CSB1726 4092
+at91sam9xeek MACH_AT91SAM9XEEK AT91SAM9XEEK 4093
+ebv210 MACH_EBV210 EBV210 4094
+msm7627a_qrd7 MACH_MSM7627A_QRD7 MSM7627A_QRD7 4095
+svthin MACH_SVTHIN SVTHIN 4096
+duovero MACH_DUOVERO DUOVERO 4097
+chupacabra MACH_CHUPACABRA CHUPACABRA 4098
+scorpion MACH_SCORPION SCORPION 4099
+davinci_he_hmi10 MACH_DAVINCI_HE_HMI10 DAVINCI_HE_HMI10 4100
+topkick MACH_TOPKICK TOPKICK 4101
+m3_auguestrush MACH_M3_AUGUESTRUSH M3_AUGUESTRUSH 4102
+ipc335x MACH_IPC335X IPC335X 4103
+sun4i MACH_SUN4I SUN4I 4104
+imx233_olinuxino MACH_IMX233_OLINUXINO IMX233_OLINUXINO 4105
+k2_wl MACH_K2_WL K2_WL 4106
+k2_ul MACH_K2_UL K2_UL 4107
+k2_cl MACH_K2_CL K2_CL 4108
+minbari_w MACH_MINBARI_W MINBARI_W 4109
+minbari_m MACH_MINBARI_M MINBARI_M 4110
+k035 MACH_K035 K035 4111
+ariel MACH_ARIEL ARIEL 4112
+arielsaarc MACH_ARIELSAARC ARIELSAARC 4113
+arieldkb MACH_ARIELDKB ARIELDKB 4114
+armadillo810 MACH_ARMADILLO810 ARMADILLO810 4115
+tam335x MACH_TAM335X TAM335X 4116
+grouper MACH_GROUPER GROUPER 4117
+mpcsa21_9g20 MACH_MPCSA21_9G20 MPCSA21_9G20 4118
+m6u_cpu MACH_M6U_CPU M6U_CPU 4119
+davinci_dp10 MACH_DAVINCI_DP10 DAVINCI_DP10 4120
+ginkgo MACH_GINKGO GINKGO 4121
+cgt_qmx6 MACH_CGT_QMX6 CGT_QMX6 4122
+profpga MACH_PROFPGA PROFPGA 4123
+acfx100oc MACH_ACFX100OC ACFX100OC 4124
+acfx100nb MACH_ACFX100NB ACFX100NB 4125
+capricorn MACH_CAPRICORN CAPRICORN 4126
+pisces MACH_PISCES PISCES 4127
+aries MACH_ARIES ARIES 4128
+cancer MACH_CANCER CANCER 4129
+leo MACH_LEO LEO 4130
+virgo MACH_VIRGO VIRGO 4131
+sagittarius MACH_SAGITTARIUS SAGITTARIUS 4132
+devil MACH_DEVIL DEVIL 4133
+ballantines MACH_BALLANTINES BALLANTINES 4134
+omap3_procerusvpu MACH_OMAP3_PROCERUSVPU OMAP3_PROCERUSVPU 4135
+my27 MACH_MY27 MY27 4136
+sun6i MACH_SUN6I SUN6I 4137
+sun5i MACH_SUN5I SUN5I 4138
+mx512_mx MACH_MX512_MX MX512_MX 4139
+kzm9g MACH_KZM9G KZM9G 4140
+vdstbn MACH_VDSTBN VDSTBN 4141
+cfa10036 MACH_CFA10036 CFA10036 4142
+cfa10049 MACH_CFA10049 CFA10049 4143
+pcm051 MACH_PCM051 PCM051 4144
+vybrid_vf7xx MACH_VYBRID_VF7XX VYBRID_VF7XX 4145
+vybrid_vf6xx MACH_VYBRID_VF6XX VYBRID_VF6XX 4146
+vybrid_vf5xx MACH_VYBRID_VF5XX VYBRID_VF5XX 4147
+vybrid_vf4xx MACH_VYBRID_VF4XX VYBRID_VF4XX 4148
+aria_g25 MACH_ARIA_G25 ARIA_G25 4149
+bcm21553 MACH_BCM21553 BCM21553 4150
+smdk5410 MACH_SMDK5410 SMDK5410 4151
+lpc18xx MACH_LPC18XX LPC18XX 4152
+oratisparty MACH_ORATISPARTY ORATISPARTY 4153
+qseven MACH_QSEVEN QSEVEN 4154
+gmv_generic MACH_GMV_GENERIC GMV_GENERIC 4155
+th_link_eth MACH_TH_LINK_ETH TH_LINK_ETH 4156
+tn_muninn MACH_TN_MUNINN TN_MUNINN 4157
+rampage MACH_RAMPAGE RAMPAGE 4158
+visstrim_mv10 MACH_VISSTRIM_MV10 VISSTRIM_MV10 4159
+mx28_wilma MACH_MX28_WILMA MX28_WILMA 4164
+msm8625_ffa MACH_MSM8625_FFA MSM8625_FFA 4166
+vpu101 MACH_VPU101 VPU101 4167
+baileys MACH_BAILEYS BAILEYS 4169
+familybox MACH_FAMILYBOX FAMILYBOX 4170
+ensemble_mx35 MACH_ENSEMBLE_MX35 ENSEMBLE_MX35 4171
+sc_sps_1 MACH_SC_SPS_1 SC_SPS_1 4172
{
int i;
- printk(KERN_ERR "VFP: Error: %s\n", reason);
- printk(KERN_ERR "VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n",
+ pr_err("VFP: Error: %s\n", reason);
+ pr_err("VFP: EXC 0x%08x SCR 0x%08x INST 0x%08x\n",
fmrx(FPEXC), fmrx(FPSCR), inst);
for (i = 0; i < 32; i += 2)
- printk(KERN_ERR "VFP: s%2u: 0x%08x s%2u: 0x%08x\n",
+ pr_err("VFP: s%2u: 0x%08x s%2u: 0x%08x\n",
i, vfp_get_float(i), i+1, vfp_get_float(i+1));
}
/* if vfp is on, then save state for resumption */
if (fpexc & FPEXC_EN) {
- printk(KERN_DEBUG "%s: saving vfp state\n", __func__);
+ pr_debug("%s: saving vfp state\n", __func__);
vfp_save_state(&ti->vfpstate, fpexc);
/* disable, just in case */
barrier();
vfp_vector = vfp_null_entry;
- printk(KERN_INFO "VFP support v0.3: ");
+ pr_info("VFP support v0.3: ");
if (VFP_arch)
- printk("not present\n");
+ pr_cont("not present\n");
else if (vfpsid & FPSID_NODOUBLE) {
- printk("no double precision support\n");
+ pr_cont("no double precision support\n");
} else {
hotcpu_notifier(vfp_hotplug, 0);
VFP_arch = (vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT; /* Extract the architecture version */
- printk("implementor %02x architecture %d part %02x variant %x rev %x\n",
+ pr_cont("implementor %02x architecture %d part %02x variant %x rev %x\n",
(vfpsid & FPSID_IMPLEMENTER_MASK) >> FPSID_IMPLEMENTER_BIT,
(vfpsid & FPSID_ARCH_MASK) >> FPSID_ARCH_BIT,
(vfpsid & FPSID_PART_MASK) >> FPSID_PART_BIT,
if (ret)
goto err_release;
- if (dev->irq[0] && dev->irq[0] != NO_IRQ)
+ if (dev->irq[0])
ret = device_create_file(&dev->dev, &dev_attr_irq0);
- if (ret == 0 && dev->irq[1] && dev->irq[1] != NO_IRQ)
+ if (ret == 0 && dev->irq[1])
ret = device_create_file(&dev->dev, &dev_attr_irq1);
if (ret == 0)
return ret;
}
EXPORT_SYMBOL_GPL(amba_device_add);
+static struct amba_device *
+amba_aphb_device_add(struct device *parent, const char *name,
+ resource_size_t base, size_t size, int irq1, int irq2,
+ void *pdata, unsigned int periphid, u64 dma_mask)
+{
+ struct amba_device *dev;
+ int ret;
+
+ dev = amba_device_alloc(name, base, size);
+ if (!dev)
+ return ERR_PTR(-ENOMEM);
+
+ dev->dma_mask = dma_mask;
+ dev->dev.coherent_dma_mask = dma_mask;
+ dev->irq[0] = irq1;
+ dev->irq[1] = irq2;
+ dev->periphid = periphid;
+ dev->dev.platform_data = pdata;
+ dev->dev.parent = parent;
+
+ ret = amba_device_add(dev, &iomem_resource);
+ if (ret) {
+ amba_device_put(dev);
+ return ERR_PTR(ret);
+ }
+
+ return dev;
+}
+
+struct amba_device *
+amba_apb_device_add(struct device *parent, const char *name,
+ resource_size_t base, size_t size, int irq1, int irq2,
+ void *pdata, unsigned int periphid)
+{
+ return amba_aphb_device_add(parent, name, base, size, irq1, irq2, pdata,
+ periphid, 0);
+}
+EXPORT_SYMBOL_GPL(amba_apb_device_add);
+
+struct amba_device *
+amba_ahb_device_add(struct device *parent, const char *name,
+ resource_size_t base, size_t size, int irq1, int irq2,
+ void *pdata, unsigned int periphid)
+{
+ return amba_aphb_device_add(parent, name, base, size, irq1, irq2, pdata,
+ periphid, ~0ULL);
+}
+EXPORT_SYMBOL_GPL(amba_ahb_device_add);
+
static void amba_device_initialize(struct amba_device *dev, const char *name)
{
device_initialize(&dev->dev);
.signal_direction = true,
};
+static struct variant_data variant_nomadik = {
+ .fifosize = 16 * 4,
+ .fifohalfsize = 8 * 4,
+ .clkreg = MCI_CLK_ENABLE,
+ .datalength_bits = 24,
+ .sdio = true,
+ .st_clkdiv = true,
+ .pwrreg_powerup = MCI_PWR_ON,
+ .signal_direction = true,
+};
+
static struct variant_data variant_ux500 = {
.fifosize = 30 * 4,
.fifohalfsize = 8 * 4,
if (ret)
goto unmap;
- if (dev->irq[1] == NO_IRQ || !dev->irq[1])
+ if (!dev->irq[1])
host->singleirq = true;
else {
ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
.mask = 0x00ffffff,
.data = &variant_u300,
},
+ {
+ .id = 0x10180180,
+ .mask = 0xf0ffffff,
+ .data = &variant_nomadik,
+ },
{
.id = 0x00280180,
.mask = 0x00ffffff,
void amba_device_put(struct amba_device *);
int amba_device_add(struct amba_device *, struct resource *);
int amba_device_register(struct amba_device *, struct resource *);
+struct amba_device *amba_apb_device_add(struct device *parent, const char *name,
+ resource_size_t base, size_t size,
+ int irq1, int irq2, void *pdata,
+ unsigned int periphid);
+struct amba_device *amba_ahb_device_add(struct device *parent, const char *name,
+ resource_size_t base, size_t size,
+ int irq1, int irq2, void *pdata,
+ unsigned int periphid);
void amba_device_unregister(struct amba_device *);
struct amba_device *amba_find_device(const char *, struct device *, unsigned int, unsigned int);
int amba_request_regions(struct amba_device *, const char *);
git.openpandora.org / pandora-kernel.git / commitdiff