[POWERPC] 8xx: platform specific mmu updates

This is just a straight port of the same done in arch/ppc
by Marcelo Tosatti. One used to be
[PATCH] ppc32 8xx: update_mmu_cache() needs unconditional tlbie,
commit eb07d964b4491d1bb5864cd3d7e7633ccdda9a53

In a nutshell, the board is nearly stuck without this, yet without any
visible failure - being just very slow.

Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>

diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c
index d1c0758..c85eda6 100644 (file)
--- a/arch/powerpc/mm/mem.c
+++ b/arch/powerpc/mm/mem.c
@@ -490,19 +490,19 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
            !cpu_has_feature(CPU_FTR_NOEXECUTE) &&
            pfn_valid(pfn)) {
                struct page *page = pfn_to_page(pfn);
+#ifdef CONFIG_8xx
+               /* On 8xx, cache control instructions (particularly
+                * "dcbst" from flush_dcache_icache) fault as write
+                * operation if there is an unpopulated TLB entry
+                * for the address in question. To workaround that,
+                * we invalidate the TLB here, thus avoiding dcbst
+                * misbehaviour.
+                */
+               _tlbie(address);
+#endif
                if (!PageReserved(page)
                    && !test_bit(PG_arch_1, &page->flags)) {
                        if (vma->vm_mm == current->active_mm) {
-#ifdef CONFIG_8xx
-                       /* On 8xx, cache control instructions (particularly 
-                        * "dcbst" from flush_dcache_icache) fault as write 
-                        * operation if there is an unpopulated TLB entry 
-                        * for the address in question. To workaround that, 
-                        * we invalidate the TLB here, thus avoiding dcbst 
-                        * misbehaviour.
-                        */
-                               _tlbie(address);
-#endif
                                __flush_dcache_icache((void *) address);
                        } else
                                flush_dcache_icache_page(page);