[MIPS] SMTC: Microoptimize atomic_postincrement for non-weak consistency.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index fe22387..137183b 100644 (file)
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -713,7 +713,7 @@ static __inline__ int atomic_postincrement(unsigned int *pv)
        "       addu    %1, %0, 1                               \n"
        "       sc      %1, %2                                  \n"
        "       beqz    %1, 1b                                  \n"
-       "       sync                                            \n"
+       __WEAK_LLSC_MB
        : "=&r" (result), "=&r" (temp), "=m" (*pv)
        : "m" (*pv)
        : "memory");